From 750b5be5d3f884e54f4a078b05b844a0e0b533de Mon Sep 17 00:00:00 2001
From: Anthony Donlon <4056887+donlon@users.noreply.github.com>
Date: Mon, 25 Sep 2023 22:40:44 +0800
Subject: [PATCH] Remove support for parameterized UDPs (#4518)

---
 src/verilog.y                      |  7 +++----
 test_regress/t/t_udp_param_bad.out |  7 +++++++
 test_regress/t/t_udp_param_bad.pl  | 19 +++++++++++++++++++
 test_regress/t/t_udp_param_bad.v   | 22 ++++++++++++++++++++++
 4 files changed, 51 insertions(+), 4 deletions(-)
 create mode 100644 test_regress/t/t_udp_param_bad.out
 create mode 100755 test_regress/t/t_udp_param_bad.pl
 create mode 100644 test_regress/t/t_udp_param_bad.v

diff --git a/src/verilog.y b/src/verilog.y
index cdc6682e9..134494488 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1346,16 +1346,15 @@ module_declaration:             // ==IEEE: module_declaration
                           GRAMMARP->m_modp = nullptr;
                           SYMP->popScope($1);
                           GRAMMARP->endLabel($<fl>7, $1, $7); }
-        |       udpFront parameter_port_listE portsStarE ';'
+        |       udpFront portsStarE ';'
         /*cont*/    module_itemListE yENDPRIMITIVE endLabelE
                         { $1->modTrace(false);  // Stash for implicit wires, etc
                           if ($2) $1->addStmtsp($2);
-                          if ($3) $1->addStmtsp($3);
-                          if ($5) $1->addStmtsp($5);
+                          if ($4) $1->addStmtsp($4);
                           GRAMMARP->m_tracingParse = true;
                           GRAMMARP->m_modp = nullptr;
                           SYMP->popScope($1);
-                          GRAMMARP->endLabel($<fl>7, $1, $7); }
+                          GRAMMARP->endLabel($<fl>6, $1, $6); }
         //
         |       yEXTERN modFront parameter_port_listE portsStarE ';'
                         { BBUNSUP($<fl>1, "Unsupported: extern module"); }
diff --git a/test_regress/t/t_udp_param_bad.out b/test_regress/t/t_udp_param_bad.out
new file mode 100644
index 000000000..cd3152a08
--- /dev/null
+++ b/test_regress/t/t_udp_param_bad.out
@@ -0,0 +1,7 @@
+%Error: t/t_udp_param_bad.v:12:15: syntax error, unexpected '#', expecting ';'
+   12 | primitive udp #(
+      |               ^
+%Error: t/t_udp_param_bad.v:14:1: syntax error, unexpected ')', expecting ';'
+   14 | ) (o, a);
+      | ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_udp_param_bad.pl b/test_regress/t/t_udp_param_bad.pl
new file mode 100755
index 000000000..a60503a1f
--- /dev/null
+++ b/test_regress/t/t_udp_param_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_udp_param_bad.v b/test_regress/t/t_udp_param_bad.v
new file mode 100644
index 000000000..8ac68827e
--- /dev/null
+++ b/test_regress/t/t_udp_param_bad.v
@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Anthony Donlon.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   wire a, b;
+   udp i_udp (a, b);
+endmodule
+
+primitive udp #(
+    parameter A = 1
+) (o, a);
+   output o;
+   input  a;
+   table
+      //o a
+      0 :  1;
+      1 :  0;
+   endtable
+endprimitive