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consolidate t_multidriven_simple

This commit is contained in:
em2machine 2025-12-22 17:28:55 +01:00
parent 87cfd53949
commit 74c7d598cb
11 changed files with 120 additions and 386 deletions
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0
test_regress/t/t_multidriven_simple0.py → test_regress/t/t_multidriven_simple.py
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120
test_regress/t/t_multidriven_simple.v Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
// direct task call
module mod0 #()(
input logic sel,
output logic val
);
logic l0;
task do_stuff();
l0 = 'b1;
endtask
always_comb begin
l0 = 'b0;
if(sel) begin
do_stuff();
end
end
assign val = l0;
endmodule
// nested task call chain
module mod1 #()(
input logic sel,
output logic val
);
logic l0;
task do_inner();
l0 = 'b1;
endtask
task do_outer();
do_inner();
endtask
always_comb begin
l0 = 'b0;
if (sel) do_outer();
end
assign val = l0;
endmodule
// task writes through an output arguement
module mod2 #()(
input logic sel,
output logic val
);
logic l0;
task automatic do_stuff(output logic q);
q = 1'b1;
endtask
always_comb begin
l0 = 1'b0;
if (sel) do_stuff(l0);
end
assign val = l0;
endmodule
// function call that writes
module mod3 #()(
input logic sel,
output logic val
);
logic l0;
function automatic void do_func();
l0 = 1'b1;
endfunction
always_comb begin
l0 = 1'b0;
if (sel) do_func();
end
assign val = l0;
endmodule
// two tasks set0/set1
module mod4 #()(
input logic sel,
output logic val
);
logic l0;
task automatic set1(); l0 = 1'b1; endtask
task automatic set0(); l0 = 1'b0; endtask
always_comb begin
set0();
if (sel) begin
set1();
end
end
assign val = l0;
endmodule
module m_tb;
logic sel;
logic v0, v1, v2, v3, v4;
mod0 u0(.sel(sel), .val(v0));
mod1 u1(.sel(sel), .val(v1));
mod2 u2(.sel(sel), .val(v2));
mod3 u3(.sel(sel), .val(v3));
mod4 u4(.sel(sel), .val(v4));
initial begin
#1; sel = 0;
`checkd(v0, 0); `checkd(v1, 0); `checkd(v2, 0); `checkd(v3, 0); `checkd(v4, 0);
#1; sel = 1;
`checkd(v0, 1); `checkd(v1, 1); `checkd(v2, 1); `checkd(v3, 1); `checkd(v4, 1);
#1; sel = 0;
`checkd(v0, 0); `checkd(v1, 0); `checkd(v2, 0); `checkd(v3, 0); `checkd(v4, 0);
#1;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

63
test_regress/t/t_multidriven_simple0.v
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@ -1,63 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
module mod #()(
input logic sel
,output logic val
);
logic l0;
task do_stuff();
l0 = 'b1;
endtask
always_comb begin
l0 = 'b0;
if(sel) begin
do_stuff();
end
end
assign val = l0;
endmodule
module m_tb#()();
logic sel, val;
mod m(
.sel(sel)
,.val(val)
);
initial begin
#1;
sel = 'b0;
`checkd(val, 1'b0);
#1;
sel = 'b1;
`checkd(val, 1'b1);
#1;
sel = 'b0;
`checkd(val, 1'b0);
#1;
end
initial begin
#5;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_multidriven_simple1.py
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=["--binary"])
test.execute()
test.passes()

66
test_regress/t/t_multidriven_simple1.v
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@ -1,66 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// task chain - testing nested task calls
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
module mod #()(
input logic sel
,output logic val
);
logic l0;
task do_inner();
l0 = 'b1;
endtask
task do_outer();
do_inner();
endtask
always_comb begin
l0 = 'b0;
if (sel) do_outer();
end
assign val = l0;
endmodule
module m_tb#()();
logic sel, val;
mod m(
.sel(sel)
,.val(val)
);
initial begin
#1;
sel = 'b0;
`checkd(val, 1'b0);
#1;
sel = 'b1;
`checkd(val, 1'b1);
#1;
sel = 'b0;
`checkd(val, 1'b0);
#1;
end
initial begin
#5;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_multidriven_simple2.py
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=["--binary"])
test.execute()
test.passes()

62
test_regress/t/t_multidriven_simple2.v
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@ -1,62 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// task writes through an argument (output argument of a task)
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
module mod #()(
input logic sel
,output logic val
);
logic l0;
task automatic do_stuff(output logic q);
q = 1'b1;
endtask
always_comb begin
l0 = 1'b0;
if (sel) do_stuff(l0);
end
assign val = l0;
endmodule
module m_tb#()();
logic sel, val;
mod m(
.sel(sel)
,.val(val)
);
initial begin
#1;
sel = 'b0;
`checkd(val, 1'b0);
#1;
sel = 'b1;
`checkd(val, 1'b1);
#1;
sel = 'b0;
`checkd(val, 1'b0);
#1;
end
initial begin
#5;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

18
test_regress/t/t_multidriven_simple3.py
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@ -1,18 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=["--binary"])
test.execute()
test.passes()

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test_regress/t/t_multidriven_simple3.v
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@ -1,62 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// function call that writes
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
module mod #()(
input logic sel
,output logic val
);
logic l0;
function automatic void do_func();
l0 = 1'b1;
endfunction
always_comb begin
l0 = 1'b0;
if (sel) do_func();
end
assign val = l0;
endmodule
module m_tb#()();
logic sel, val;
mod m(
.sel(sel)
,.val(val)
);
initial begin
#1;
sel = 'b0;
`checkd(val, 1'b0);
#1;
sel = 'b1;
`checkd(val, 1'b1);
#1;
sel = 'b0;
`checkd(val, 1'b0);
#1;
end
initial begin
#5;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

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test_regress/t/t_multidriven_simple4.py
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@ -1,18 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=["--binary"])
test.execute()
test.passes()

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test_regress/t/t_multidriven_simple4.v
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@ -1,61 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
module mod #()(
input logic sel
,output logic val
);
logic l0;
task automatic set1(); l0 = 1'b1; endtask
task automatic set0(); l0 = 1'b0; endtask
always_comb begin
set0();
if (sel) begin
set1();
end
end
assign val = l0;
endmodule
module m_tb#()();
logic sel, val;
mod m(
.sel(sel)
,.val(val)
);
initial begin
#1;
sel = 'b0;
`checkd(val, 1'b0);
#1;
sel = 'b1;
`checkd(val, 1'b1);
#1;
sel = 'b0;
`checkd(val, 1'b0);
#1;
end
initial begin
#5;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule