From 74c7d598cb9f27228592d5f38fd61461433982ec Mon Sep 17 00:00:00 2001 From: em2machine <92717390+em2machine@users.noreply.github.com> Date: Mon, 22 Dec 2025 17:28:55 +0100 Subject: [PATCH] consolidate t_multidriven_simple --- ...ven_simple0.py => t_multidriven_simple.py} | 0 test_regress/t/t_multidriven_simple.v | 120 ++++++++++++++++++ test_regress/t/t_multidriven_simple0.v | 63 --------- test_regress/t/t_multidriven_simple1.py | 18 --- test_regress/t/t_multidriven_simple1.v | 66 ---------- test_regress/t/t_multidriven_simple2.py | 18 --- test_regress/t/t_multidriven_simple2.v | 62 --------- test_regress/t/t_multidriven_simple3.py | 18 --- test_regress/t/t_multidriven_simple3.v | 62 --------- test_regress/t/t_multidriven_simple4.py | 18 --- test_regress/t/t_multidriven_simple4.v | 61 --------- 11 files changed, 120 insertions(+), 386 deletions(-) rename test_regress/t/{t_multidriven_simple0.py => t_multidriven_simple.py} (100%) create mode 100644 test_regress/t/t_multidriven_simple.v delete mode 100644 test_regress/t/t_multidriven_simple0.v delete mode 100755 test_regress/t/t_multidriven_simple1.py delete mode 100644 test_regress/t/t_multidriven_simple1.v delete mode 100755 test_regress/t/t_multidriven_simple2.py delete mode 100644 test_regress/t/t_multidriven_simple2.v delete mode 100755 test_regress/t/t_multidriven_simple3.py delete mode 100644 test_regress/t/t_multidriven_simple3.v delete mode 100755 test_regress/t/t_multidriven_simple4.py delete mode 100644 test_regress/t/t_multidriven_simple4.v diff --git a/test_regress/t/t_multidriven_simple0.py b/test_regress/t/t_multidriven_simple.py similarity index 100% rename from test_regress/t/t_multidriven_simple0.py rename to test_regress/t/t_multidriven_simple.py diff --git a/test_regress/t/t_multidriven_simple.v b/test_regress/t/t_multidriven_simple.v new file mode 100644 index 000000000..e1a240578 --- /dev/null +++ b/test_regress/t/t_multidriven_simple.v @@ -0,0 +1,120 @@ + +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +// direct task call +module mod0 #()( + input logic sel, + output logic val +); + logic l0; + task do_stuff(); + l0 = 'b1; + endtask + always_comb begin + l0 = 'b0; + if(sel) begin + do_stuff(); + end + end + assign val = l0; +endmodule + +// nested task call chain +module mod1 #()( + input logic sel, + output logic val +); + logic l0; + task do_inner(); + l0 = 'b1; + endtask + task do_outer(); + do_inner(); + endtask + always_comb begin + l0 = 'b0; + if (sel) do_outer(); + end + assign val = l0; +endmodule + +// task writes through an output arguement +module mod2 #()( + input logic sel, + output logic val +); + logic l0; + task automatic do_stuff(output logic q); + q = 1'b1; + endtask + always_comb begin + l0 = 1'b0; + if (sel) do_stuff(l0); + end + assign val = l0; +endmodule + +// function call that writes +module mod3 #()( + input logic sel, + output logic val +); + logic l0; + function automatic void do_func(); + l0 = 1'b1; + endfunction + always_comb begin + l0 = 1'b0; + if (sel) do_func(); + end + assign val = l0; +endmodule + +// two tasks set0/set1 +module mod4 #()( + input logic sel, + output logic val +); + logic l0; + task automatic set1(); l0 = 1'b1; endtask + task automatic set0(); l0 = 1'b0; endtask + always_comb begin + set0(); + if (sel) begin + set1(); + end + end + assign val = l0; +endmodule + +module m_tb; + logic sel; + logic v0, v1, v2, v3, v4; + + mod0 u0(.sel(sel), .val(v0)); + mod1 u1(.sel(sel), .val(v1)); + mod2 u2(.sel(sel), .val(v2)); + mod3 u3(.sel(sel), .val(v3)); + mod4 u4(.sel(sel), .val(v4)); + + initial begin + #1; sel = 0; + `checkd(v0, 0); `checkd(v1, 0); `checkd(v2, 0); `checkd(v3, 0); `checkd(v4, 0); + #1; sel = 1; + `checkd(v0, 1); `checkd(v1, 1); `checkd(v2, 1); `checkd(v3, 1); `checkd(v4, 1); + #1; sel = 0; + `checkd(v0, 0); `checkd(v1, 0); `checkd(v2, 0); `checkd(v3, 0); `checkd(v4, 0); + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_multidriven_simple0.v b/test_regress/t/t_multidriven_simple0.v deleted file mode 100644 index 66a50beed..000000000 --- a/test_regress/t/t_multidriven_simple0.v +++ /dev/null @@ -1,63 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - - task do_stuff(); - l0 = 'b1; - endtask - - always_comb begin - l0 = 'b0; - - if(sel) begin - do_stuff(); - end - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - `checkd(val, 1'b0); - #1; - sel = 'b1; - `checkd(val, 1'b1); - #1; - sel = 'b0; - `checkd(val, 1'b0); - #1; - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_multidriven_simple1.py b/test_regress/t/t_multidriven_simple1.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_multidriven_simple1.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_multidriven_simple1.v b/test_regress/t/t_multidriven_simple1.v deleted file mode 100644 index ef5e9d164..000000000 --- a/test_regress/t/t_multidriven_simple1.v +++ /dev/null @@ -1,66 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// task chain - testing nested task calls - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - - task do_inner(); - l0 = 'b1; - endtask - - task do_outer(); - do_inner(); - endtask - - always_comb begin - l0 = 'b0; - if (sel) do_outer(); - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - `checkd(val, 1'b0); - #1; - sel = 'b1; - `checkd(val, 1'b1); - #1; - sel = 'b0; - `checkd(val, 1'b0); - #1; - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_multidriven_simple2.py b/test_regress/t/t_multidriven_simple2.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_multidriven_simple2.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_multidriven_simple2.v b/test_regress/t/t_multidriven_simple2.v deleted file mode 100644 index 15f80e1e5..000000000 --- a/test_regress/t/t_multidriven_simple2.v +++ /dev/null @@ -1,62 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// task writes through an argument (output argument of a task) - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - - task automatic do_stuff(output logic q); - q = 1'b1; - endtask - - always_comb begin - l0 = 1'b0; - if (sel) do_stuff(l0); - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - `checkd(val, 1'b0); - #1; - sel = 'b1; - `checkd(val, 1'b1); - #1; - sel = 'b0; - `checkd(val, 1'b0); - #1; - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_multidriven_simple3.py b/test_regress/t/t_multidriven_simple3.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_multidriven_simple3.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_multidriven_simple3.v b/test_regress/t/t_multidriven_simple3.v deleted file mode 100644 index 7ea624d45..000000000 --- a/test_regress/t/t_multidriven_simple3.v +++ /dev/null @@ -1,62 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// function call that writes - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - -function automatic void do_func(); - l0 = 1'b1; -endfunction - -always_comb begin - l0 = 1'b0; - if (sel) do_func(); -end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - `checkd(val, 1'b0); - #1; - sel = 'b1; - `checkd(val, 1'b1); - #1; - sel = 'b0; - `checkd(val, 1'b0); - #1; - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_multidriven_simple4.py b/test_regress/t/t_multidriven_simple4.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_multidriven_simple4.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_multidriven_simple4.v b/test_regress/t/t_multidriven_simple4.v deleted file mode 100644 index 475c8589b..000000000 --- a/test_regress/t/t_multidriven_simple4.v +++ /dev/null @@ -1,61 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. -// SPDX-License-Identifier: CC0-1.0 - -// verilog_format: off -`define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); -// verilog_format: on - -module mod #()( - input logic sel - ,output logic val -); - - logic l0; - - task automatic set1(); l0 = 1'b1; endtask - task automatic set0(); l0 = 1'b0; endtask - - always_comb begin - set0(); - if (sel) begin - set1(); - end - end - - assign val = l0; - -endmodule - -module m_tb#()(); - - logic sel, val; - - mod m( - .sel(sel) - ,.val(val) - ); - - initial begin - #1; - sel = 'b0; - `checkd(val, 1'b0); - #1; - sel = 'b1; - `checkd(val, 1'b1); - #1; - sel = 'b0; - `checkd(val, 1'b0); - #1; - end - - initial begin - #5; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule