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Internals/Tests: Cleanup some missing dev coverage items

This commit is contained in:
Wilson Snyder 2025-10-11 12:54:55 -04:00
parent 078275034d
commit 6e8bd3da19
21 changed files with 1289 additions and 963 deletions
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1
Makefile.in
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@ -655,6 +655,7 @@ GENHTML := genhtml
GENHTML_OPT := -j $(shell nproc) GENHTML_OPT := -j $(shell nproc)
GENHTML_OPT += --branch-coverage GENHTML_OPT += --branch-coverage
GENHTML_OPT += --demangle-cpp GENHTML_OPT += --demangle-cpp
GENHTML_OPT += --missed
GENHTML_OPT += --rc branch_coverage=1 GENHTML_OPT += --rc branch_coverage=1
GENHTML_OPT += --rc genhtml_hi_limit=100 GENHTML_OPT += --rc genhtml_hi_limit=100
GENHTML_OPT += --ignore-errors negative GENHTML_OPT += --ignore-errors negative

2
include/verilated_random.h
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@ -111,7 +111,7 @@ public:
return it->second->m_datap; return it->second->m_datap;
} else { } else {
VL_FATAL_MT(__FILE__, __LINE__, "randomize", "indexed_name not found in m_arr_vars"); VL_FATAL_MT(__FILE__, __LINE__, "randomize", "indexed_name not found in m_arr_vars");
return nullptr; return nullptr; // LCOV_EXCL_BR_LINE
} }
} }
void emitHexs(std::ostream& s, const std::vector<IData>& indices, const size_t bit_width, void emitHexs(std::ostream& s, const std::vector<IData>& indices, const size_t bit_width,

2
include/verilated_trace.h
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@ -531,7 +531,7 @@ public:
} }
VL_ATTR_ALWINLINE void chgEventTriggered(uint32_t* oldp) { fullEventTriggered(oldp); } VL_ATTR_ALWINLINE void chgEventTriggered(uint32_t* oldp) { fullEventTriggered(oldp); }
VL_ATTR_ALWINLINE void chgDouble(uint32_t* oldp, double newval) { VL_ATTR_ALWINLINE void chgDouble(uint32_t* oldp, double newval) {
double old; double old; // LCOV_EXCL_LINE // lcov bug
std::memcpy(&old, oldp, sizeof(old)); std::memcpy(&old, oldp, sizeof(old));
if (VL_UNLIKELY(old != newval)) fullDouble(oldp, newval); if (VL_UNLIKELY(old != newval)) fullDouble(oldp, newval);
} }

20
include/verilated_vpi.cpp
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@ -2399,7 +2399,7 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c
case VLVT_UINT32: case VLVT_UINT32:
case VLVT_UINT64: case VLVT_UINT64:
case VLVT_WDATA: return status; case VLVT_WDATA: return status;
default: status = false; default: status = false; // LCOV_EXCL_LINE
} }
} else if (valuep->format == vpiDecStrVal) { } else if (valuep->format == vpiDecStrVal) {
switch (varp->vltype()) { switch (varp->vltype()) {
@ -2407,7 +2407,7 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c
case VLVT_UINT16: case VLVT_UINT16:
case VLVT_UINT32: case VLVT_UINT32:
case VLVT_UINT64: return status; case VLVT_UINT64: return status;
default: status = false; default: status = false; // LCOV_EXCL_LINE
} }
} else if (valuep->format == vpiStringVal) { } else if (valuep->format == vpiStringVal) {
switch (varp->vltype()) { switch (varp->vltype()) {
@ -2424,7 +2424,7 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c
status = false; status = false;
break; break;
} }
default: status = false; default: status = false; // LCOV_EXCL_LINE
} }
} else if (valuep->format == vpiIntVal) { } else if (valuep->format == vpiIntVal) {
switch (varp->vltype()) { switch (varp->vltype()) {
@ -2433,12 +2433,12 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c
case VLVT_UINT32: case VLVT_UINT32:
case VLVT_UINT64: case VLVT_UINT64:
case VLVT_WDATA: return status; case VLVT_WDATA: return status;
default: status = false; default: status = false; // LCOV_EXCL_LINE
} }
} else if (valuep->format == vpiRealVal) { } else if (valuep->format == vpiRealVal) {
switch (varp->vltype()) { switch (varp->vltype()) {
case VLVT_REAL: return status; case VLVT_REAL: return status;
default: status = false; default: status = false; // LCOV_EXCL_LINE
} }
} else if (valuep->format == vpiSuppressVal) { } else if (valuep->format == vpiSuppressVal) {
return status; return status;
@ -2919,14 +2919,14 @@ bool vl_check_array_format(const VerilatedVar* varp, const p_vpi_arrayvalue arra
case VLVT_UINT32: case VLVT_UINT32:
case VLVT_UINT64: case VLVT_UINT64:
case VLVT_WDATA: return true; case VLVT_WDATA: return true;
default:; default:; // LCOV_EXCL_LINE
} }
} else if (arrayvalue_p->format == vpiIntVal) { } else if (arrayvalue_p->format == vpiIntVal) {
switch (varp->vltype()) { switch (varp->vltype()) {
case VLVT_UINT8: case VLVT_UINT8:
case VLVT_UINT16: case VLVT_UINT16:
case VLVT_UINT32: return true; case VLVT_UINT32: return true;
default:; default:; // LCOV_EXCL_LINE
} }
} else if ((arrayvalue_p->format == vpiRawTwoStateVal) } else if ((arrayvalue_p->format == vpiRawTwoStateVal)
|| (arrayvalue_p->format == vpiRawFourStateVal)) { || (arrayvalue_p->format == vpiRawFourStateVal)) {
@ -2936,13 +2936,13 @@ bool vl_check_array_format(const VerilatedVar* varp, const p_vpi_arrayvalue arra
case VLVT_UINT32: case VLVT_UINT32:
case VLVT_UINT64: case VLVT_UINT64:
case VLVT_WDATA: return true; case VLVT_WDATA: return true;
default:; default:; // LCOV_EXCL_LINE
} }
} else if (arrayvalue_p->format == vpiShortIntVal) { } else if (arrayvalue_p->format == vpiShortIntVal) {
switch (varp->vltype()) { switch (varp->vltype()) {
case VLVT_UINT8: case VLVT_UINT8:
case VLVT_UINT16: return true; case VLVT_UINT16: return true;
default:; default:; // LCOV_EXCL_LINE
} }
} else if (arrayvalue_p->format == vpiLongIntVal) { } else if (arrayvalue_p->format == vpiLongIntVal) {
switch (varp->vltype()) { switch (varp->vltype()) {
@ -2950,7 +2950,7 @@ bool vl_check_array_format(const VerilatedVar* varp, const p_vpi_arrayvalue arra
case VLVT_UINT16: case VLVT_UINT16:
case VLVT_UINT32: case VLVT_UINT32:
case VLVT_UINT64: return true; case VLVT_UINT64: return true;
default:; default:; // LCOV_EXCL_LINE
} }
} }

16
test_regress/t/t_attr.py Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.lint()
test.passes()

16
test_regress/t/t_attr.v Normal file
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@ -0,0 +1,16 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2011 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
(* attr_name1 *)
(* attr_name1 = val1 *)
(* attr_name1 = val1, attr_name2 *)
(* attr_name1 = val1, attr_name2=1 *)
initial $finish;
endmodule

20
test_regress/t/t_dpi_export_scope_bad.cpp
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@ -7,7 +7,6 @@
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
#include <verilated.h> #include <verilated.h>
#include VM_PREFIX_INCLUDE
//====================================================================== //======================================================================
@ -21,25 +20,6 @@ extern void dpix_task();
//====================================================================== //======================================================================
unsigned int main_time = 0;
double sc_time_stamp() { return main_time; }
VM_PREFIX* topp = nullptr;
int main(int argc, char* argv[]) {
Verilated::debug(0);
Verilated::commandArgs(argc, argv);
topp = new VM_PREFIX;
topp->eval();
topp->final();
VL_DO_DANGLING(delete topp, topp);
return 1;
}
void dpix_run_tests() { void dpix_run_tests() {
dpix_task(); // Wrong scope dpix_task(); // Wrong scope
} }

2
test_regress/t/t_dpi_export_scope_bad.out
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@ -1,2 +1,2 @@
%Error: unknown:0: Testbench C called 'dpix_task' but this DPI export function exists only in other scopes, not scope 'TOP.t' %Error: unknown:0: Testbench C called 'dpix_task' but this DPI export function exists only in other scopes, not scope 't'
Aborting... Aborting...

2
test_regress/t/t_dpi_export_scope_bad.py
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@ -11,7 +11,7 @@ import vltest_bootstrap
test.scenarios('simulator') test.scenarios('simulator')
test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) test.compile(v_flags2=["--binary", test.pli_filename])
test.execute(fails=True, expect_filename=test.golden_filename) test.execute(fails=True, expect_filename=test.golden_filename)

42
test_regress/t/t_gate_array.v
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@ -4,11 +4,9 @@
// any use, without warranty, 2014 by Wilson Snyder. // any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk
); );
input clk;
integer cyc = 0; integer cyc = 0;
reg [63:0] crc; reg [63:0] crc;
@ -21,11 +19,13 @@ module t (/*AUTOARG*/
/*AUTOWIRE*/ /*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs) // Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] out; // From test of Test.v wire [63:0] out; // From test of Test.v
wire [63:0] out2; // From test of Test.v
// End of automatics // End of automatics
Test test ( /*AUTOINST*/ Test test ( /*AUTOINST*/
// Outputs // Outputs
.out (out[63:0]), .out (out[63:0]),
.out2 (out2[63:0]),
// Inputs // Inputs
.clk (clk), .clk (clk),
.a (a[7:0]), .a (a[7:0]),
@ -51,6 +51,7 @@ module t (/*AUTOARG*/
sum <= 64'h0; sum <= 64'h0;
end end
else if (cyc < 90) begin else if (cyc < 90) begin
if (out2 !== out) $stop;
end end
else if (cyc == 99) begin else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
@ -65,25 +66,22 @@ module t (/*AUTOARG*/
endmodule endmodule
module Test (/*AUTOARG*/ module Test (
// Outputs input clk,
out, input [7:0] a,
// Inputs input [7:0] b,
clk, a, b output reg [63:0] out,
output reg [63:0] out2
); );
input clk; // Also cover comma syntax
input [7:0] a; and u0a[7:0] (out[7:0], a[7:0], b[7:0]), u0b[7:0] (out2[7:0], a[7:0], b[7:0]);
input [7:0] b; and u1a[7:0] (out[15:8], a[0], b[7:0]), u1b[7:0] (out2[15:8], a[0], b[7:0]);
output reg [63:0] out; and u2a[7:0] (out[23:16], a[0], b[0]), u2b[7:0] (out2[23:16], a[0], b[0]);
nand u3a[7:0] (out[31:24], a[0], b[7:0]), u3b[7:0] (out2[31:24], a[0], b[7:0]);
and u0[7:0] (out[7:0], a[7:0], b[7:0]); or u4a[7:0] (out[39:32], a[0], b[7:0]), u4b[7:0] (out2[39:32], a[0], b[7:0]);
and u1[7:0] (out[15:8], a[0], b[7:0]); nor u5a[7:0] (out[47:40], a[0], b[7:0]), u5b[7:0] (out2[47:40], a[0], b[7:0]);
and u2[7:0] (out[23:16], a[0], b[0]); xor u6a[7:0] (out[55:48], a[0], b[7:0]), u6b[7:0] (out2[55:48], a[0], b[7:0]);
nand u3[7:0] (out[31:24], a[0], b[7:0]); xnor u7a[7:0] (out[63:56], a[0], b[7:0]), u7b[7:0] (out2[63:56], a[0], b[7:0]);
or u4[7:0] (out[39:32], a[0], b[7:0]);
nor u5[7:0] (out[47:40], a[0], b[7:0]);
xor u6[7:0] (out[55:48], a[0], b[7:0]);
xnor u7[7:0] (out[63:56], a[0], b[7:0]);
endmodule endmodule

306
test_regress/t/t_gate_primitives_implicit_net.out
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@ -1,166 +1,214 @@
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:21: Signal definition not found, creating implicitly: 'i_and1' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:20: Signal definition not found, creating implicitly: 'i_and1'
15 | and g_and(o_and, i_and1, i_and2, i_and3); 18 | and g_and(o_and, i_and1, i_and2, i_and3),
| ^~~~~~ | ^~~~~~
... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest
... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:29: Signal definition not found, creating implicitly: 'i_and2' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:28: Signal definition not found, creating implicitly: 'i_and2'
: ... Suggested alternative: 'i_and1' : ... Suggested alternative: 'i_and1'
15 | and g_and(o_and, i_and1, i_and2, i_and3); 18 | and g_and(o_and, i_and1, i_and2, i_and3),
| ^~~~~~ | ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:37: Signal definition not found, creating implicitly: 'i_and3' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:36: Signal definition not found, creating implicitly: 'i_and3'
: ... Suggested alternative: 'i_and1' : ... Suggested alternative: 'i_and1'
15 | and g_and(o_and, i_and1, i_and2, i_and3); 18 | and g_and(o_and, i_and1, i_and2, i_and3),
| ^~~~~~ | ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:14: Signal definition not found, creating implicitly: 'o_and' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:13: Signal definition not found, creating implicitly: 'o_and'
: ... Suggested alternative: 'i_and1' : ... Suggested alternative: 'i_and1'
15 | and g_and(o_and, i_and1, i_and2, i_and3); 18 | and g_and(o_and, i_and1, i_and2, i_and3),
| ^~~~~ | ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:16:30: Signal definition not found, creating implicitly: 'i_not1' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:11: Signal definition not found, creating implicitly: 'o2_and'
16 | not g_not(o_not1, o_not2, i_not1);
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:16:14: Signal definition not found, creating implicitly: 'o_not1'
: ... Suggested alternative: 'i_not1'
16 | not g_not(o_not1, o_not2, i_not1);
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:16:22: Signal definition not found, creating implicitly: 'o_not2'
: ... Suggested alternative: 'o_not1'
16 | not g_not(o_not1, o_not2, i_not1);
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:21: Signal definition not found, creating implicitly: 'i_nor1'
: ... Suggested alternative: 'i_not1'
17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3);
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:29: Signal definition not found, creating implicitly: 'i_nor2'
: ... Suggested alternative: 'i_nor1'
17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3);
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:37: Signal definition not found, creating implicitly: 'i_nor3'
: ... Suggested alternative: 'i_nor1'
17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3);
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:14: Signal definition not found, creating implicitly: 'o_nor'
: ... Suggested alternative: 'i_nor1'
17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3);
| ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:18: Signal definition not found, creating implicitly: 'i_or1'
: ... Suggested alternative: 'i_nor1'
18 | or g_or(o_or, i_or1, i_or2, i_or3);
| ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:25: Signal definition not found, creating implicitly: 'i_or2'
: ... Suggested alternative: 'i_nor2'
18 | or g_or(o_or, i_or1, i_or2, i_or3);
| ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:32: Signal definition not found, creating implicitly: 'i_or3'
: ... Suggested alternative: 'i_nor3'
18 | or g_or(o_or, i_or1, i_or2, i_or3);
| ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:12: Signal definition not found, creating implicitly: 'o_or'
: ... Suggested alternative: 'o_nor'
18 | or g_or(o_or, i_or1, i_or2, i_or3);
| ^~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:24: Signal definition not found, creating implicitly: 'i_nand1'
: ... Suggested alternative: 'i_and1'
19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3);
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:33: Signal definition not found, creating implicitly: 'i_nand2'
: ... Suggested alternative: 'i_and2'
19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3);
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:42: Signal definition not found, creating implicitly: 'i_nand3'
: ... Suggested alternative: 'i_and3'
19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3);
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:16: Signal definition not found, creating implicitly: 'o_nand'
: ... Suggested alternative: 'o_and' : ... Suggested alternative: 'o_and'
19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3); 19 | g2_and(o2_and, i_and1, i_and2, i_and3);
| ^~~~~~ | ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:21: Signal definition not found, creating implicitly: 'i_xor1' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:29: Signal definition not found, creating implicitly: 'i_not1'
20 | not g_not(o_not1, o_not2, i_not1),
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:13: Signal definition not found, creating implicitly: 'o_not1'
: ... Suggested alternative: 'i_not1'
20 | not g_not(o_not1, o_not2, i_not1),
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:21: Signal definition not found, creating implicitly: 'o_not2'
: ... Suggested alternative: 'o_not1'
20 | not g_not(o_not1, o_not2, i_not1),
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:11: Signal definition not found, creating implicitly: 'o2_not1'
: ... Suggested alternative: 'o_not1'
21 | g2_not(o2_not1, o_not2, i_not1);
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:20: Signal definition not found, creating implicitly: 'i_nor1'
: ... Suggested alternative: 'i_not1'
22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3),
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:28: Signal definition not found, creating implicitly: 'i_nor2'
: ... Suggested alternative: 'i_nor1' : ... Suggested alternative: 'i_nor1'
20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3); 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3),
| ^~~~~~ | ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:29: Signal definition not found, creating implicitly: 'i_xor2' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:36: Signal definition not found, creating implicitly: 'i_nor3'
: ... Suggested alternative: 'i_nor2' : ... Suggested alternative: 'i_nor1'
20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3); 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3),
| ^~~~~~ | ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:37: Signal definition not found, creating implicitly: 'i_xor3' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:13: Signal definition not found, creating implicitly: 'o_nor'
: ... Suggested alternative: 'i_nor3' : ... Suggested alternative: 'i_nor1'
20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3); 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3),
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:14: Signal definition not found, creating implicitly: 'o_xor'
: ... Suggested alternative: 'o_nor'
20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3);
| ^~~~~ | ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:23: Signal definition not found, creating implicitly: 'i_xnor1' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:11: Signal definition not found, creating implicitly: 'o2_nor'
: ... Suggested alternative: 'i_nor1'
21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3);
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:32: Signal definition not found, creating implicitly: 'i_xnor2'
: ... Suggested alternative: 'i_nor2'
21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3);
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:41: Signal definition not found, creating implicitly: 'i_xnor3'
: ... Suggested alternative: 'i_nor3'
21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3);
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:15: Signal definition not found, creating implicitly: 'o_xnor'
: ... Suggested alternative: 'o_nor' : ... Suggested alternative: 'o_nor'
21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3); 23 | g2_nor(o2_nor, i_nor1, i_nor2, i_nor3);
| ^~~~~~ | ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:30: Signal definition not found, creating implicitly: 'i_buf1' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:17: Signal definition not found, creating implicitly: 'i_or1'
22 | buf g_buf(o_buf1, o_buf2, i_buf1); : ... Suggested alternative: 'i_nor1'
24 | or g_or(o_or, i_or1, i_or2, i_or3),
| ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:24: Signal definition not found, creating implicitly: 'i_or2'
: ... Suggested alternative: 'i_nor2'
24 | or g_or(o_or, i_or1, i_or2, i_or3),
| ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:31: Signal definition not found, creating implicitly: 'i_or3'
: ... Suggested alternative: 'i_nor3'
24 | or g_or(o_or, i_or1, i_or2, i_or3),
| ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:11: Signal definition not found, creating implicitly: 'o_or'
: ... Suggested alternative: 'o_nor'
24 | or g_or(o_or, i_or1, i_or2, i_or3),
| ^~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:10: Signal definition not found, creating implicitly: 'o2_or'
: ... Suggested alternative: 'o2_nor'
25 | g2_or(o2_or, i_or1, i_or2, i_or3);
| ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:23: Signal definition not found, creating implicitly: 'i_nand1'
: ... Suggested alternative: 'i_and1'
26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3),
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:32: Signal definition not found, creating implicitly: 'i_nand2'
: ... Suggested alternative: 'i_and2'
26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3),
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:41: Signal definition not found, creating implicitly: 'i_nand3'
: ... Suggested alternative: 'i_and3'
26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3),
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:15: Signal definition not found, creating implicitly: 'o_nand'
: ... Suggested alternative: 'o_and'
26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3),
| ^~~~~~ | ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:14: Signal definition not found, creating implicitly: 'o_buf1' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:27:12: Signal definition not found, creating implicitly: 'o2_nand'
: ... Suggested alternative: 'o2_and'
27 | g2_nand(o2_nand, i_nand1, i_nand2, i_nand3);
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:20: Signal definition not found, creating implicitly: 'i_xor1'
: ... Suggested alternative: 'i_nor1'
28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3),
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:28: Signal definition not found, creating implicitly: 'i_xor2'
: ... Suggested alternative: 'i_nor2'
28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3),
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:36: Signal definition not found, creating implicitly: 'i_xor3'
: ... Suggested alternative: 'i_nor3'
28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3),
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:13: Signal definition not found, creating implicitly: 'o_xor'
: ... Suggested alternative: 'o_nor'
28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3),
| ^~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:29:11: Signal definition not found, creating implicitly: 'o2_xor'
: ... Suggested alternative: 'o2_nor'
29 | g2_xor(o2_xor, i_xor1, i_xor2, i_xor3);
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:22: Signal definition not found, creating implicitly: 'i_xnor1'
: ... Suggested alternative: 'i_nor1'
30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3),
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:31: Signal definition not found, creating implicitly: 'i_xnor2'
: ... Suggested alternative: 'i_nor2'
30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3),
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:40: Signal definition not found, creating implicitly: 'i_xnor3'
: ... Suggested alternative: 'i_nor3'
30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3),
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:14: Signal definition not found, creating implicitly: 'o_xnor'
: ... Suggested alternative: 'o_nor'
30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3),
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:31:11: Signal definition not found, creating implicitly: 'o2_xnor'
: ... Suggested alternative: 'o2_nor'
31 | g2_xor(o2_xnor, i_xnor1, i_xnor2, i_xnor3);
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:29: Signal definition not found, creating implicitly: 'i_buf1'
32 | buf g_buf(o_buf1, o_buf2, i_buf1),
| ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:13: Signal definition not found, creating implicitly: 'o_buf1'
: ... Suggested alternative: 'i_buf1' : ... Suggested alternative: 'i_buf1'
22 | buf g_buf(o_buf1, o_buf2, i_buf1); 32 | buf g_buf(o_buf1, o_buf2, i_buf1),
| ^~~~~~ | ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:22: Signal definition not found, creating implicitly: 'o_buf2' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:21: Signal definition not found, creating implicitly: 'o_buf2'
: ... Suggested alternative: 'o_buf1' : ... Suggested alternative: 'o_buf1'
22 | buf g_buf(o_buf1, o_buf2, i_buf1); 32 | buf g_buf(o_buf1, o_buf2, i_buf1),
| ^~~~~~ | ^~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:41: Signal definition not found, creating implicitly: 'i_bufif02' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:33:11: Signal definition not found, creating implicitly: 'o2_buf1'
23 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02); : ... Suggested alternative: 'o_buf1'
33 | g2_buf(o2_buf1, o_buf2, i_buf1);
| ^~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:40: Signal definition not found, creating implicitly: 'i_bufif02'
34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02),
| ^~~~~~~~~ | ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:30: Signal definition not found, creating implicitly: 'i_bufif01' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:29: Signal definition not found, creating implicitly: 'i_bufif01'
: ... Suggested alternative: 'i_bufif02' : ... Suggested alternative: 'i_bufif02'
23 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02); 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02),
| ^~~~~~~~~ | ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:20: Signal definition not found, creating implicitly: 'o_bufif0' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:19: Signal definition not found, creating implicitly: 'o_bufif0'
: ... Suggested alternative: 'i_bufif01' : ... Suggested alternative: 'i_bufif01'
23 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02); 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02),
| ^~~~~~~~ | ^~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:41: Signal definition not found, creating implicitly: 'i_bufif12' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:35:14: Signal definition not found, creating implicitly: 'o2_bufif0'
: ... Suggested alternative: 'i_bufif02'
24 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12);
| ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:30: Signal definition not found, creating implicitly: 'i_bufif11'
: ... Suggested alternative: 'i_bufif01'
24 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12);
| ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:20: Signal definition not found, creating implicitly: 'o_bufif1'
: ... Suggested alternative: 'o_bufif0' : ... Suggested alternative: 'o_bufif0'
24 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12); 35 | g2_bufif0(o2_bufif0, i_bufif01, i_bufif02);
| ^~~~~~~~ | ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:41: Signal definition not found, creating implicitly: 'i_notif02' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:40: Signal definition not found, creating implicitly: 'i_bufif12'
: ... Suggested alternative: 'i_bufif02' : ... Suggested alternative: 'i_bufif02'
25 | notif0 g_notif0(o_notif0, i_notif01, i_notif02); 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12),
| ^~~~~~~~~ | ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:30: Signal definition not found, creating implicitly: 'i_notif01' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:29: Signal definition not found, creating implicitly: 'i_bufif11'
: ... Suggested alternative: 'i_notif02' : ... Suggested alternative: 'i_bufif01'
25 | notif0 g_notif0(o_notif0, i_notif01, i_notif02); 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12),
| ^~~~~~~~~ | ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:20: Signal definition not found, creating implicitly: 'o_notif0' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:19: Signal definition not found, creating implicitly: 'o_bufif1'
: ... Suggested alternative: 'i_notif01' : ... Suggested alternative: 'o_bufif0'
25 | notif0 g_notif0(o_notif0, i_notif01, i_notif02); 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12),
| ^~~~~~~~ | ^~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:41: Signal definition not found, creating implicitly: 'i_notif12' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:37:14: Signal definition not found, creating implicitly: 'o2_bufif1'
: ... Suggested alternative: 'o2_bufif0'
37 | g2_bufif1(o2_bufif1, i_bufif11, i_bufif12);
| ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:40: Signal definition not found, creating implicitly: 'i_notif02'
: ... Suggested alternative: 'i_bufif02'
38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02),
| ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:29: Signal definition not found, creating implicitly: 'i_notif01'
: ... Suggested alternative: 'i_notif02' : ... Suggested alternative: 'i_notif02'
26 | notif1 g_notif1(o_notif1, i_notif11, i_notif12); 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02),
| ^~~~~~~~~ | ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:30: Signal definition not found, creating implicitly: 'i_notif11' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:19: Signal definition not found, creating implicitly: 'o_notif0'
: ... Suggested alternative: 'i_notif01' : ... Suggested alternative: 'i_notif01'
26 | notif1 g_notif1(o_notif1, i_notif11, i_notif12); 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02),
| ^~~~~~~~~ | ^~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:20: Signal definition not found, creating implicitly: 'o_notif1' %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:39:14: Signal definition not found, creating implicitly: 'o2_notif0'
: ... Suggested alternative: 'o_notif0' : ... Suggested alternative: 'o_notif0'
26 | notif1 g_notif1(o_notif1, i_notif11, i_notif12); 39 | g2_notif0(o2_notif0, i_notif01, i_notif02);
| ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:40: Signal definition not found, creating implicitly: 'i_notif12'
: ... Suggested alternative: 'i_notif02'
40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12),
| ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:29: Signal definition not found, creating implicitly: 'i_notif11'
: ... Suggested alternative: 'i_notif01'
40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12),
| ^~~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:19: Signal definition not found, creating implicitly: 'o_notif1'
: ... Suggested alternative: 'o_notif0'
40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12),
| ^~~~~~~~ | ^~~~~~~~
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:41:14: Signal definition not found, creating implicitly: 'o2_notif1'
: ... Suggested alternative: 'o2_notif0'
41 | g2_notif1(o2_notif1, i_notif11, i_notif12);
| ^~~~~~~~~

59
test_regress/t/t_gate_primitives_implicit_net.v
View File

@ -4,26 +4,41 @@
// any use, without warranty, 2023 by Wilson Snyder. // any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/ // verilog_format: off
// Inputs `define stop $stop
clk `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
module t(
input clk
); );
input clk;
int cyc=1; int cyc=1;
// Instantiate the primitive gates to be tested. // Instantiate the primitive gates to be tested.
and g_and(o_and, i_and1, i_and2, i_and3); and g_and(o_and, i_and1, i_and2, i_and3),
not g_not(o_not1, o_not2, i_not1); g2_and(o2_and, i_and1, i_and2, i_and3);
nor g_nor(o_nor, i_nor1, i_nor2, i_nor3); not g_not(o_not1, o_not2, i_not1),
or g_or(o_or, i_or1, i_or2, i_or3); g2_not(o2_not1, o_not2, i_not1);
nand g_nand(o_nand, i_nand1, i_nand2, i_nand3); nor g_nor(o_nor, i_nor1, i_nor2, i_nor3),
xor g_xor(o_xor, i_xor1, i_xor2, i_xor3); g2_nor(o2_nor, i_nor1, i_nor2, i_nor3);
xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3); or g_or(o_or, i_or1, i_or2, i_or3),
buf g_buf(o_buf1, o_buf2, i_buf1); g2_or(o2_or, i_or1, i_or2, i_or3);
bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02); nand g_nand(o_nand, i_nand1, i_nand2, i_nand3),
bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12); g2_nand(o2_nand, i_nand1, i_nand2, i_nand3);
notif0 g_notif0(o_notif0, i_notif01, i_notif02); xor g_xor(o_xor, i_xor1, i_xor2, i_xor3),
notif1 g_notif1(o_notif1, i_notif11, i_notif12); g2_xor(o2_xor, i_xor1, i_xor2, i_xor3);
xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3),
g2_xor(o2_xnor, i_xnor1, i_xnor2, i_xnor3);
buf g_buf(o_buf1, o_buf2, i_buf1),
g2_buf(o2_buf1, o_buf2, i_buf1);
bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02),
g2_bufif0(o2_bufif0, i_bufif01, i_bufif02);
bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12),
g2_bufif1(o2_bufif1, i_bufif11, i_bufif12);
notif0 g_notif0(o_notif0, i_notif01, i_notif02),
g2_notif0(o2_notif0, i_notif01, i_notif02);
notif1 g_notif1(o_notif1, i_notif11, i_notif12),
g2_notif1(o2_notif1, i_notif11, i_notif12);
// Generate random data for inputs // Generate random data for inputs
reg rd_data1, rd_data2, rd_data3; reg rd_data1, rd_data2, rd_data3;
@ -89,6 +104,18 @@ module t(/*AUTOARG*/
if (!(o_bufif1 == (i_bufif11 & i_bufif12))) $stop; if (!(o_bufif1 == (i_bufif11 & i_bufif12))) $stop;
if (!(o_notif0 == (!i_notif01 & !i_notif02))) $stop; if (!(o_notif0 == (!i_notif01 & !i_notif02))) $stop;
if (!(o_notif1 == (!i_notif11 & i_notif12))) $stop; if (!(o_notif1 == (!i_notif11 & i_notif12))) $stop;
`checkh(o2_and, o2_and);
`checkh(o2_not1, o2_not1);
`checkh(o2_nor, o2_nor);
`checkh(o2_or, o2_or);
`checkh(o2_nand, o2_nand);
`checkh(o2_xor, o2_xor);
`checkh(o2_xnor, o2_xnor);
`checkh(o2_buf1, o2_buf1);
`checkh(o2_bufif0, o2_bufif0);
`checkh(o2_bufif1, o2_bufif1);
`checkh(o2_notif0, o2_notif0);
`checkh(o2_notif1, o2_notif1);
end end
always @(posedge clk) begin always @(posedge clk) begin

5
test_regress/t/t_scope_map.cpp
View File

@ -128,6 +128,11 @@ int main(int argc, char** argv) {
int varLeft = varp->range(0)->left(); int varLeft = varp->range(0)->left();
int varBits = varLeft + 1; int varBits = varLeft + 1;
uint8_t* varData = reinterpret_cast<uint8_t*>(varp->datap()); uint8_t* varData = reinterpret_cast<uint8_t*>(varp->datap());
// Cover illegal access
if (varp->range(1000) != nullptr) {
VL_PRINTF("%%Error: Range null mismatch\n");
return -1;
}
// Check that all bits are high now // Check that all bits are high now
for (int i = 0; i < varBits / 8; i++) { for (int i = 0; i < varBits / 8; i++) {

2
test_regress/t/t_time_vpi_1us1ns.py
View File

@ -16,7 +16,7 @@ test.main_time_multiplier = 1e-6 / 1e-9
test.compile( test.compile(
v_flags2=['+define+time_scale_units=1us +define+time_scale_prec=1ns', test.pli_filename], v_flags2=['+define+time_scale_units=1us +define+time_scale_prec=1ns', test.pli_filename],
verilator_flags2=['--vpi']) verilator_flags2=['--vpi --trace-vcd'])
test.execute(expect_filename=test.golden_filename) test.execute(expect_filename=test.golden_filename)

1117
test_regress/t/t_trace_fst.out
View File

File diff suppressed because it is too large Load Diff

5
test_regress/t/t_trace_fst.v
View File

@ -7,6 +7,8 @@
module t (/*AUTOARG*/ module t (/*AUTOARG*/
// Outputs // Outputs
state, state,
// Inouts
fst_inout,
// Inputs // Inputs
clk clk
); );
@ -27,6 +29,7 @@ module t (/*AUTOARG*/
shortint fst_shortint; shortint fst_shortint;
longint fst_longint; longint fst_longint;
byte fst_byte; byte fst_byte;
time fst_time;
parameter fst_parameter = 123; parameter fst_parameter = 123;
localparam fst_lparam = 456; localparam fst_lparam = 456;
@ -36,6 +39,7 @@ module t (/*AUTOARG*/
tri1 fst_tri1; tri1 fst_tri1;
tri fst_tri; tri fst_tri;
wire fst_wire; wire fst_wire;
inout fst_inout;
Test test (/*AUTOINST*/ Test test (/*AUTOINST*/
// Outputs // Outputs
@ -47,6 +51,7 @@ module t (/*AUTOARG*/
// Test loop // Test loop
always @ (posedge clk) begin always @ (posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
fst_time <= $time;
if (cyc==0) begin if (cyc==0) begin
// Setup // Setup
rstn <= ~'1; rstn <= ~'1;

66
test_regress/t/t_trace_saif.out
View File

@ -14,6 +14,7 @@
(state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
(state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
(fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
) )
(INSTANCE t (INSTANCE t
(NET (NET
@ -402,6 +403,70 @@
(fst_byte\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_byte\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_byte\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
(fst_time\[2\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
(fst_time\[3\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 75))
(fst_time\[4\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 62))
(fst_time\[5\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 31))
(fst_time\[6\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 15))
(fst_time\[7\] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 7))
(fst_time\[8\] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 3))
(fst_time\[9\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_time\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_time\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_parameter\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@ -472,6 +537,7 @@
(fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_tri (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_tri (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
(fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
) )
(INSTANCE test (INSTANCE test
(NET (NET

73
test_regress/t/t_tri_various.v
View File

@ -4,10 +4,13 @@
// without warranty, 2008 by Lane Brooks. // without warranty, 2008 by Lane Brooks.
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (clk); module t (
clk
);
input clk; input clk;
reg [31:0] state; initial state=0; reg [31:0] state;
initial state = 0;
wire A = state[0]; wire A = state[0];
wire OE = state[1]; wire OE = state[1];
@ -66,8 +69,8 @@ module t (clk);
always @(posedge clk) begin always @(posedge clk) begin
state <= state + 1; state <= state + 1;
`ifdef TEST_VERBOSE `ifdef TEST_VERBOSE
$write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n", $write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n", $time,
$time, state, Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11); state, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11);
`endif `endif
if (state == 0) begin if (state == 0) begin
@ -135,30 +138,40 @@ module t (clk);
$finish; $finish;
end end
end end
pullup(Z1); pullup (Z1), (Z2);
pullup(Z2);
pullup (Z3); pullup (Z3);
pullup (Z4); pullup (Z4);
pullup (Z5); pullup (Z5);
pullup (Z6); pullup (Z6);
pulldown(Z7); pulldown (Z7), (Z9);
pullup (Z8); pullup (Z8);
pulldown(Z9);
pulldown pd10[3:0] (Z10); pulldown pd10[3:0] (Z10);
endmodule endmodule
module Test1(input OE, input A, inout Z1); module Test1 (
input OE,
input A,
inout Z1
);
assign Z1 = (OE) ? A : 1'bz; assign Z1 = (OE) ? A : 1'bz;
endmodule endmodule
module Test2(input OE, input A, inout Z2); module Test2 (
input OE,
input A,
inout Z2
);
assign Z2 = (OE) ? A : 1'bz; assign Z2 = (OE) ? A : 1'bz;
endmodule endmodule
// mixed low-Z and tristate // mixed low-Z and tristate
module Test3(input OE, input A, inout Z3); module Test3 (
input OE,
input A,
inout Z3
);
assign Z3 = (OE) ? A : 1'bz; assign Z3 = (OE) ? A : 1'bz;
assign Z3 = 1'b1; assign Z3 = 1'b1;
endmodule endmodule
@ -168,12 +181,21 @@ endmodule
`ifndef VERILATOR `ifndef VERILATOR
// Note verilator doesn't know to make Z4 a tristate unless marked an inout // Note verilator doesn't know to make Z4 a tristate unless marked an inout
`endif `endif
module Test4(output Z4, inout Z5); module Test4 (
output Z4,
inout Z5
);
endmodule endmodule
// AND gate tristates // AND gate tristates
module Test5(input OE, inout Z6, inout Z7, inout Z8, inout Z9); module Test5 (
input OE,
inout Z6,
inout Z7,
inout Z8,
inout Z9
);
assign Z6 = (OE) ? 1'b0 : 1'bz; assign Z6 = (OE) ? 1'b0 : 1'bz;
assign Z7 = (OE) ? 1'b1 : 1'bz; assign Z7 = (OE) ? 1'b1 : 1'bz;
assign Z8 = (OE) ? 1'bz : 1'b0; assign Z8 = (OE) ? 1'bz : 1'b0;
@ -181,17 +203,32 @@ module Test5(input OE, inout Z6, inout Z7, inout Z8, inout Z9);
endmodule endmodule
// AND gate tristates // AND gate tristates
module Test6(input OE, inout [3:0] Z10); module Test6 (
input OE,
inout [3:0] Z10
);
wire [1:0] i; wire [1:0] i;
Test6a a (.OE(OE), .Z({Z10[0],Z10[1]})); Test6a a (
Test6a b (.OE(~OE), .Z({Z10[2],Z10[0]})); .OE(OE),
.Z({Z10[0], Z10[1]})
);
Test6a b (
.OE(~OE),
.Z({Z10[2], Z10[0]})
);
endmodule endmodule
module Test6a(input OE, inout [1:0] Z); module Test6a (
input OE,
inout [1:0] Z
);
assign Z = (OE) ? 2'b01 : 2'bzz; assign Z = (OE) ? 2'b01 : 2'bzz;
endmodule endmodule
module Test7(input [2:0] state, output reg Z11); module Test7 (
input [2:0] state,
output reg Z11
);
always @(*) begin always @(*) begin
casez (state) casez (state)
3'b000: Z11 = 1'b0; 3'b000: Z11 = 1'b0;

19
test_regress/t/t_wire_trireg_unsup.out
View File

@ -2,4 +2,23 @@
11 | trireg unsup; 11 | trireg unsup;
| ^~~~~~ | ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:12:4: Unsupported: trireg
12 | trireg (small) unsup_s;
| ^~~~~~
%Error: t/t_wire_trireg_unsup.v:12:12: syntax error, unexpected STRENGTH keyword (strong1/etc)
12 | trireg (small) unsup_s;
| ^~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:13:4: Unsupported: trireg
13 | trireg (medium) unsup_m;
| ^~~~~~
%Error: t/t_wire_trireg_unsup.v:13:12: syntax error, unexpected STRENGTH keyword (strong1/etc)
13 | trireg (medium) unsup_m;
| ^~~~~~
%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:14:4: Unsupported: trireg
14 | trireg (large) unsup_l;
| ^~~~~~
%Error: t/t_wire_trireg_unsup.v:14:12: syntax error, unexpected STRENGTH keyword (strong1/etc)
14 | trireg (large) unsup_l;
| ^~~~~
%Error: Exiting due to %Error: Exiting due to

3
test_regress/t/t_wire_trireg_unsup.v
View File

@ -9,5 +9,8 @@
module t; module t;
trireg unsup; trireg unsup;
trireg (small) unsup_s;
trireg (medium) unsup_m;
trireg (large) unsup_l;
endmodule endmodule