From 6e8bd3da19f37ef7515ec3ec52bc911b521d4c13 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 11 Oct 2025 12:54:55 -0400 Subject: [PATCH] Internals/Tests: Cleanup some missing dev coverage items --- Makefile.in | 1 + include/verilated_random.h | 2 +- include/verilated_trace.h | 2 +- include/verilated_vpi.cpp | 20 +- src/verilog.l | 22 +- test_regress/t/t_attr.py | 16 + test_regress/t/t_attr.v | 16 + test_regress/t/t_dpi_export_scope_bad.cpp | 20 - test_regress/t/t_dpi_export_scope_bad.out | 2 +- test_regress/t/t_dpi_export_scope_bad.py | 2 +- test_regress/t/t_gate_array.v | 136 +- .../t/t_gate_primitives_implicit_net.out | 342 ++--- .../t/t_gate_primitives_implicit_net.v | 181 +-- test_regress/t/t_scope_map.cpp | 5 + test_regress/t/t_time_vpi_1us1ns.py | 2 +- test_regress/t/t_trace_fst.out | 1117 +++++++++-------- test_regress/t/t_trace_fst.v | 15 +- test_regress/t/t_trace_saif.out | 66 + test_regress/t/t_tri_various.v | 263 ++-- test_regress/t/t_wire_trireg_unsup.out | 19 + test_regress/t/t_wire_trireg_unsup.v | 3 + 21 files changed, 1289 insertions(+), 963 deletions(-) create mode 100755 test_regress/t/t_attr.py create mode 100644 test_regress/t/t_attr.v diff --git a/Makefile.in b/Makefile.in index d724da8cf..fa4d0407d 100644 --- a/Makefile.in +++ b/Makefile.in @@ -655,6 +655,7 @@ GENHTML := genhtml GENHTML_OPT := -j $(shell nproc) GENHTML_OPT += --branch-coverage GENHTML_OPT += --demangle-cpp +GENHTML_OPT += --missed GENHTML_OPT += --rc branch_coverage=1 GENHTML_OPT += --rc genhtml_hi_limit=100 GENHTML_OPT += --ignore-errors negative diff --git a/include/verilated_random.h b/include/verilated_random.h index 607e14357..c7e41e590 100644 --- a/include/verilated_random.h +++ b/include/verilated_random.h @@ -111,7 +111,7 @@ public: return it->second->m_datap; } else { VL_FATAL_MT(__FILE__, __LINE__, "randomize", "indexed_name not found in m_arr_vars"); - return nullptr; + return nullptr; // LCOV_EXCL_BR_LINE } } void emitHexs(std::ostream& s, const std::vector& indices, const size_t bit_width, diff --git a/include/verilated_trace.h b/include/verilated_trace.h index 3d3d73b53..39725394d 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -531,7 +531,7 @@ public: } VL_ATTR_ALWINLINE void chgEventTriggered(uint32_t* oldp) { fullEventTriggered(oldp); } VL_ATTR_ALWINLINE void chgDouble(uint32_t* oldp, double newval) { - double old; + double old; // LCOV_EXCL_LINE // lcov bug std::memcpy(&old, oldp, sizeof(old)); if (VL_UNLIKELY(old != newval)) fullDouble(oldp, newval); } diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index f46ce0e25..3e1db346b 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -2399,7 +2399,7 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c case VLVT_UINT32: case VLVT_UINT64: case VLVT_WDATA: return status; - default: status = false; + default: status = false; // LCOV_EXCL_LINE } } else if (valuep->format == vpiDecStrVal) { switch (varp->vltype()) { @@ -2407,7 +2407,7 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c case VLVT_UINT16: case VLVT_UINT32: case VLVT_UINT64: return status; - default: status = false; + default: status = false; // LCOV_EXCL_LINE } } else if (valuep->format == vpiStringVal) { switch (varp->vltype()) { @@ -2424,7 +2424,7 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c status = false; break; } - default: status = false; + default: status = false; // LCOV_EXCL_LINE } } else if (valuep->format == vpiIntVal) { switch (varp->vltype()) { @@ -2433,12 +2433,12 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c case VLVT_UINT32: case VLVT_UINT64: case VLVT_WDATA: return status; - default: status = false; + default: status = false; // LCOV_EXCL_LINE } } else if (valuep->format == vpiRealVal) { switch (varp->vltype()) { case VLVT_REAL: return status; - default: status = false; + default: status = false; // LCOV_EXCL_LINE } } else if (valuep->format == vpiSuppressVal) { return status; @@ -2919,14 +2919,14 @@ bool vl_check_array_format(const VerilatedVar* varp, const p_vpi_arrayvalue arra case VLVT_UINT32: case VLVT_UINT64: case VLVT_WDATA: return true; - default:; + default:; // LCOV_EXCL_LINE } } else if (arrayvalue_p->format == vpiIntVal) { switch (varp->vltype()) { case VLVT_UINT8: case VLVT_UINT16: case VLVT_UINT32: return true; - default:; + default:; // LCOV_EXCL_LINE } } else if ((arrayvalue_p->format == vpiRawTwoStateVal) || (arrayvalue_p->format == vpiRawFourStateVal)) { @@ -2936,13 +2936,13 @@ bool vl_check_array_format(const VerilatedVar* varp, const p_vpi_arrayvalue arra case VLVT_UINT32: case VLVT_UINT64: case VLVT_WDATA: return true; - default:; + default:; // LCOV_EXCL_LINE } } else if (arrayvalue_p->format == vpiShortIntVal) { switch (varp->vltype()) { case VLVT_UINT8: case VLVT_UINT16: return true; - default:; + default:; // LCOV_EXCL_LINE } } else if (arrayvalue_p->format == vpiLongIntVal) { switch (varp->vltype()) { @@ -2950,7 +2950,7 @@ bool vl_check_array_format(const VerilatedVar* varp, const p_vpi_arrayvalue arra case VLVT_UINT16: case VLVT_UINT32: case VLVT_UINT64: return true; - default:; + default:; // LCOV_EXCL_LINE } } diff --git a/src/verilog.l b/src/verilog.l index 6796cb811..1173aeec1 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -1045,17 +1045,17 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Tables */ -[rRfFpPnN\*] { FL; yylval.strp = PARSEP->newString(yytext, yyleng); return yaTABLE_FIELD; } /* edge_symbol */ -
[01xX\?bB\-] { FL; yylval.strp = PARSEP->newString(yytext, yyleng); return yaTABLE_FIELD; } /* level_symbol, next_state */ -
":" { FL; return yaTABLE_LRSEP; } /* LHS and RHS separator for table line. */ -
";" { FL; return yaTABLE_LINEEND; } -
[\(\)] { FL; return yytext[0]; } -
{ws}|(\\){0,1}{crnl} { FL_FWD; FL_BRK; } -
"`line"{ws}+[^\n\r]*{crnl} { FL_FWD; PARSEP->lexPpline(yytext); FL_BRK; } -
"//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */ -
"endtable" { FL; yy_pop_state(); return yENDTABLE; } -
<> { FL; yylval.fl->v3error("EOF in 'table'"); - yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); } +
[rRfFpPnN\*] { FL; yylval.strp = PARSEP->newString(yytext, yyleng); return yaTABLE_FIELD; } /* edge_symbol */ +
[01xX\?bB\-] { FL; yylval.strp = PARSEP->newString(yytext, yyleng); return yaTABLE_FIELD; } /* level_symbol, next_state */ +
":" { FL; return yaTABLE_LRSEP; } /* LHS and RHS separator for table line. */ +
";" { FL; return yaTABLE_LINEEND; } +
[\(\)] { FL; return yytext[0]; } +
{ws}|(\\){0,1}{crnl} { FL_FWD; FL_BRK; } +
"`line"{ws}+[^\n\r]*{crnl} { FL_FWD; PARSEP->lexPpline(yytext); FL_BRK; } +
"//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */ +
"endtable" { FL; yy_pop_state(); return yENDTABLE; } +
<> { FL; yylval.fl->v3error("EOF in 'table'"); + yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); } { 01|10|[01][zZxX]|[zZxX][01] { FL; return yaEDGEDESC; } diff --git a/test_regress/t/t_attr.py b/test_regress/t/t_attr.py new file mode 100755 index 000000000..f81c3d68d --- /dev/null +++ b/test_regress/t/t_attr.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_attr.v b/test_regress/t/t_attr.v new file mode 100644 index 000000000..b24939114 --- /dev/null +++ b/test_regress/t/t_attr.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + (* attr_name1 *) + (* attr_name1 = val1 *) + (* attr_name1 = val1, attr_name2 *) + (* attr_name1 = val1, attr_name2=1 *) + + initial $finish; + +endmodule diff --git a/test_regress/t/t_dpi_export_scope_bad.cpp b/test_regress/t/t_dpi_export_scope_bad.cpp index e6a04e849..66a178afc 100644 --- a/test_regress/t/t_dpi_export_scope_bad.cpp +++ b/test_regress/t/t_dpi_export_scope_bad.cpp @@ -7,7 +7,6 @@ // SPDX-License-Identifier: CC0-1.0 #include -#include VM_PREFIX_INCLUDE //====================================================================== @@ -21,25 +20,6 @@ extern void dpix_task(); //====================================================================== -unsigned int main_time = 0; - -double sc_time_stamp() { return main_time; } - -VM_PREFIX* topp = nullptr; - -int main(int argc, char* argv[]) { - Verilated::debug(0); - Verilated::commandArgs(argc, argv); - - topp = new VM_PREFIX; - - topp->eval(); - - topp->final(); - VL_DO_DANGLING(delete topp, topp); - return 1; -} - void dpix_run_tests() { dpix_task(); // Wrong scope } diff --git a/test_regress/t/t_dpi_export_scope_bad.out b/test_regress/t/t_dpi_export_scope_bad.out index 490d26c84..677411429 100644 --- a/test_regress/t/t_dpi_export_scope_bad.out +++ b/test_regress/t/t_dpi_export_scope_bad.out @@ -1,2 +1,2 @@ -%Error: unknown:0: Testbench C called 'dpix_task' but this DPI export function exists only in other scopes, not scope 'TOP.t' +%Error: unknown:0: Testbench C called 'dpix_task' but this DPI export function exists only in other scopes, not scope 't' Aborting... diff --git a/test_regress/t/t_dpi_export_scope_bad.py b/test_regress/t/t_dpi_export_scope_bad.py index b84ad228c..2f7249020 100755 --- a/test_regress/t/t_dpi_export_scope_bad.py +++ b/test_regress/t/t_dpi_export_scope_bad.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) +test.compile(v_flags2=["--binary", test.pli_filename]) test.execute(fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_gate_array.v b/test_regress/t/t_gate_array.v index 239d17495..224946680 100644 --- a/test_regress/t/t_gate_array.v +++ b/test_regress/t/t_gate_array.v @@ -4,86 +4,84 @@ // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [7:0] a = crc[7:0]; - wire [7:0] b = crc[15:8]; + // Take CRC data and apply to testblock inputs + wire [7:0] a = crc[7:0]; + wire [7:0] b = crc[15:8]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [63:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [63:0] out; // From test of Test.v + wire [63:0] out2; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[63:0]), - // Inputs - .clk (clk), - .a (a[7:0]), - .b (b[7:0])); + Test test ( /*AUTOINST*/ + // Outputs + .out (out[63:0]), + .out2 (out2[63:0]), + // Inputs + .clk (clk), + .a (a[7:0]), + .b (b[7:0])); - // Aggregate outputs into a single result vector - wire [63:0] result = {out}; + // Aggregate outputs into a single result vector + wire [63:0] result = {out}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h0908a1f2194d24ee - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + if (out2 !== out) $stop; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h0908a1f2194d24ee + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, a, b - ); +module Test ( + input clk, + input [7:0] a, + input [7:0] b, + output reg [63:0] out, + output reg [63:0] out2 +); - input clk; - input [7:0] a; - input [7:0] b; - output reg [63:0] out; - - and u0[7:0] (out[7:0], a[7:0], b[7:0]); - and u1[7:0] (out[15:8], a[0], b[7:0]); - and u2[7:0] (out[23:16], a[0], b[0]); - nand u3[7:0] (out[31:24], a[0], b[7:0]); - or u4[7:0] (out[39:32], a[0], b[7:0]); - nor u5[7:0] (out[47:40], a[0], b[7:0]); - xor u6[7:0] (out[55:48], a[0], b[7:0]); - xnor u7[7:0] (out[63:56], a[0], b[7:0]); + // Also cover comma syntax + and u0a[7:0] (out[7:0], a[7:0], b[7:0]), u0b[7:0] (out2[7:0], a[7:0], b[7:0]); + and u1a[7:0] (out[15:8], a[0], b[7:0]), u1b[7:0] (out2[15:8], a[0], b[7:0]); + and u2a[7:0] (out[23:16], a[0], b[0]), u2b[7:0] (out2[23:16], a[0], b[0]); + nand u3a[7:0] (out[31:24], a[0], b[7:0]), u3b[7:0] (out2[31:24], a[0], b[7:0]); + or u4a[7:0] (out[39:32], a[0], b[7:0]), u4b[7:0] (out2[39:32], a[0], b[7:0]); + nor u5a[7:0] (out[47:40], a[0], b[7:0]), u5b[7:0] (out2[47:40], a[0], b[7:0]); + xor u6a[7:0] (out[55:48], a[0], b[7:0]), u6b[7:0] (out2[55:48], a[0], b[7:0]); + xnor u7a[7:0] (out[63:56], a[0], b[7:0]), u7b[7:0] (out2[63:56], a[0], b[7:0]); endmodule diff --git a/test_regress/t/t_gate_primitives_implicit_net.out b/test_regress/t/t_gate_primitives_implicit_net.out index 3f41c1ff9..61abfe8bc 100755 --- a/test_regress/t/t_gate_primitives_implicit_net.out +++ b/test_regress/t/t_gate_primitives_implicit_net.out @@ -1,166 +1,214 @@ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:21: Signal definition not found, creating implicitly: 'i_and1' - 15 | and g_and(o_and, i_and1, i_and2, i_and3); - | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:20: Signal definition not found, creating implicitly: 'i_and1' + 18 | and g_and(o_and, i_and1, i_and2, i_and3), + | ^~~~~~ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:29: Signal definition not found, creating implicitly: 'i_and2' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:28: Signal definition not found, creating implicitly: 'i_and2' : ... Suggested alternative: 'i_and1' - 15 | and g_and(o_and, i_and1, i_and2, i_and3); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:37: Signal definition not found, creating implicitly: 'i_and3' + 18 | and g_and(o_and, i_and1, i_and2, i_and3), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:36: Signal definition not found, creating implicitly: 'i_and3' : ... Suggested alternative: 'i_and1' - 15 | and g_and(o_and, i_and1, i_and2, i_and3); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:14: Signal definition not found, creating implicitly: 'o_and' + 18 | and g_and(o_and, i_and1, i_and2, i_and3), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:13: Signal definition not found, creating implicitly: 'o_and' : ... Suggested alternative: 'i_and1' - 15 | and g_and(o_and, i_and1, i_and2, i_and3); - | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:16:30: Signal definition not found, creating implicitly: 'i_not1' - 16 | not g_not(o_not1, o_not2, i_not1); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:16:14: Signal definition not found, creating implicitly: 'o_not1' - : ... Suggested alternative: 'i_not1' - 16 | not g_not(o_not1, o_not2, i_not1); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:16:22: Signal definition not found, creating implicitly: 'o_not2' - : ... Suggested alternative: 'o_not1' - 16 | not g_not(o_not1, o_not2, i_not1); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:21: Signal definition not found, creating implicitly: 'i_nor1' - : ... Suggested alternative: 'i_not1' - 17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:29: Signal definition not found, creating implicitly: 'i_nor2' - : ... Suggested alternative: 'i_nor1' - 17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:37: Signal definition not found, creating implicitly: 'i_nor3' - : ... Suggested alternative: 'i_nor1' - 17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:14: Signal definition not found, creating implicitly: 'o_nor' - : ... Suggested alternative: 'i_nor1' - 17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3); - | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:18: Signal definition not found, creating implicitly: 'i_or1' - : ... Suggested alternative: 'i_nor1' - 18 | or g_or(o_or, i_or1, i_or2, i_or3); - | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:25: Signal definition not found, creating implicitly: 'i_or2' - : ... Suggested alternative: 'i_nor2' - 18 | or g_or(o_or, i_or1, i_or2, i_or3); - | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:32: Signal definition not found, creating implicitly: 'i_or3' - : ... Suggested alternative: 'i_nor3' - 18 | or g_or(o_or, i_or1, i_or2, i_or3); - | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:12: Signal definition not found, creating implicitly: 'o_or' - : ... Suggested alternative: 'o_nor' - 18 | or g_or(o_or, i_or1, i_or2, i_or3); - | ^~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:24: Signal definition not found, creating implicitly: 'i_nand1' - : ... Suggested alternative: 'i_and1' - 19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3); - | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:33: Signal definition not found, creating implicitly: 'i_nand2' - : ... Suggested alternative: 'i_and2' - 19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3); - | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:42: Signal definition not found, creating implicitly: 'i_nand3' - : ... Suggested alternative: 'i_and3' - 19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3); - | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:16: Signal definition not found, creating implicitly: 'o_nand' + 18 | and g_and(o_and, i_and1, i_and2, i_and3), + | ^~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:11: Signal definition not found, creating implicitly: 'o2_and' : ... Suggested alternative: 'o_and' - 19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:21: Signal definition not found, creating implicitly: 'i_xor1' - : ... Suggested alternative: 'i_nor1' - 20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:29: Signal definition not found, creating implicitly: 'i_xor2' - : ... Suggested alternative: 'i_nor2' - 20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3); + 19 | g2_and(o2_and, i_and1, i_and2, i_and3); + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:29: Signal definition not found, creating implicitly: 'i_not1' + 20 | not g_not(o_not1, o_not2, i_not1), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:37: Signal definition not found, creating implicitly: 'i_xor3' - : ... Suggested alternative: 'i_nor3' - 20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:14: Signal definition not found, creating implicitly: 'o_xor' - : ... Suggested alternative: 'o_nor' - 20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3); - | ^~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:23: Signal definition not found, creating implicitly: 'i_xnor1' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:13: Signal definition not found, creating implicitly: 'o_not1' + : ... Suggested alternative: 'i_not1' + 20 | not g_not(o_not1, o_not2, i_not1), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:21: Signal definition not found, creating implicitly: 'o_not2' + : ... Suggested alternative: 'o_not1' + 20 | not g_not(o_not1, o_not2, i_not1), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:11: Signal definition not found, creating implicitly: 'o2_not1' + : ... Suggested alternative: 'o_not1' + 21 | g2_not(o2_not1, o_not2, i_not1); + | ^~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:20: Signal definition not found, creating implicitly: 'i_nor1' + : ... Suggested alternative: 'i_not1' + 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:28: Signal definition not found, creating implicitly: 'i_nor2' : ... Suggested alternative: 'i_nor1' - 21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3); - | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:32: Signal definition not found, creating implicitly: 'i_xnor2' - : ... Suggested alternative: 'i_nor2' - 21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3); - | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:41: Signal definition not found, creating implicitly: 'i_xnor3' - : ... Suggested alternative: 'i_nor3' - 21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3); - | ^~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:15: Signal definition not found, creating implicitly: 'o_xnor' + 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:36: Signal definition not found, creating implicitly: 'i_nor3' + : ... Suggested alternative: 'i_nor1' + 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:13: Signal definition not found, creating implicitly: 'o_nor' + : ... Suggested alternative: 'i_nor1' + 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), + | ^~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:11: Signal definition not found, creating implicitly: 'o2_nor' : ... Suggested alternative: 'o_nor' - 21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3); + 23 | g2_nor(o2_nor, i_nor1, i_nor2, i_nor3); + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:17: Signal definition not found, creating implicitly: 'i_or1' + : ... Suggested alternative: 'i_nor1' + 24 | or g_or(o_or, i_or1, i_or2, i_or3), + | ^~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:24: Signal definition not found, creating implicitly: 'i_or2' + : ... Suggested alternative: 'i_nor2' + 24 | or g_or(o_or, i_or1, i_or2, i_or3), + | ^~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:31: Signal definition not found, creating implicitly: 'i_or3' + : ... Suggested alternative: 'i_nor3' + 24 | or g_or(o_or, i_or1, i_or2, i_or3), + | ^~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:11: Signal definition not found, creating implicitly: 'o_or' + : ... Suggested alternative: 'o_nor' + 24 | or g_or(o_or, i_or1, i_or2, i_or3), + | ^~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:10: Signal definition not found, creating implicitly: 'o2_or' + : ... Suggested alternative: 'o2_nor' + 25 | g2_or(o2_or, i_or1, i_or2, i_or3); + | ^~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:23: Signal definition not found, creating implicitly: 'i_nand1' + : ... Suggested alternative: 'i_and1' + 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), + | ^~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:32: Signal definition not found, creating implicitly: 'i_nand2' + : ... Suggested alternative: 'i_and2' + 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), + | ^~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:41: Signal definition not found, creating implicitly: 'i_nand3' + : ... Suggested alternative: 'i_and3' + 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), + | ^~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:15: Signal definition not found, creating implicitly: 'o_nand' + : ... Suggested alternative: 'o_and' + 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:30: Signal definition not found, creating implicitly: 'i_buf1' - 22 | buf g_buf(o_buf1, o_buf2, i_buf1); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:14: Signal definition not found, creating implicitly: 'o_buf1' - : ... Suggested alternative: 'i_buf1' - 22 | buf g_buf(o_buf1, o_buf2, i_buf1); +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:27:12: Signal definition not found, creating implicitly: 'o2_nand' + : ... Suggested alternative: 'o2_and' + 27 | g2_nand(o2_nand, i_nand1, i_nand2, i_nand3); + | ^~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:20: Signal definition not found, creating implicitly: 'i_xor1' + : ... Suggested alternative: 'i_nor1' + 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:28: Signal definition not found, creating implicitly: 'i_xor2' + : ... Suggested alternative: 'i_nor2' + 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:36: Signal definition not found, creating implicitly: 'i_xor3' + : ... Suggested alternative: 'i_nor3' + 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:13: Signal definition not found, creating implicitly: 'o_xor' + : ... Suggested alternative: 'o_nor' + 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), + | ^~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:29:11: Signal definition not found, creating implicitly: 'o2_xor' + : ... Suggested alternative: 'o2_nor' + 29 | g2_xor(o2_xor, i_xor1, i_xor2, i_xor3); + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:22: Signal definition not found, creating implicitly: 'i_xnor1' + : ... Suggested alternative: 'i_nor1' + 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), + | ^~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:31: Signal definition not found, creating implicitly: 'i_xnor2' + : ... Suggested alternative: 'i_nor2' + 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), + | ^~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:40: Signal definition not found, creating implicitly: 'i_xnor3' + : ... Suggested alternative: 'i_nor3' + 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), + | ^~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:14: Signal definition not found, creating implicitly: 'o_xnor' + : ... Suggested alternative: 'o_nor' + 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:22: Signal definition not found, creating implicitly: 'o_buf2' +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:31:11: Signal definition not found, creating implicitly: 'o2_xnor' + : ... Suggested alternative: 'o2_nor' + 31 | g2_xor(o2_xnor, i_xnor1, i_xnor2, i_xnor3); + | ^~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:29: Signal definition not found, creating implicitly: 'i_buf1' + 32 | buf g_buf(o_buf1, o_buf2, i_buf1), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:13: Signal definition not found, creating implicitly: 'o_buf1' + : ... Suggested alternative: 'i_buf1' + 32 | buf g_buf(o_buf1, o_buf2, i_buf1), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:21: Signal definition not found, creating implicitly: 'o_buf2' : ... Suggested alternative: 'o_buf1' - 22 | buf g_buf(o_buf1, o_buf2, i_buf1); - | ^~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:41: Signal definition not found, creating implicitly: 'i_bufif02' - 23 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02); - | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:30: Signal definition not found, creating implicitly: 'i_bufif01' + 32 | buf g_buf(o_buf1, o_buf2, i_buf1), + | ^~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:33:11: Signal definition not found, creating implicitly: 'o2_buf1' + : ... Suggested alternative: 'o_buf1' + 33 | g2_buf(o2_buf1, o_buf2, i_buf1); + | ^~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:40: Signal definition not found, creating implicitly: 'i_bufif02' + 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:29: Signal definition not found, creating implicitly: 'i_bufif01' : ... Suggested alternative: 'i_bufif02' - 23 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02); - | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:20: Signal definition not found, creating implicitly: 'o_bufif0' + 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:19: Signal definition not found, creating implicitly: 'o_bufif0' : ... Suggested alternative: 'i_bufif01' - 23 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02); - | ^~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:41: Signal definition not found, creating implicitly: 'i_bufif12' - : ... Suggested alternative: 'i_bufif02' - 24 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12); - | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:30: Signal definition not found, creating implicitly: 'i_bufif11' - : ... Suggested alternative: 'i_bufif01' - 24 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12); - | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:20: Signal definition not found, creating implicitly: 'o_bufif1' + 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), + | ^~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:35:14: Signal definition not found, creating implicitly: 'o2_bufif0' : ... Suggested alternative: 'o_bufif0' - 24 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12); - | ^~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:41: Signal definition not found, creating implicitly: 'i_notif02' + 35 | g2_bufif0(o2_bufif0, i_bufif01, i_bufif02); + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:40: Signal definition not found, creating implicitly: 'i_bufif12' : ... Suggested alternative: 'i_bufif02' - 25 | notif0 g_notif0(o_notif0, i_notif01, i_notif02); - | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:30: Signal definition not found, creating implicitly: 'i_notif01' + 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:29: Signal definition not found, creating implicitly: 'i_bufif11' + : ... Suggested alternative: 'i_bufif01' + 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:19: Signal definition not found, creating implicitly: 'o_bufif1' + : ... Suggested alternative: 'o_bufif0' + 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), + | ^~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:37:14: Signal definition not found, creating implicitly: 'o2_bufif1' + : ... Suggested alternative: 'o2_bufif0' + 37 | g2_bufif1(o2_bufif1, i_bufif11, i_bufif12); + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:40: Signal definition not found, creating implicitly: 'i_notif02' + : ... Suggested alternative: 'i_bufif02' + 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:29: Signal definition not found, creating implicitly: 'i_notif01' : ... Suggested alternative: 'i_notif02' - 25 | notif0 g_notif0(o_notif0, i_notif01, i_notif02); - | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:20: Signal definition not found, creating implicitly: 'o_notif0' + 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:19: Signal definition not found, creating implicitly: 'o_notif0' : ... Suggested alternative: 'i_notif01' - 25 | notif0 g_notif0(o_notif0, i_notif01, i_notif02); - | ^~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:41: Signal definition not found, creating implicitly: 'i_notif12' - : ... Suggested alternative: 'i_notif02' - 26 | notif1 g_notif1(o_notif1, i_notif11, i_notif12); - | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:30: Signal definition not found, creating implicitly: 'i_notif11' - : ... Suggested alternative: 'i_notif01' - 26 | notif1 g_notif1(o_notif1, i_notif11, i_notif12); - | ^~~~~~~~~ -%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:20: Signal definition not found, creating implicitly: 'o_notif1' + 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), + | ^~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:39:14: Signal definition not found, creating implicitly: 'o2_notif0' : ... Suggested alternative: 'o_notif0' - 26 | notif1 g_notif1(o_notif1, i_notif11, i_notif12); - | ^~~~~~~~ + 39 | g2_notif0(o2_notif0, i_notif01, i_notif02); + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:40: Signal definition not found, creating implicitly: 'i_notif12' + : ... Suggested alternative: 'i_notif02' + 40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:29: Signal definition not found, creating implicitly: 'i_notif11' + : ... Suggested alternative: 'i_notif01' + 40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), + | ^~~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:19: Signal definition not found, creating implicitly: 'o_notif1' + : ... Suggested alternative: 'o_notif0' + 40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), + | ^~~~~~~~ +%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:41:14: Signal definition not found, creating implicitly: 'o2_notif1' + : ... Suggested alternative: 'o2_notif0' + 41 | g2_notif1(o2_notif1, i_notif11, i_notif12); + | ^~~~~~~~~ diff --git a/test_regress/t/t_gate_primitives_implicit_net.v b/test_regress/t/t_gate_primitives_implicit_net.v index 7c1308524..97759afbf 100755 --- a/test_regress/t/t_gate_primitives_implicit_net.v +++ b/test_regress/t/t_gate_primitives_implicit_net.v @@ -4,98 +4,125 @@ // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; - int cyc=1; +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on - // Instantiate the primitive gates to be tested. - and g_and(o_and, i_and1, i_and2, i_and3); - not g_not(o_not1, o_not2, i_not1); - nor g_nor(o_nor, i_nor1, i_nor2, i_nor3); - or g_or(o_or, i_or1, i_or2, i_or3); - nand g_nand(o_nand, i_nand1, i_nand2, i_nand3); - xor g_xor(o_xor, i_xor1, i_xor2, i_xor3); - xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3); - buf g_buf(o_buf1, o_buf2, i_buf1); - bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02); - bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12); - notif0 g_notif0(o_notif0, i_notif01, i_notif02); - notif1 g_notif1(o_notif1, i_notif11, i_notif12); +module t( + input clk + ); + int cyc=1; - // Generate random data for inputs - reg rd_data1, rd_data2, rd_data3; - always @(posedge clk) begin - rd_data1 = 1'($random); - rd_data2 = 1'($random); - rd_data3 = 1'($random); - end + // Instantiate the primitive gates to be tested. + and g_and(o_and, i_and1, i_and2, i_and3), + g2_and(o2_and, i_and1, i_and2, i_and3); + not g_not(o_not1, o_not2, i_not1), + g2_not(o2_not1, o_not2, i_not1); + nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), + g2_nor(o2_nor, i_nor1, i_nor2, i_nor3); + or g_or(o_or, i_or1, i_or2, i_or3), + g2_or(o2_or, i_or1, i_or2, i_or3); + nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), + g2_nand(o2_nand, i_nand1, i_nand2, i_nand3); + xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), + g2_xor(o2_xor, i_xor1, i_xor2, i_xor3); + xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), + g2_xor(o2_xnor, i_xnor1, i_xnor2, i_xnor3); + buf g_buf(o_buf1, o_buf2, i_buf1), + g2_buf(o2_buf1, o_buf2, i_buf1); + bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), + g2_bufif0(o2_bufif0, i_bufif01, i_bufif02); + bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), + g2_bufif1(o2_bufif1, i_bufif11, i_bufif12); + notif0 g_notif0(o_notif0, i_notif01, i_notif02), + g2_notif0(o2_notif0, i_notif01, i_notif02); + notif1 g_notif1(o_notif1, i_notif11, i_notif12), + g2_notif1(o2_notif1, i_notif11, i_notif12); - // Assign the input of primitive gates. + // Generate random data for inputs + reg rd_data1, rd_data2, rd_data3; + always @(posedge clk) begin + rd_data1 = 1'($random); + rd_data2 = 1'($random); + rd_data3 = 1'($random); + end + + // Assign the input of primitive gates. `default_nettype none - assign i_and1 = rd_data1; - assign i_and2 = rd_data2; - assign i_and3 = rd_data3; + assign i_and1 = rd_data1; + assign i_and2 = rd_data2; + assign i_and3 = rd_data3; - assign i_not1 = rd_data1; + assign i_not1 = rd_data1; - assign i_nor1 = rd_data1; - assign i_nor2 = rd_data2; - assign i_nor3 = rd_data3; + assign i_nor1 = rd_data1; + assign i_nor2 = rd_data2; + assign i_nor3 = rd_data3; - assign i_or1 = rd_data1; - assign i_or2 = rd_data2; - assign i_or3 = rd_data3; + assign i_or1 = rd_data1; + assign i_or2 = rd_data2; + assign i_or3 = rd_data3; - assign i_nand1 = rd_data1; - assign i_nand2 = rd_data2; - assign i_nand3 = rd_data3; + assign i_nand1 = rd_data1; + assign i_nand2 = rd_data2; + assign i_nand3 = rd_data3; - assign i_xor1 = rd_data1; - assign i_xor2 = rd_data2; - assign i_xor3 = rd_data3; + assign i_xor1 = rd_data1; + assign i_xor2 = rd_data2; + assign i_xor3 = rd_data3; - assign i_xnor1 = rd_data1; - assign i_xnor2 = rd_data2; - assign i_xnor3 = rd_data3; + assign i_xnor1 = rd_data1; + assign i_xnor2 = rd_data2; + assign i_xnor3 = rd_data3; - assign i_buf1 = rd_data1; + assign i_buf1 = rd_data1; - assign i_bufif01 = rd_data1; - assign i_bufif02 = rd_data2; + assign i_bufif01 = rd_data1; + assign i_bufif02 = rd_data2; - assign i_bufif11 = rd_data1; - assign i_bufif12 = rd_data2; + assign i_bufif11 = rd_data1; + assign i_bufif12 = rd_data2; - assign i_notif01 = rd_data1; - assign i_notif02 = rd_data2; + assign i_notif01 = rd_data1; + assign i_notif02 = rd_data2; - assign i_notif11 = rd_data1; - assign i_notif12 = rd_data2; + assign i_notif11 = rd_data1; + assign i_notif12 = rd_data2; - // Check the outputs of the gate instances - always @(negedge clk) begin - if (o_and !== (i_and1 & i_and2 & i_and3)) $stop; - if ((o_not1 !== ~i_not1) || (o_not2 != ~i_not1)) $stop; - if (o_nor !== !(i_nor1 | i_nor2 | i_nor3)) $stop; - if (o_or !== (i_or1 | i_or2 | i_or3)) $stop; - if (o_nand !== !(i_nand1 & i_nand2 & i_nand3)) $stop; - if (o_xor !== (i_xor1 ^ i_xor2 ^ i_xor3)) $stop; - if (o_xnor !== !(i_xnor1 ^ i_xnor2 ^ i_xnor3)) $stop; - if ((o_buf1 !== i_buf1) || (o_buf2 !== i_buf1)) $stop; - if (!(o_bufif0 == (i_bufif01 & !i_bufif02))) $stop; - if (!(o_bufif1 == (i_bufif11 & i_bufif12))) $stop; - if (!(o_notif0 == (!i_notif01 & !i_notif02))) $stop; - if (!(o_notif1 == (!i_notif11 & i_notif12))) $stop; - end + // Check the outputs of the gate instances + always @(negedge clk) begin + if (o_and !== (i_and1 & i_and2 & i_and3)) $stop; + if ((o_not1 !== ~i_not1) || (o_not2 != ~i_not1)) $stop; + if (o_nor !== !(i_nor1 | i_nor2 | i_nor3)) $stop; + if (o_or !== (i_or1 | i_or2 | i_or3)) $stop; + if (o_nand !== !(i_nand1 & i_nand2 & i_nand3)) $stop; + if (o_xor !== (i_xor1 ^ i_xor2 ^ i_xor3)) $stop; + if (o_xnor !== !(i_xnor1 ^ i_xnor2 ^ i_xnor3)) $stop; + if ((o_buf1 !== i_buf1) || (o_buf2 !== i_buf1)) $stop; + if (!(o_bufif0 == (i_bufif01 & !i_bufif02))) $stop; + if (!(o_bufif1 == (i_bufif11 & i_bufif12))) $stop; + if (!(o_notif0 == (!i_notif01 & !i_notif02))) $stop; + if (!(o_notif1 == (!i_notif11 & i_notif12))) $stop; + `checkh(o2_and, o2_and); + `checkh(o2_not1, o2_not1); + `checkh(o2_nor, o2_nor); + `checkh(o2_or, o2_or); + `checkh(o2_nand, o2_nand); + `checkh(o2_xor, o2_xor); + `checkh(o2_xnor, o2_xnor); + `checkh(o2_buf1, o2_buf1); + `checkh(o2_bufif0, o2_bufif0); + `checkh(o2_bufif1, o2_bufif1); + `checkh(o2_notif0, o2_notif0); + `checkh(o2_notif1, o2_notif1); + end - always @(posedge clk) begin - cyc = cyc + 1; - if (cyc == 100) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc = cyc + 1; + if (cyc == 100) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_scope_map.cpp b/test_regress/t/t_scope_map.cpp index df6e22e1a..df1a12dd8 100644 --- a/test_regress/t/t_scope_map.cpp +++ b/test_regress/t/t_scope_map.cpp @@ -128,6 +128,11 @@ int main(int argc, char** argv) { int varLeft = varp->range(0)->left(); int varBits = varLeft + 1; uint8_t* varData = reinterpret_cast(varp->datap()); + // Cover illegal access + if (varp->range(1000) != nullptr) { + VL_PRINTF("%%Error: Range null mismatch\n"); + return -1; + } // Check that all bits are high now for (int i = 0; i < varBits / 8; i++) { diff --git a/test_regress/t/t_time_vpi_1us1ns.py b/test_regress/t/t_time_vpi_1us1ns.py index 547804dae..4639def59 100755 --- a/test_regress/t/t_time_vpi_1us1ns.py +++ b/test_regress/t/t_time_vpi_1us1ns.py @@ -16,7 +16,7 @@ test.main_time_multiplier = 1e-6 / 1e-9 test.compile( v_flags2=['+define+time_scale_units=1us +define+time_scale_prec=1ns', test.pli_filename], - verilator_flags2=['--vpi']) + verilator_flags2=['--vpi --trace-vcd']) test.execute(expect_filename=test.golden_filename) diff --git a/test_regress/t/t_trace_fst.out b/test_regress/t/t_trace_fst.out index caf33d8b5..5dacc97f4 100644 --- a/test_regress/t/t_trace_fst.out +++ b/test_regress/t/t_trace_fst.out @@ -1,5 +1,5 @@ $date - Sat Apr 5 13:56:24 2025 + Fri Oct 10 11:48:13 2025 $end $version @@ -11,42 +11,45 @@ $end $scope module top $end $var wire 1 ! clk $end $var wire 5 " state [4:0] $end +$var wire 1 # fst_inout $end $scope module t $end $var wire 1 ! clk $end -$var int 32 # cyc [31:0] $end -$var logic 1 $ rstn $end +$var int 32 $ cyc [31:0] $end +$var logic 1 % rstn $end $var wire 5 " state [4:0] $end -$var real_parameter 64 % fst_gparam_real $end -$var real_parameter 64 & fst_lparam_real $end -$var real 64 % fst_real $end -$var integer 32 ' fst_integer [31:0] $end -$var bit 1 ( fst_bit $end -$var logic 1 ) fst_logic $end -$var int 32 * fst_int [31:0] $end -$var shortint 16 + fst_shortint [15:0] $end -$var longint 64 , fst_longint [63:0] $end -$var byte 8 - fst_byte [7:0] $end -$var parameter 32 . fst_parameter [31:0] $end -$var parameter 32 / fst_lparam [31:0] $end -$var supply0 1 0 fst_supply0 $end -$var supply1 1 1 fst_supply1 $end -$var tri0 1 0 fst_tri0 $end -$var tri1 1 1 fst_tri1 $end -$var tri 1 2 fst_tri $end -$var wire 1 3 fst_wire $end +$var real_parameter 64 & fst_gparam_real $end +$var real_parameter 64 ' fst_lparam_real $end +$var real 64 & fst_real $end +$var integer 32 ( fst_integer [31:0] $end +$var bit 1 ) fst_bit $end +$var logic 1 * fst_logic $end +$var int 32 + fst_int [31:0] $end +$var shortint 16 , fst_shortint [15:0] $end +$var longint 64 - fst_longint [63:0] $end +$var byte 8 . fst_byte [7:0] $end +$var time 64 / fst_time [63:0] $end +$var parameter 32 0 fst_parameter [31:0] $end +$var parameter 32 1 fst_lparam [31:0] $end +$var supply0 1 2 fst_supply0 $end +$var supply1 1 3 fst_supply1 $end +$var tri0 1 2 fst_tri0 $end +$var tri1 1 3 fst_tri1 $end +$var tri 1 4 fst_tri $end +$var wire 1 5 fst_wire $end +$var wire 1 # fst_inout $end $scope module test $end $var wire 1 ! clk $end -$var wire 1 $ rstn $end +$var wire 1 % rstn $end $var wire 5 " state [4:0] $end -$var logic 5 4 state_w [4:0] $end -$var logic 5 5 state_array[0] [4:0] $end -$var logic 5 6 state_array[1] [4:0] $end -$var logic 5 7 state_array[2] [4:0] $end +$var logic 5 6 state_w [4:0] $end +$var logic 5 7 state_array[0] [4:0] $end +$var logic 5 8 state_array[1] [4:0] $end +$var logic 5 9 state_array[2] [4:0] $end $scope module unnamedblk1 $end -$var int 32 8 i [31:0] $end +$var int 32 : i [31:0] $end $upscope $end $scope module unnamedblk2 $end -$var int 32 9 i [31:0] $end +$var int 32 ; i [31:0] $end $upscope $end $upscope $end $upscope $end @@ -54,975 +57,1077 @@ $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 9 -b00000000000000000000000000000000 8 +b00000000000000000000000000000000 ; +b00000000000000000000000000000000 : +b00000 9 +b00000 8 b00000 7 b00000 6 -b00000 5 -b00000 4 -03 +05 +04 +13 02 -11 -00 -b00000000000000000000000111001000 / -b00000000000000000000000001111011 . -b00000000 - -b0000000000000000000000000000000000000000000000000000000000000000 , -b0000000000000000 + -b00000000000000000000000000000000 * +b00000000000000000000000111001000 1 +b00000000000000000000000001111011 0 +b0000000000000000000000000000000000000000000000000000000000000000 / +b00000000 . +b0000000000000000000000000000000000000000000000000000000000000000 - +b0000000000000000 , +b00000000000000000000000000000000 + +0* 0) -0( -b00000000000000000000000000000000 ' -r4.56 & -r1.23 % -0$ -b00000000000000000000000000000000 # +b00000000000000000000000000000000 ( +r4.56 ' +r1.23 & +0% +b00000000000000000000000000000000 $ +0# b00000 " 0! $end #10 1! b00001 " -b00000000000000000000000000000001 # -b10100 4 -b00001 5 -b00001 6 +b00000000000000000000000000000001 $ +b0000000000000000000000000000000000000000000000000000000000001010 / +b10100 6 b00001 7 -b00000000000000000000000000000011 8 +b00001 8 +b00001 9 +b00000000000000000000000000000011 : #15 0! #20 1! -b00000000000000000000000000000010 # +b0000000000000000000000000000000000000000000000000000000000010100 / +b00000000000000000000000000000010 $ #25 0! #30 1! -b00000000000000000000000000000011 # +b00000000000000000000000000000011 $ +b0000000000000000000000000000000000000000000000000000000000011110 / #35 0! #40 1! -b00000000000000000000000000000100 # +b0000000000000000000000000000000000000000000000000000000000101000 / +b00000000000000000000000000000100 $ #45 0! #50 1! -b00000000000000000000000000000101 # +b00000000000000000000000000000101 $ +b0000000000000000000000000000000000000000000000000000000000110010 / #55 0! #60 1! -b00000000000000000000000000000110 # +b0000000000000000000000000000000000000000000000000000000000111100 / +b00000000000000000000000000000110 $ #65 0! #70 1! -b00000000000000000000000000000111 # +b00000000000000000000000000000111 $ +b0000000000000000000000000000000000000000000000000000000001000110 / #75 0! #80 1! -b00000000000000000000000000001000 # +b0000000000000000000000000000000000000000000000000000000001010000 / +b00000000000000000000000000001000 $ #85 0! #90 1! -b00000000000000000000000000001001 # +b00000000000000000000000000001001 $ +b0000000000000000000000000000000000000000000000000000000001011010 / #95 0! #100 1! -b00000000000000000000000000001010 # +b0000000000000000000000000000000000000000000000000000000001100100 / +b00000000000000000000000000001010 $ #105 0! #110 1! -b00000000000000000000000000001011 # -1$ +b00000000000000000000000000001011 $ +b0000000000000000000000000000000000000000000000000000000001101110 / +1% #115 0! #120 1! -b00000000000000000000000000001100 # -b10100 7 -b01010 4 -b00000000000000000000000000000010 9 +b0000000000000000000000000000000000000000000000000000000001111000 / +b00000000000000000000000000001100 $ +b10100 9 +b01010 6 +b00000000000000000000000000000010 ; #125 0! #130 1! -b00101 4 -b01010 7 -b00000000000000000000000000001101 # -b10100 6 +b00101 6 +b01010 9 +b00000000000000000000000000001101 $ +b0000000000000000000000000000000000000000000000000000000010000010 / +b10100 8 #135 0! #140 1! -b01010 6 -b00000000000000000000000000001110 # -b00101 7 -b10110 4 -b10100 5 +b01010 8 +b0000000000000000000000000000000000000000000000000000000010001100 / +b00000000000000000000000000001110 $ +b00101 9 +b10110 6 +b10100 7 b10100 " #145 0! #150 1! b01010 " -b01010 5 -b01011 4 -b10110 7 -b00000000000000000000000000001111 # -b00101 6 +b01010 7 +b01011 6 +b10110 9 +b00000000000000000000000000001111 $ +b0000000000000000000000000000000000000000000000000000000010010110 / +b00101 8 #155 0! #160 1! -b10110 6 -b00000000000000000000000000010000 # -b01011 7 -b10001 4 -b00101 5 +b10110 8 +b0000000000000000000000000000000000000000000000000000000010100000 / +b00000000000000000000000000010000 $ +b01011 9 +b10001 6 +b00101 7 b00101 " #165 0! #170 1! b10110 " -b10110 5 -b11100 4 -b10001 7 -b00000000000000000000000000010001 # -b01011 6 +b10110 7 +b11100 6 +b10001 9 +b00000000000000000000000000010001 $ +b0000000000000000000000000000000000000000000000000000000010101010 / +b01011 8 #175 0! #180 1! -b10001 6 -b00000000000000000000000000010010 # -b11100 7 -b01110 4 -b01011 5 +b10001 8 +b0000000000000000000000000000000000000000000000000000000010110100 / +b00000000000000000000000000010010 $ +b11100 9 +b01110 6 +b01011 7 b01011 " #185 0! #190 1! b10001 " -b10001 5 -b00111 4 -b01110 7 -b00000000000000000000000000010011 # -b11100 6 +b10001 7 +b00111 6 +b01110 9 +b00000000000000000000000000010011 $ +b0000000000000000000000000000000000000000000000000000000010111110 / +b11100 8 #195 0! #200 1! -b01110 6 -b00000000000000000000000000010100 # -b00111 7 -b10111 4 -b11100 5 +b01110 8 +b0000000000000000000000000000000000000000000000000000000011001000 / +b00000000000000000000000000010100 $ +b00111 9 +b10111 6 +b11100 7 b11100 " #205 0! #210 1! b01110 " -b01110 5 -b11111 4 -b10111 7 -b00000000000000000000000000010101 # -b00111 6 +b01110 7 +b11111 6 +b10111 9 +b00000000000000000000000000010101 $ +b0000000000000000000000000000000000000000000000000000000011010010 / +b00111 8 #215 0! #220 1! -b10111 6 -b00000000000000000000000000010110 # -b11111 7 -b11011 4 -b00111 5 +b10111 8 +b0000000000000000000000000000000000000000000000000000000011011100 / +b00000000000000000000000000010110 $ +b11111 9 +b11011 6 +b00111 7 b00111 " #225 0! #230 1! b10111 " -b10111 5 -b11001 4 -b11011 7 -b00000000000000000000000000010111 # -b11111 6 +b10111 7 +b11001 6 +b11011 9 +b00000000000000000000000000010111 $ +b0000000000000000000000000000000000000000000000000000000011100110 / +b11111 8 #235 0! #240 1! -b11011 6 -b00000000000000000000000000011000 # -b11001 7 -b11000 4 -b11111 5 +b11011 8 +b0000000000000000000000000000000000000000000000000000000011110000 / +b00000000000000000000000000011000 $ +b11001 9 +b11000 6 +b11111 7 b11111 " #245 0! #250 1! b11011 " -b11011 5 -b01100 4 -b11000 7 -b00000000000000000000000000011001 # -b11001 6 +b11011 7 +b01100 6 +b11000 9 +b00000000000000000000000000011001 $ +b0000000000000000000000000000000000000000000000000000000011111010 / +b11001 8 #255 0! #260 1! -b11000 6 -b00000000000000000000000000011010 # -b01100 7 -b00110 4 -b11001 5 +b11000 8 +b0000000000000000000000000000000000000000000000000000000100000100 / +b00000000000000000000000000011010 $ +b01100 9 +b00110 6 +b11001 7 b11001 " #265 0! #270 1! b11000 " -b11000 5 -b00011 4 -b00110 7 -b00000000000000000000000000011011 # -b01100 6 +b11000 7 +b00011 6 +b00110 9 +b00000000000000000000000000011011 $ +b0000000000000000000000000000000000000000000000000000000100001110 / +b01100 8 #275 0! #280 1! -b00110 6 -b00000000000000000000000000011100 # -b00011 7 -b10101 4 -b01100 5 +b00110 8 +b0000000000000000000000000000000000000000000000000000000100011000 / +b00000000000000000000000000011100 $ +b00011 9 +b10101 6 +b01100 7 b01100 " #285 0! #290 1! b00110 " -b00110 5 -b11110 4 -b10101 7 -b00000000000000000000000000011101 # -b00011 6 +b00110 7 +b11110 6 +b10101 9 +b00000000000000000000000000011101 $ +b0000000000000000000000000000000000000000000000000000000100100010 / +b00011 8 #295 0! #300 1! -b10101 6 -b00000000000000000000000000011110 # -b11110 7 -b01111 4 -b00011 5 +b10101 8 +b0000000000000000000000000000000000000000000000000000000100101100 / +b00000000000000000000000000011110 $ +b11110 9 +b01111 6 +b00011 7 b00011 " #305 0! #310 1! b10101 " -b10101 5 -b10011 4 -b01111 7 -b00000000000000000000000000011111 # -b11110 6 +b10101 7 +b10011 6 +b01111 9 +b00000000000000000000000000011111 $ +b0000000000000000000000000000000000000000000000000000000100110110 / +b11110 8 #315 0! #320 1! -b01111 6 -b00000000000000000000000000100000 # -b10011 7 -b11101 4 -b11110 5 +b01111 8 +b0000000000000000000000000000000000000000000000000000000101000000 / +b00000000000000000000000000100000 $ +b10011 9 +b11101 6 +b11110 7 b11110 " #325 0! #330 1! b01111 " -b01111 5 -b11010 4 -b11101 7 -b00000000000000000000000000100001 # -b10011 6 +b01111 7 +b11010 6 +b11101 9 +b00000000000000000000000000100001 $ +b0000000000000000000000000000000000000000000000000000000101001010 / +b10011 8 #335 0! #340 1! -b11101 6 -b00000000000000000000000000100010 # -b11010 7 -b01101 4 -b10011 5 +b11101 8 +b0000000000000000000000000000000000000000000000000000000101010100 / +b00000000000000000000000000100010 $ +b11010 9 +b01101 6 +b10011 7 b10011 " #345 0! #350 1! b11101 " -b11101 5 -b10010 4 -b01101 7 -b00000000000000000000000000100011 # -b11010 6 +b11101 7 +b10010 6 +b01101 9 +b00000000000000000000000000100011 $ +b0000000000000000000000000000000000000000000000000000000101011110 / +b11010 8 #355 0! #360 1! -b01101 6 -b00000000000000000000000000100100 # -b10010 7 -b01001 4 -b11010 5 +b01101 8 +b0000000000000000000000000000000000000000000000000000000101101000 / +b00000000000000000000000000100100 $ +b10010 9 +b01001 6 +b11010 7 b11010 " #365 0! #370 1! b01101 " -b01101 5 -b10000 4 -b01001 7 -b00000000000000000000000000100101 # -b10010 6 +b01101 7 +b10000 6 +b01001 9 +b00000000000000000000000000100101 $ +b0000000000000000000000000000000000000000000000000000000101110010 / +b10010 8 #375 0! #380 1! -b01001 6 -b00000000000000000000000000100110 # -b10000 7 -b01000 4 -b10010 5 +b01001 8 +b0000000000000000000000000000000000000000000000000000000101111100 / +b00000000000000000000000000100110 $ +b10000 9 +b01000 6 +b10010 7 b10010 " #385 0! #390 1! b01001 " -b01001 5 -b00100 4 -b01000 7 -b00000000000000000000000000100111 # -b10000 6 +b01001 7 +b00100 6 +b01000 9 +b00000000000000000000000000100111 $ +b0000000000000000000000000000000000000000000000000000000110000110 / +b10000 8 #395 0! #400 1! -b01000 6 -b00000000000000000000000000101000 # -b00100 7 -b00010 4 -b10000 5 +b01000 8 +b0000000000000000000000000000000000000000000000000000000110010000 / +b00000000000000000000000000101000 $ +b00100 9 +b00010 6 +b10000 7 b10000 " #405 0! #410 1! b01000 " -b01000 5 -b00001 4 -b00010 7 -b00000000000000000000000000101001 # -b00100 6 +b01000 7 +b00001 6 +b00010 9 +b00000000000000000000000000101001 $ +b0000000000000000000000000000000000000000000000000000000110011010 / +b00100 8 #415 0! #420 1! -b00010 6 -b00000000000000000000000000101010 # -b00001 7 -b10100 4 -b00100 5 +b00010 8 +b0000000000000000000000000000000000000000000000000000000110100100 / +b00000000000000000000000000101010 $ +b00001 9 +b10100 6 +b00100 7 b00100 " #425 0! #430 1! b00010 " -b00010 5 -b01010 4 -b10100 7 -b00000000000000000000000000101011 # -b00001 6 +b00010 7 +b01010 6 +b10100 9 +b00000000000000000000000000101011 $ +b0000000000000000000000000000000000000000000000000000000110101110 / +b00001 8 #435 0! #440 1! -b10100 6 -b00000000000000000000000000101100 # -b01010 7 -b00101 4 -b00001 5 +b10100 8 +b0000000000000000000000000000000000000000000000000000000110111000 / +b00000000000000000000000000101100 $ +b01010 9 +b00101 6 +b00001 7 b00001 " #445 0! #450 1! b10100 " -b10100 5 -b10110 4 -b00101 7 -b00000000000000000000000000101101 # -b01010 6 +b10100 7 +b10110 6 +b00101 9 +b00000000000000000000000000101101 $ +b0000000000000000000000000000000000000000000000000000000111000010 / +b01010 8 #455 0! #460 1! -b00101 6 -b00000000000000000000000000101110 # -b10110 7 -b01011 4 -b01010 5 +b00101 8 +b0000000000000000000000000000000000000000000000000000000111001100 / +b00000000000000000000000000101110 $ +b10110 9 +b01011 6 +b01010 7 b01010 " #465 0! #470 1! b00101 " -b00101 5 -b10001 4 -b01011 7 -b00000000000000000000000000101111 # -b10110 6 +b00101 7 +b10001 6 +b01011 9 +b00000000000000000000000000101111 $ +b0000000000000000000000000000000000000000000000000000000111010110 / +b10110 8 #475 0! #480 1! -b01011 6 -b00000000000000000000000000110000 # -b10001 7 -b11100 4 -b10110 5 +b01011 8 +b0000000000000000000000000000000000000000000000000000000111100000 / +b00000000000000000000000000110000 $ +b10001 9 +b11100 6 +b10110 7 b10110 " #485 0! #490 1! b01011 " -b01011 5 -b01110 4 -b11100 7 -b00000000000000000000000000110001 # -b10001 6 +b01011 7 +b01110 6 +b11100 9 +b00000000000000000000000000110001 $ +b0000000000000000000000000000000000000000000000000000000111101010 / +b10001 8 #495 0! #500 1! -b11100 6 -b00000000000000000000000000110010 # -b01110 7 -b00111 4 -b10001 5 +b11100 8 +b0000000000000000000000000000000000000000000000000000000111110100 / +b00000000000000000000000000110010 $ +b01110 9 +b00111 6 +b10001 7 b10001 " #505 0! #510 1! b11100 " -b11100 5 -b10111 4 -b00111 7 -b00000000000000000000000000110011 # -b01110 6 +b11100 7 +b10111 6 +b00111 9 +b00000000000000000000000000110011 $ +b0000000000000000000000000000000000000000000000000000000111111110 / +b01110 8 #515 0! #520 1! -b00111 6 -b00000000000000000000000000110100 # -b10111 7 -b11111 4 -b01110 5 +b00111 8 +b0000000000000000000000000000000000000000000000000000001000001000 / +b00000000000000000000000000110100 $ +b10111 9 +b11111 6 +b01110 7 b01110 " #525 0! #530 1! b00111 " -b00111 5 -b11011 4 -b11111 7 -b00000000000000000000000000110101 # -b10111 6 +b00111 7 +b11011 6 +b11111 9 +b00000000000000000000000000110101 $ +b0000000000000000000000000000000000000000000000000000001000010010 / +b10111 8 #535 0! #540 1! -b11111 6 -b00000000000000000000000000110110 # -b11011 7 -b11001 4 -b10111 5 +b11111 8 +b0000000000000000000000000000000000000000000000000000001000011100 / +b00000000000000000000000000110110 $ +b11011 9 +b11001 6 +b10111 7 b10111 " #545 0! #550 1! b11111 " -b11111 5 -b11000 4 -b11001 7 -b00000000000000000000000000110111 # -b11011 6 +b11111 7 +b11000 6 +b11001 9 +b00000000000000000000000000110111 $ +b0000000000000000000000000000000000000000000000000000001000100110 / +b11011 8 #555 0! #560 1! -b11001 6 -b00000000000000000000000000111000 # -b11000 7 -b01100 4 -b11011 5 +b11001 8 +b0000000000000000000000000000000000000000000000000000001000110000 / +b00000000000000000000000000111000 $ +b11000 9 +b01100 6 +b11011 7 b11011 " #565 0! #570 1! b11001 " -b11001 5 -b00110 4 -b01100 7 -b00000000000000000000000000111001 # -b11000 6 +b11001 7 +b00110 6 +b01100 9 +b00000000000000000000000000111001 $ +b0000000000000000000000000000000000000000000000000000001000111010 / +b11000 8 #575 0! #580 1! -b01100 6 -b00000000000000000000000000111010 # -b00110 7 -b00011 4 -b11000 5 +b01100 8 +b0000000000000000000000000000000000000000000000000000001001000100 / +b00000000000000000000000000111010 $ +b00110 9 +b00011 6 +b11000 7 b11000 " #585 0! #590 1! b01100 " -b01100 5 -b10101 4 -b00011 7 -b00000000000000000000000000111011 # -b00110 6 +b01100 7 +b10101 6 +b00011 9 +b00000000000000000000000000111011 $ +b0000000000000000000000000000000000000000000000000000001001001110 / +b00110 8 #595 0! #600 1! -b00011 6 -b00000000000000000000000000111100 # -b10101 7 -b11110 4 -b00110 5 +b00011 8 +b0000000000000000000000000000000000000000000000000000001001011000 / +b00000000000000000000000000111100 $ +b10101 9 +b11110 6 +b00110 7 b00110 " #605 0! #610 1! b00011 " -b00011 5 -b01111 4 -b11110 7 -b00000000000000000000000000111101 # -b10101 6 +b00011 7 +b01111 6 +b11110 9 +b00000000000000000000000000111101 $ +b0000000000000000000000000000000000000000000000000000001001100010 / +b10101 8 #615 0! #620 1! -b11110 6 -b00000000000000000000000000111110 # -b01111 7 -b10011 4 -b10101 5 +b11110 8 +b0000000000000000000000000000000000000000000000000000001001101100 / +b00000000000000000000000000111110 $ +b01111 9 +b10011 6 +b10101 7 b10101 " #625 0! #630 1! b11110 " -b11110 5 -b11101 4 -b10011 7 -b00000000000000000000000000111111 # -b01111 6 +b11110 7 +b11101 6 +b10011 9 +b00000000000000000000000000111111 $ +b0000000000000000000000000000000000000000000000000000001001110110 / +b01111 8 #635 0! #640 1! -b10011 6 -b00000000000000000000000001000000 # -b11101 7 -b11010 4 -b01111 5 +b10011 8 +b0000000000000000000000000000000000000000000000000000001010000000 / +b00000000000000000000000001000000 $ +b11101 9 +b11010 6 +b01111 7 b01111 " #645 0! #650 1! b10011 " -b10011 5 -b01101 4 -b11010 7 -b00000000000000000000000001000001 # -b11101 6 +b10011 7 +b01101 6 +b11010 9 +b00000000000000000000000001000001 $ +b0000000000000000000000000000000000000000000000000000001010001010 / +b11101 8 #655 0! #660 1! -b11010 6 -b00000000000000000000000001000010 # -b01101 7 -b10010 4 -b11101 5 +b11010 8 +b0000000000000000000000000000000000000000000000000000001010010100 / +b00000000000000000000000001000010 $ +b01101 9 +b10010 6 +b11101 7 b11101 " #665 0! #670 1! b11010 " -b11010 5 -b01001 4 -b10010 7 -b00000000000000000000000001000011 # -b01101 6 +b11010 7 +b01001 6 +b10010 9 +b00000000000000000000000001000011 $ +b0000000000000000000000000000000000000000000000000000001010011110 / +b01101 8 #675 0! #680 1! -b10010 6 -b00000000000000000000000001000100 # -b01001 7 -b10000 4 -b01101 5 +b10010 8 +b0000000000000000000000000000000000000000000000000000001010101000 / +b00000000000000000000000001000100 $ +b01001 9 +b10000 6 +b01101 7 b01101 " #685 0! #690 1! b10010 " -b10010 5 -b01000 4 -b10000 7 -b00000000000000000000000001000101 # -b01001 6 +b10010 7 +b01000 6 +b10000 9 +b00000000000000000000000001000101 $ +b0000000000000000000000000000000000000000000000000000001010110010 / +b01001 8 #695 0! #700 1! -b10000 6 -b00000000000000000000000001000110 # -b01000 7 -b00100 4 -b01001 5 +b10000 8 +b0000000000000000000000000000000000000000000000000000001010111100 / +b00000000000000000000000001000110 $ +b01000 9 +b00100 6 +b01001 7 b01001 " #705 0! #710 1! b10000 " -b10000 5 -b00010 4 -b00100 7 -b00000000000000000000000001000111 # -b01000 6 +b10000 7 +b00010 6 +b00100 9 +b00000000000000000000000001000111 $ +b0000000000000000000000000000000000000000000000000000001011000110 / +b01000 8 #715 0! #720 1! -b00100 6 -b00000000000000000000000001001000 # -b00010 7 -b00001 4 -b01000 5 +b00100 8 +b0000000000000000000000000000000000000000000000000000001011010000 / +b00000000000000000000000001001000 $ +b00010 9 +b00001 6 +b01000 7 b01000 " #725 0! #730 1! b00100 " -b00100 5 -b10100 4 -b00001 7 -b00000000000000000000000001001001 # -b00010 6 +b00100 7 +b10100 6 +b00001 9 +b00000000000000000000000001001001 $ +b0000000000000000000000000000000000000000000000000000001011011010 / +b00010 8 #735 0! #740 1! -b00001 6 -b00000000000000000000000001001010 # -b10100 7 -b01010 4 -b00010 5 +b00001 8 +b0000000000000000000000000000000000000000000000000000001011100100 / +b00000000000000000000000001001010 $ +b10100 9 +b01010 6 +b00010 7 b00010 " #745 0! #750 1! b00001 " -b00001 5 -b00101 4 -b01010 7 -b00000000000000000000000001001011 # -b10100 6 +b00001 7 +b00101 6 +b01010 9 +b00000000000000000000000001001011 $ +b0000000000000000000000000000000000000000000000000000001011101110 / +b10100 8 #755 0! #760 1! -b01010 6 -b00000000000000000000000001001100 # -b00101 7 -b10110 4 -b10100 5 +b01010 8 +b0000000000000000000000000000000000000000000000000000001011111000 / +b00000000000000000000000001001100 $ +b00101 9 +b10110 6 +b10100 7 b10100 " #765 0! #770 1! b01010 " -b01010 5 -b01011 4 -b10110 7 -b00000000000000000000000001001101 # -b00101 6 +b01010 7 +b01011 6 +b10110 9 +b00000000000000000000000001001101 $ +b0000000000000000000000000000000000000000000000000000001100000010 / +b00101 8 #775 0! #780 1! -b10110 6 -b00000000000000000000000001001110 # -b01011 7 -b10001 4 -b00101 5 +b10110 8 +b0000000000000000000000000000000000000000000000000000001100001100 / +b00000000000000000000000001001110 $ +b01011 9 +b10001 6 +b00101 7 b00101 " #785 0! #790 1! b10110 " -b10110 5 -b11100 4 -b10001 7 -b00000000000000000000000001001111 # -b01011 6 +b10110 7 +b11100 6 +b10001 9 +b00000000000000000000000001001111 $ +b0000000000000000000000000000000000000000000000000000001100010110 / +b01011 8 #795 0! #800 1! -b10001 6 -b00000000000000000000000001010000 # -b11100 7 -b01110 4 -b01011 5 +b10001 8 +b0000000000000000000000000000000000000000000000000000001100100000 / +b00000000000000000000000001010000 $ +b11100 9 +b01110 6 +b01011 7 b01011 " #805 0! #810 1! b10001 " -b10001 5 -b00111 4 -b01110 7 -b00000000000000000000000001010001 # -b11100 6 +b10001 7 +b00111 6 +b01110 9 +b00000000000000000000000001010001 $ +b0000000000000000000000000000000000000000000000000000001100101010 / +b11100 8 #815 0! #820 1! -b01110 6 -b00000000000000000000000001010010 # -b00111 7 -b10111 4 -b11100 5 +b01110 8 +b0000000000000000000000000000000000000000000000000000001100110100 / +b00000000000000000000000001010010 $ +b00111 9 +b10111 6 +b11100 7 b11100 " #825 0! #830 1! b01110 " -b01110 5 -b11111 4 -b10111 7 -b00000000000000000000000001010011 # -b00111 6 +b01110 7 +b11111 6 +b10111 9 +b00000000000000000000000001010011 $ +b0000000000000000000000000000000000000000000000000000001100111110 / +b00111 8 #835 0! #840 1! -b10111 6 -b00000000000000000000000001010100 # -b11111 7 -b11011 4 -b00111 5 +b10111 8 +b0000000000000000000000000000000000000000000000000000001101001000 / +b00000000000000000000000001010100 $ +b11111 9 +b11011 6 +b00111 7 b00111 " #845 0! #850 1! b10111 " -b10111 5 -b11001 4 -b11011 7 -b00000000000000000000000001010101 # -b11111 6 +b10111 7 +b11001 6 +b11011 9 +b00000000000000000000000001010101 $ +b0000000000000000000000000000000000000000000000000000001101010010 / +b11111 8 #855 0! #860 1! -b11011 6 -b00000000000000000000000001010110 # -b11001 7 -b11000 4 -b11111 5 +b11011 8 +b0000000000000000000000000000000000000000000000000000001101011100 / +b00000000000000000000000001010110 $ +b11001 9 +b11000 6 +b11111 7 b11111 " #865 0! #870 1! b11011 " -b11011 5 -b01100 4 -b11000 7 -b00000000000000000000000001010111 # -b11001 6 +b11011 7 +b01100 6 +b11000 9 +b00000000000000000000000001010111 $ +b0000000000000000000000000000000000000000000000000000001101100110 / +b11001 8 #875 0! #880 1! -b11000 6 -b00000000000000000000000001011000 # -b01100 7 -b00110 4 -b11001 5 +b11000 8 +b0000000000000000000000000000000000000000000000000000001101110000 / +b00000000000000000000000001011000 $ +b01100 9 +b00110 6 +b11001 7 b11001 " #885 0! #890 1! b11000 " -b11000 5 -b00011 4 -b00110 7 -b00000000000000000000000001011001 # -b01100 6 +b11000 7 +b00011 6 +b00110 9 +b00000000000000000000000001011001 $ +b0000000000000000000000000000000000000000000000000000001101111010 / +b01100 8 #895 0! #900 1! -b00110 6 -b00000000000000000000000001011010 # -b00011 7 -b10101 4 -b01100 5 +b00110 8 +b0000000000000000000000000000000000000000000000000000001110000100 / +b00000000000000000000000001011010 $ +b00011 9 +b10101 6 +b01100 7 b01100 " #905 0! #910 1! b00110 " -b00110 5 -b11110 4 -b10101 7 -b00000000000000000000000001011011 # -b00011 6 +b00110 7 +b11110 6 +b10101 9 +b00000000000000000000000001011011 $ +b0000000000000000000000000000000000000000000000000000001110001110 / +b00011 8 #915 0! #920 1! -b10101 6 -b00000000000000000000000001011100 # -b11110 7 -b01111 4 -b00011 5 +b10101 8 +b0000000000000000000000000000000000000000000000000000001110011000 / +b00000000000000000000000001011100 $ +b11110 9 +b01111 6 +b00011 7 b00011 " #925 0! #930 1! b10101 " -b10101 5 -b10011 4 -b01111 7 -b00000000000000000000000001011101 # -b11110 6 +b10101 7 +b10011 6 +b01111 9 +b00000000000000000000000001011101 $ +b0000000000000000000000000000000000000000000000000000001110100010 / +b11110 8 #935 0! #940 1! -b01111 6 -b00000000000000000000000001011110 # -b10011 7 -b11101 4 -b11110 5 +b01111 8 +b0000000000000000000000000000000000000000000000000000001110101100 / +b00000000000000000000000001011110 $ +b10011 9 +b11101 6 +b11110 7 b11110 " #945 0! #950 1! b01111 " -b01111 5 -b11010 4 -b11101 7 -b00000000000000000000000001011111 # -b10011 6 +b01111 7 +b11010 6 +b11101 9 +b00000000000000000000000001011111 $ +b0000000000000000000000000000000000000000000000000000001110110110 / +b10011 8 #955 0! #960 1! -b11101 6 -b00000000000000000000000001100000 # -b11010 7 -b01101 4 -b10011 5 +b11101 8 +b0000000000000000000000000000000000000000000000000000001111000000 / +b00000000000000000000000001100000 $ +b11010 9 +b01101 6 +b10011 7 b10011 " #965 0! #970 1! b11101 " -b11101 5 -b10010 4 -b01101 7 -b00000000000000000000000001100001 # -b11010 6 +b11101 7 +b10010 6 +b01101 9 +b00000000000000000000000001100001 $ +b0000000000000000000000000000000000000000000000000000001111001010 / +b11010 8 #975 0! #980 1! -b01101 6 -b00000000000000000000000001100010 # -b10010 7 -b01001 4 -b11010 5 +b01101 8 +b0000000000000000000000000000000000000000000000000000001111010100 / +b00000000000000000000000001100010 $ +b10010 9 +b01001 6 +b11010 7 b11010 " #985 0! #990 1! b01101 " -b01101 5 -b10000 4 -b01001 7 -b00000000000000000000000001100011 # -b10010 6 +b01101 7 +b10000 6 +b01001 9 +b00000000000000000000000001100011 $ +b0000000000000000000000000000000000000000000000000000001111011110 / +b10010 8 #995 0! #1000 1! -b01001 6 -b00000000000000000000000001100100 # -b10000 7 -b01000 4 -b10010 5 +b01001 8 +b0000000000000000000000000000000000000000000000000000001111101000 / +b00000000000000000000000001100100 $ +b10000 9 +b01000 6 +b10010 7 b10010 " diff --git a/test_regress/t/t_trace_fst.v b/test_regress/t/t_trace_fst.v index 288ddadfc..44ac7feac 100644 --- a/test_regress/t/t_trace_fst.v +++ b/test_regress/t/t_trace_fst.v @@ -5,11 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - state, - // Inputs - clk - ); + // Outputs + state, + // Inouts + fst_inout, + // Inputs + clk + ); input clk; @@ -27,6 +29,7 @@ module t (/*AUTOARG*/ shortint fst_shortint; longint fst_longint; byte fst_byte; + time fst_time; parameter fst_parameter = 123; localparam fst_lparam = 456; @@ -36,6 +39,7 @@ module t (/*AUTOARG*/ tri1 fst_tri1; tri fst_tri; wire fst_wire; + inout fst_inout; Test test (/*AUTOINST*/ // Outputs @@ -47,6 +51,7 @@ module t (/*AUTOARG*/ // Test loop always @ (posedge clk) begin cyc <= cyc + 1; + fst_time <= $time; if (cyc==0) begin // Setup rstn <= ~'1; diff --git a/test_regress/t/t_trace_saif.out b/test_regress/t/t_trace_saif.out index b3929c760..ae73a26b2 100644 --- a/test_regress/t/t_trace_saif.out +++ b/test_regress/t/t_trace_saif.out @@ -14,6 +14,7 @@ (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE t (NET @@ -402,6 +403,70 @@ (fst_byte\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) + (fst_time\[2\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) + (fst_time\[3\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 75)) + (fst_time\[4\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 62)) + (fst_time\[5\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 31)) + (fst_time\[6\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 15)) + (fst_time\[7\] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 7)) + (fst_time\[8\] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 3)) + (fst_time\[9\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_time\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) @@ -472,6 +537,7 @@ (fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE test (NET diff --git a/test_regress/t/t_tri_various.v b/test_regress/t/t_tri_various.v index 5abf42b1e..e492ec1de 100644 --- a/test_regress/t/t_tri_various.v +++ b/test_regress/t/t_tri_various.v @@ -4,45 +4,48 @@ // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; +module t ( + clk +); + input clk; - reg [31:0] state; initial state=0; + reg [31:0] state; + initial state = 0; - wire A = state[0]; - wire OE = state[1]; - wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9; - wire [3:0] Z10; - wire Z11; + wire A = state[0]; + wire OE = state[1]; + wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9; + wire [3:0] Z10; + wire Z11; - Test1 test1(/*AUTOINST*/ + Test1 test1 ( /*AUTOINST*/ // Inouts .Z1 (Z1), // Inputs .OE (OE), .A (A)); - Test2 test2(/*AUTOINST*/ + Test2 test2 ( /*AUTOINST*/ // Inouts .Z2 (Z2), // Inputs .OE (OE), .A (A)); - Test3 test3(/*AUTOINST*/ + Test3 test3 ( /*AUTOINST*/ // Inouts .Z3 (Z3), // Inputs .OE (OE), .A (A)); - Test4 test4(/*AUTOINST*/ + Test4 test4 ( /*AUTOINST*/ // Outputs .Z4 (Z4), // Inouts .Z5 (Z5)); - Test5 test5(/*AUTOINST*/ + Test5 test5 ( /*AUTOINST*/ // Inouts .Z6 (Z6), .Z7 (Z7), @@ -51,116 +54,126 @@ module t (clk); // Inputs .OE (OE)); - Test6 test6(/*AUTOINST*/ + Test6 test6 ( /*AUTOINST*/ // Inouts .Z10 (Z10[3:0]), // Inputs .OE (OE)); - Test7 test7(/*AUTOINST*/ + Test7 test7 ( /*AUTOINST*/ // Outputs .Z11 (Z11), // Inputs .state (state[2:0])); - always @(posedge clk) begin - state <= state + 1; + always @(posedge clk) begin + state <= state + 1; `ifdef TEST_VERBOSE - $write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n", - $time, state, Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11); + $write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n", $time, + state, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11); `endif - if(state == 0) begin - if(Z1 !== 1'b1) $stop; // tests pullups - if(Z2 !== 1'b1) $stop; - if(Z3 !== 1'b1) $stop; + if (state == 0) begin + if (Z1 !== 1'b1) $stop; // tests pullups + if (Z2 !== 1'b1) $stop; + if (Z3 !== 1'b1) $stop; `ifndef VERILATOR - if(Z4 !== 1'b1) $stop; + if (Z4 !== 1'b1) $stop; `endif - if(Z5 !== 1'b1) $stop; - if(Z6 !== 1'b1) $stop; - if(Z7 !== 1'b0) $stop; - if(Z8 !== 1'b0) $stop; - if(Z9 !== 1'b1) $stop; - if(Z10 !== 4'b0001) $stop; - if(Z11 !== 1'b0) $stop; - end - else if(state == 1) begin - if(Z1 !== 1'b1) $stop; // tests pullup - if(Z2 !== 1'b1) $stop; - if(Z3 !== 1'b1) $stop; + if (Z5 !== 1'b1) $stop; + if (Z6 !== 1'b1) $stop; + if (Z7 !== 1'b0) $stop; + if (Z8 !== 1'b0) $stop; + if (Z9 !== 1'b1) $stop; + if (Z10 !== 4'b0001) $stop; + if (Z11 !== 1'b0) $stop; + end + else if (state == 1) begin + if (Z1 !== 1'b1) $stop; // tests pullup + if (Z2 !== 1'b1) $stop; + if (Z3 !== 1'b1) $stop; `ifndef VERILATOR - if(Z4 !== 1'b1) $stop; + if (Z4 !== 1'b1) $stop; `endif - if(Z5 !== 1'b1) $stop; - if(Z6 !== 1'b1) $stop; - if(Z7 !== 1'b0) $stop; - if(Z8 !== 1'b0) $stop; - if(Z9 !== 1'b1) $stop; - if(Z10 !== 4'b0001) $stop; - if(Z11 !== 1'b1) $stop; - end - else if(state == 2) begin - if(Z1 !== 1'b0) $stop; // tests output driver low - if(Z2 !== 1'b0) $stop; - if(Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts + if (Z5 !== 1'b1) $stop; + if (Z6 !== 1'b1) $stop; + if (Z7 !== 1'b0) $stop; + if (Z8 !== 1'b0) $stop; + if (Z9 !== 1'b1) $stop; + if (Z10 !== 4'b0001) $stop; + if (Z11 !== 1'b1) $stop; + end + else if (state == 2) begin + if (Z1 !== 1'b0) $stop; // tests output driver low + if (Z2 !== 1'b0) $stop; + if (Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts `ifndef VERILATOR - if(Z4 !== 1'b1) $stop; + if (Z4 !== 1'b1) $stop; `endif - if(Z5 !== 1'b1) $stop; - if(Z6 !== 1'b0) $stop; - if(Z7 !== 1'b1) $stop; - if(Z8 !== 1'b1) $stop; - if(Z9 !== 1'b0) $stop; - if(Z10 !== 4'b0010) $stop; - //if(Z11 !== 1'bx) $stop; // Doesn't matter - end - else if(state == 3) begin - if(Z1 !== 1'b1) $stop; // tests output driver high - if(Z2 !== 1'b1) $stop; - if(Z3 !== 1'b1) $stop; + if (Z5 !== 1'b1) $stop; + if (Z6 !== 1'b0) $stop; + if (Z7 !== 1'b1) $stop; + if (Z8 !== 1'b1) $stop; + if (Z9 !== 1'b0) $stop; + if (Z10 !== 4'b0010) $stop; + //if(Z11 !== 1'bx) $stop; // Doesn't matter + end + else if (state == 3) begin + if (Z1 !== 1'b1) $stop; // tests output driver high + if (Z2 !== 1'b1) $stop; + if (Z3 !== 1'b1) $stop; `ifndef VERILATOR - if(Z4 !== 1'b1) $stop; + if (Z4 !== 1'b1) $stop; `endif - if(Z5 !== 1'b1) $stop; - if(Z6 !== 1'b0) $stop; - if(Z7 !== 1'b1) $stop; - if(Z8 !== 1'b1) $stop; - if(Z9 !== 1'b0) $stop; - if(Z10 !== 4'b0010) $stop; - if(Z11 !== 1'b1) $stop; - end - else if(state == 4) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - pullup(Z1); - pullup(Z2); - pullup(Z3); - pullup(Z4); - pullup(Z5); - pullup(Z6); - pulldown(Z7); - pullup(Z8); - pulldown(Z9); - pulldown pd10[3:0] (Z10); + if (Z5 !== 1'b1) $stop; + if (Z6 !== 1'b0) $stop; + if (Z7 !== 1'b1) $stop; + if (Z8 !== 1'b1) $stop; + if (Z9 !== 1'b0) $stop; + if (Z10 !== 4'b0010) $stop; + if (Z11 !== 1'b1) $stop; + end + else if (state == 4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + pullup (Z1), (Z2); + pullup (Z3); + pullup (Z4); + pullup (Z5); + pullup (Z6); + pulldown (Z7), (Z9); + pullup (Z8); + pulldown pd10[3:0] (Z10); endmodule -module Test1(input OE, input A, inout Z1); - assign Z1 = (OE) ? A : 1'bz; +module Test1 ( + input OE, + input A, + inout Z1 +); + assign Z1 = (OE) ? A : 1'bz; endmodule -module Test2(input OE, input A, inout Z2); - assign Z2 = (OE) ? A : 1'bz; +module Test2 ( + input OE, + input A, + inout Z2 +); + assign Z2 = (OE) ? A : 1'bz; endmodule // mixed low-Z and tristate -module Test3(input OE, input A, inout Z3); - assign Z3 = (OE) ? A : 1'bz; - assign Z3 = 1'b1; +module Test3 ( + input OE, + input A, + inout Z3 +); + assign Z3 = (OE) ? A : 1'bz; + assign Z3 = 1'b1; endmodule @@ -168,37 +181,61 @@ endmodule `ifndef VERILATOR // Note verilator doesn't know to make Z4 a tristate unless marked an inout `endif -module Test4(output Z4, inout Z5); +module Test4 ( + output Z4, + inout Z5 +); endmodule // AND gate tristates -module Test5(input OE, inout Z6, inout Z7, inout Z8, inout Z9); - assign Z6 = (OE) ? 1'b0 : 1'bz; - assign Z7 = (OE) ? 1'b1 : 1'bz; - assign Z8 = (OE) ? 1'bz : 1'b0; - assign Z9 = (OE) ? 1'bz : 1'b1; +module Test5 ( + input OE, + inout Z6, + inout Z7, + inout Z8, + inout Z9 +); + assign Z6 = (OE) ? 1'b0 : 1'bz; + assign Z7 = (OE) ? 1'b1 : 1'bz; + assign Z8 = (OE) ? 1'bz : 1'b0; + assign Z9 = (OE) ? 1'bz : 1'b1; endmodule // AND gate tristates -module Test6(input OE, inout [3:0] Z10); - wire [1:0] i; - Test6a a (.OE(OE), .Z({Z10[0],Z10[1]})); - Test6a b (.OE(~OE), .Z({Z10[2],Z10[0]})); +module Test6 ( + input OE, + inout [3:0] Z10 +); + wire [1:0] i; + Test6a a ( + .OE(OE), + .Z({Z10[0], Z10[1]}) + ); + Test6a b ( + .OE(~OE), + .Z({Z10[2], Z10[0]}) + ); endmodule -module Test6a(input OE, inout [1:0] Z); - assign Z = (OE) ? 2'b01 : 2'bzz; +module Test6a ( + input OE, + inout [1:0] Z +); + assign Z = (OE) ? 2'b01 : 2'bzz; endmodule -module Test7(input [2:0] state, output reg Z11); - always @(*) begin - casez (state) - 3'b000: Z11 = 1'b0; - 3'b0?1: Z11 = 1'b1; - default: Z11 = 1'bx; - endcase - end +module Test7 ( + input [2:0] state, + output reg Z11 +); + always @(*) begin + casez (state) + 3'b000: Z11 = 1'b0; + 3'b0?1: Z11 = 1'b1; + default: Z11 = 1'bx; + endcase + end endmodule // This is not implemented yet diff --git a/test_regress/t/t_wire_trireg_unsup.out b/test_regress/t/t_wire_trireg_unsup.out index 593710f80..a7ed87914 100644 --- a/test_regress/t/t_wire_trireg_unsup.out +++ b/test_regress/t/t_wire_trireg_unsup.out @@ -2,4 +2,23 @@ 11 | trireg unsup; | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:12:4: Unsupported: trireg + 12 | trireg (small) unsup_s; + | ^~~~~~ +%Error: t/t_wire_trireg_unsup.v:12:12: syntax error, unexpected STRENGTH keyword (strong1/etc) + 12 | trireg (small) unsup_s; + | ^~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:13:4: Unsupported: trireg + 13 | trireg (medium) unsup_m; + | ^~~~~~ +%Error: t/t_wire_trireg_unsup.v:13:12: syntax error, unexpected STRENGTH keyword (strong1/etc) + 13 | trireg (medium) unsup_m; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:14:4: Unsupported: trireg + 14 | trireg (large) unsup_l; + | ^~~~~~ +%Error: t/t_wire_trireg_unsup.v:14:12: syntax error, unexpected STRENGTH keyword (strong1/etc) + 14 | trireg (large) unsup_l; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_trireg_unsup.v b/test_regress/t/t_wire_trireg_unsup.v index 1f24693bb..b704552b4 100644 --- a/test_regress/t/t_wire_trireg_unsup.v +++ b/test_regress/t/t_wire_trireg_unsup.v @@ -9,5 +9,8 @@ module t; trireg unsup; + trireg (small) unsup_s; + trireg (medium) unsup_m; + trireg (large) unsup_l; endmodule