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Internal coverage improvements

This commit is contained in:
Wilson Snyder 2021-03-28 20:30:22 -04:00
parent f26a7c2a5d
commit 6d3ec160e1
3 changed files with 49 additions and 2 deletions
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34
test_regress/t/t_lint_rsvd_bad.out
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@ -4,7 +4,37 @@
%Error: t/t_lint_rsvd_bad.v:7:8: syntax error, unexpected IDENTIFIER %Error: t/t_lint_rsvd_bad.v:7:8: syntax error, unexpected IDENTIFIER
7 | config cfgBad; 7 | config cfgBad;
| ^~~~~~ | ^~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:8:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig' %Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:8:4: Unsupported: Verilog 2001-config reserved word not implemented: 'design'
8 | endconfig 8 | design rtlLib.top;
| ^~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:9:12: Unsupported: Verilog 2001-config reserved word not implemented: 'liblist'
9 | default liblist rtlLib;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:10:4: Unsupported: Verilog 2001-config reserved word not implemented: 'instance'
10 | instance top.a2 liblist gateLib;
| ^~~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:10:20: Unsupported: Verilog 2001-config reserved word not implemented: 'liblist'
10 | instance top.a2 liblist gateLib;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:11:4: Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: 'include'
11 | include none;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:12:4: Unsupported: Verilog 2001-config reserved word not implemented: 'library'
12 | library rtlLib *.v;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:13:4: Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: 'include'
13 | include aa;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:14:4: Unsupported: Verilog 2001-config reserved word not implemented: 'use'
14 | use gateLib;
| ^~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:15:4: Unsupported: Verilog 2001-config reserved word not implemented: 'cell'
15 | cell rtlLib.cell;
| ^~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:15:16: Unsupported: Verilog 2001-config reserved word not implemented: 'cell'
15 | cell rtlLib.cell;
| ^~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:16:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig'
16 | endconfig
| ^~~~~~~~~ | ^~~~~~~~~
%Error: Exiting due to %Error: Exiting due to

8
test_regress/t/t_lint_rsvd_bad.v
View File

@ -5,6 +5,14 @@
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
config cfgBad; config cfgBad;
design rtlLib.top;
default liblist rtlLib;
instance top.a2 liblist gateLib;
include none;
library rtlLib *.v;
include aa;
use gateLib;
cell rtlLib.cell;
endconfig endconfig
module t; module t;

9
test_regress/t/t_sys_sformat.v
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@ -74,6 +74,15 @@ module t;
$sformat(ochar,"%s","c"); $sformat(ochar,"%s","c");
if (ochar != "c") $stop; if (ochar != "c") $stop;
$swrite(str2, 4'd12);
if (str2 != "12") $stop;
$swriteb(str2, 4'd12);
if (str2 != "1100") $stop;
$swriteh(str2, 4'd12);
if (str2 != "c") $stop;
$swriteo(str2, 4'd12);
if (str2 != "14") $stop;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end