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Tests: Fix t_force_release to reflect intent (#7906) 

Signed-off-by: Artur Bieniek <abieniek@antmicro.com>
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Artur Bieniek 2026-07-08 20:29:49 +02:00 committed by GitHub
parent c7e8075972
commit 671ff628ff
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2 changed files with 4 additions and 3 deletions
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2
test_regress/t/t_force_release.py
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@ -11,7 +11,7 @@ import vltest_bootstrap
test.scenarios('simulator') test.scenarios('simulator')
test.compile(verilator_flags2=["--binary"]) test.compile(verilator_flags2=["--binary", "-Wno-IEEEMAYDEPRECATE"])
test.execute() test.execute()

5
test_regress/t/t_force_release.v
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@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off // verilog_format: off
`define stop // TODO `define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
// verilog_format: on // verilog_format: on
@ -14,11 +14,12 @@
module t; module t;
logic a, b, c, d; logic a, b, c, d;
wire e; wire e;
and and1 (e, a, b, c); and and1 (e, a, b, c);
initial begin initial begin
$monitor("%d d=%b,e=%b", $stime, d, e); $monitor("%d d=%b,e=%b", $stime, d, e);
d = a & b & c; assign d = a & b & c;
a = 1; a = 1;
b = 0; b = 0;
c = 1; c = 1;