From 671ff628ffd6009f81b3505ad9934013b7fbce0b Mon Sep 17 00:00:00 2001 From: Artur Bieniek Date: Wed, 8 Jul 2026 20:29:49 +0200 Subject: [PATCH] Tests: Fix t_force_release to reflect intent (#7906) Signed-off-by: Artur Bieniek --- test_regress/t/t_force_release.py | 2 +- test_regress/t/t_force_release.v | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/test_regress/t/t_force_release.py b/test_regress/t/t_force_release.py index 31b1f0e53..fd98eab68 100755 --- a/test_regress/t/t_force_release.py +++ b/test_regress/t/t_force_release.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--binary"]) +test.compile(verilator_flags2=["--binary", "-Wno-IEEEMAYDEPRECATE"]) test.execute() diff --git a/test_regress/t/t_force_release.v b/test_regress/t/t_force_release.v index fe78ccfcd..34a3e60b7 100644 --- a/test_regress/t/t_force_release.v +++ b/test_regress/t/t_force_release.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 // verilog_format: off -`define stop // TODO +`define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on @@ -14,11 +14,12 @@ module t; logic a, b, c, d; wire e; + and and1 (e, a, b, c); initial begin $monitor("%d d=%b,e=%b", $stime, d, e); - d = a & b & c; + assign d = a & b & c; a = 1; b = 0; c = 1;