Fix timing control in while-break loops (#3733) (#3769)

src/V3Const.cpp

@@ -2801,16 +2801,13 @@ private:
             // least as frequently activating.  So we
             // SENGATE(SENITEM(x)) -> SENITEM(x), then let it collapse with the
             // other SENITEM(x).
-            {
+
-                const VNUser4InUse m_inuse4;
             // Mark x in SENITEM(x)
-                for (AstSenItem* senp = nodep->sensesp(); senp;
+            for (AstSenItem* senp = nodep->sensesp(); senp; senp = VN_AS(senp->nextp(), SenItem)) {
-                     senp = VN_AS(senp->nextp(), SenItem)) {
                 if (senp->varrefp() && senp->varrefp()->varScopep()) {
                     senp->varrefp()->varScopep()->user4(1);
                 }
             }
-            }
 
             // Sort the sensitivity names so "posedge a or b" and "posedge b or a" end up together.
             // Also, remove duplicate assignments, and fold POS&NEGs into ANYEDGEs

test_regress/t/t_while_timing_control.pl

@@ -0,0 +1,30 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+$Self->{main_time_multiplier} = 10e-7 / 10e-9;
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    compile(
+        timing_loop => 1,
+        verilator_flags2 => ['--timing -Wno-ZERODLY'],
+        );
+
+    execute(
+        check_finished => 1,
+        );
+}
+
+ok(1);
+1;

test_regress/t/t_while_timing_control.v

@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t();
+   logic clk = 0;
+   logic out = 1;
+
+   always #5 clk = ~clk;
+
+   initial begin
+      while(1) begin
+         if(out) begin
+            break;
+         end
+         @(negedge clk);
+      end
+
+      $write("*-* All Finished *-*\n");
+      $finish();
+   end
+endmodule