From 62bdd3ab497ac333dc528f080663ed9daed87f8f Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Mon, 21 Nov 2022 12:27:55 +0100
Subject: [PATCH] Fix timing control in while-break loops (#3733) (#3769)

---
 src/V3Const.cpp                          | 13 ++++------
 test_regress/t/t_while_timing_control.pl | 30 ++++++++++++++++++++++++
 test_regress/t/t_while_timing_control.v  | 24 +++++++++++++++++++
 3 files changed, 59 insertions(+), 8 deletions(-)
 create mode 100755 test_regress/t/t_while_timing_control.pl
 create mode 100644 test_regress/t/t_while_timing_control.v

diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 000b31dab..c583563d8 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -2801,14 +2801,11 @@ private:
             // least as frequently activating.  So we
             // SENGATE(SENITEM(x)) -> SENITEM(x), then let it collapse with the
             // other SENITEM(x).
-            {
-                const VNUser4InUse m_inuse4;
-                // Mark x in SENITEM(x)
-                for (AstSenItem* senp = nodep->sensesp(); senp;
-                     senp = VN_AS(senp->nextp(), SenItem)) {
-                    if (senp->varrefp() && senp->varrefp()->varScopep()) {
-                        senp->varrefp()->varScopep()->user4(1);
-                    }
+
+            // Mark x in SENITEM(x)
+            for (AstSenItem* senp = nodep->sensesp(); senp; senp = VN_AS(senp->nextp(), SenItem)) {
+                if (senp->varrefp() && senp->varrefp()->varScopep()) {
+                    senp->varrefp()->varScopep()->user4(1);
                 }
             }
 
diff --git a/test_regress/t/t_while_timing_control.pl b/test_regress/t/t_while_timing_control.pl
new file mode 100755
index 000000000..5f740b172
--- /dev/null
+++ b/test_regress/t/t_while_timing_control.pl
@@ -0,0 +1,30 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+$Self->{main_time_multiplier} = 10e-7 / 10e-9;
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    compile(
+        timing_loop => 1,
+        verilator_flags2 => ['--timing -Wno-ZERODLY'],
+        );
+
+    execute(
+        check_finished => 1,
+        );
+}
+
+ok(1);
+1;
diff --git a/test_regress/t/t_while_timing_control.v b/test_regress/t/t_while_timing_control.v
new file mode 100644
index 000000000..11d54b9c6
--- /dev/null
+++ b/test_regress/t/t_while_timing_control.v
@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t();
+   logic clk = 0;
+   logic out = 1;
+
+   always #5 clk = ~clk;
+
+   initial begin
+      while(1) begin
+         if(out) begin
+            break;
+         end
+         @(negedge clk);
+      end
+
+      $write("*-* All Finished *-*\n");
+      $finish();
+   end
+endmodule