[#73220] add t_trace_jumps_do_while_saif test

test_regress/t/t_trace_jumps_do_while_saif.out

@@ -0,0 +1,34 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "t")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 10)
+(INSTANCE top
+  (NET
+    (clk (T0 10) (T1 0) (TX 0) (TC 1))
+  )
+  (INSTANCE t
+    (NET
+      (clk (T0 10) (T1 0) (TX 0) (TC 1))
+    )
+    (INSTANCE unnamedblk1
+      (NET
+        (results\[0\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[1\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[2\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[3\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[4\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[5\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[6\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[7\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[8\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[9\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[10\] (T0 10) (T1 0) (TX 0) (TC 1))
+        (results\[11\] (T0 10) (T1 0) (TX 0) (TC 1))
+      )
+    )
+  )
+)
+)

test_regress/t/t_trace_jumps_do_while_saif.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test module
+#
+# Copyright 2025 by Antmicro. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_jumps_do_while.v"
+
+test.compile(verilator_flags2=['--trace-saif'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()