[#73220] add t_trace_no_top_name2_saif test

test_regress/t/t_trace_no_top_name2.cpp

@@ -15,6 +15,10 @@
 #include <verilated_vcd_c.h>
 #define TRACE_FILE_NAME "simx.vcd"
 #define TRACE_CLASS VerilatedVcdC
+#elif VM_TRACE_SAIF
+#include <verilated_saif_c.h>
+#define TRACE_FILE_NAME "simx.saif"
+#define TRACE_CLASS VerilatedSaifC
 #endif
 
 #include <memory>

test_regress/t/t_trace_no_top_name2_saif.out

@@ -0,0 +1,32 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "t")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 20)
+(INSTANCE $rootio
+  (NET
+    (clk (T0 10) (T1 10) (TX 0) (TC 20))
+  )
+)
+(INSTANCE t
+  (NET
+    (clk (T0 10) (T1 10) (TX 0) (TC 20))
+    (cyc\[0\] (T0 10) (T1 10) (TX 0) (TC 10))
+    (cyc\[1\] (T0 11) (T1 9) (TX 0) (TC 5))
+    (cyc\[2\] (T0 12) (T1 8) (TX 0) (TC 2))
+    (cyc\[3\] (T0 15) (T1 5) (TX 0) (TC 1))
+  )
+  (INSTANCE sub
+    (NET
+      (a\[2\] (T0 0) (T1 20) (TX 0) (TC 1))
+      (a\[3\] (T0 0) (T1 20) (TX 0) (TC 1))
+      (a\[4\] (T0 0) (T1 20) (TX 0) (TC 1))
+      (a\[5\] (T0 0) (T1 20) (TX 0) (TC 1))
+      (a\[7\] (T0 0) (T1 20) (TX 0) (TC 1))
+      (a\[10\] (T0 0) (T1 20) (TX 0) (TC 1))
+    )
+  )
+)
+)

test_regress/t/t_trace_no_top_name2_saif.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.pli_filename = "t/t_trace_no_top_name2.cpp"
+test.top_filename = "t/t_trace_no_top_name2.v"
+
+test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()