Dfg: Fix incorrect folding of associative expressions with shared terms

Fixes #3679

src/V3DfgPeephole.cpp

@@ -248,10 +248,7 @@ class V3DfgPeephole final : public DfgVisitor {
                         foldOp<Vertex>(constp->num(), lConstp->num(), rlConstp->num());
 
                         // Replace vertex
-                        if VL_CONSTEXPR_CXX17 (!std::is_same<DfgConcat, Vertex>::value) {
+                        if (!rVtxp->hasMultipleSinks()) {
-                            rVtxp->lhsp(constp);
-                            vtxp->replaceWith(rVtxp);
-                        } else if (!rVtxp->hasMultipleSinks()) {
                             rVtxp->lhsp(constp);
                             rVtxp->dtypep(vtxp->dtypep());
                             vtxp->replaceWith(rVtxp);
@@ -279,10 +276,7 @@ class V3DfgPeephole final : public DfgVisitor {
                         foldOp<Vertex>(constp->num(), lrConstp->num(), rConstp->num());
 
                         // Replace vertex
-                        if VL_CONSTEXPR_CXX17 (!std::is_same<DfgConcat, Vertex>::value) {
+                        if (!lVtxp->hasMultipleSinks()) {
-                            lVtxp->rhsp(constp);
-                            vtxp->replaceWith(lVtxp);
-                        } else if (!lVtxp->hasMultipleSinks()) {
                             lVtxp->rhsp(constp);
                             lVtxp->dtypep(vtxp->dtypep());
                             vtxp->replaceWith(lVtxp);

test_regress/t/t_dfg_3679.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_dfg_3679.v

@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc=1;
+
+   reg [31:0] dly0;
+
+   // DFG can fold this into 'dly3 = dly1 = dly0 + 1' and 'dly2 = dly0 + 2',
+   // but the 'dly0 + 1' term having multiple sinks needs to considered.
+   wire [31:0] dly1 = dly0 + 32'h1;
+   wire [31:0] dly2 = dly1 + 32'h1;
+   wire [31:0] dly3 = dly0 + 32'h1;
+
+   always @ (posedge clk) begin
+      $display("[%0t] dly0=%h dly1=%h dly2=%h dly3=%h", $time, dly0, dly1, dly2, dly3);
+      cyc <= cyc + 1;
+      if (cyc == 1) begin
+         dly0 <= 32'h55;
+      end
+      else if (cyc == 3) begin
+         if (dly1 !== 32'h56) $stop;
+         if (dly2 !== 32'h57) $stop;
+         if (dly3 !== 32'h56) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule