Add SystemVerilog 1800-2009 keywords
This commit is contained in:
Wilson Snyder
parent
4360fe492e
commit
58efab5cdf
3
Changes
3
Changes
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@ -5,6 +5,9 @@ indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.800***
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** SystemVerilog 1800-2009 is now the default language.
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Thus "global" etc are now keywords. See the --language option.
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** Support SystemVerilog types "byte", "chandle", "int", "longint",
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"shortint", "time", "var" and "void" in variables and functions.
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@ -42,6 +42,7 @@ public:
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L1364_2001,
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L1364_2005,
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L1800_2005,
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L1800_2009,
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// ***Add new elements below also***
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MAX
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};
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@ -52,11 +53,12 @@ public:
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"1364-1995",
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"1364-2001",
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"1364-2005",
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"1800-2005"
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"1800-2005",
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"1800-2009"
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};
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return names[m_e];
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};
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static V3LangCode mostRecent() { return V3LangCode(L1800_2005); }
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static V3LangCode mostRecent() { return V3LangCode(L1800_2009); }
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bool legal() const { return m_e != ERROR; }
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//
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enum en m_e;
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@ -32,7 +32,7 @@
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extern void yyerror(const char*);
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extern void yyerrorf(const char* format, ...);
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#define STATE_VERILOG_RECENT S05 // State name for most recent Verilog Version
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#define STATE_VERILOG_RECENT S09 // State name for most recent Verilog Version
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#define PARSEP V3ParseImp::parsep()
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#define SYMP PARSEP->symp()
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@ -131,7 +131,7 @@ void yyerrorf(const char* format, ...) {
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%a 15000
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%o 25000
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%s V95 V01 V05 S05
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%s V95 V01 V05 S05 S09
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%s STRING ATTRMODE TABLE
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%s PSL VLT
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%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
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@ -166,7 +166,7 @@ escid \\[^ \t\f\r\n]+
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/************************************************************************/
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/* Verilog 1995 */
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<V95,V01,V05,S05,PSL>{
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<V95,V01,V05,S05,S09,PSL>{
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{ws} { } /* otherwise ignore white-space */
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{crnl} { NEXTLINE(); } /* Count line numbers */
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/* Extensions to Verilog set, some specified by PSL */
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@ -327,7 +327,7 @@ escid \\[^ \t\f\r\n]+
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}
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/* Verilog 2001 */
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<V01,V05,S05,PSL>{
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<V01,V05,S05,S09,PSL>{
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/* System Tasks */
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"$signed" { FL; return yD_SIGNED; }
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"$unsigned" { FL; return yD_UNSIGNED; }
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@ -358,13 +358,13 @@ escid \\[^ \t\f\r\n]+
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}
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/* Verilog 2005 */
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<V05,S05,PSL>{
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<V05,S05,S09,PSL>{
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/* Keywords */
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"uwire" { FL; return yWIRE; }
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}
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/* System Verilog 2005 */
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<S05,PSL>{
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<S05,S09,PSL>{
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/* System Tasks */
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"$bits" { FL; return yD_BITS; }
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"$clog2" { FL; return yD_CLOG2; }
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@ -472,8 +472,8 @@ escid \\[^ \t\f\r\n]+
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"with" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
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}
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/* SystemVerilog ONLY not PSL; different rules for PSL as specified below */
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<S05>{
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/* SystemVerilog 2005 ONLY not PSL; different rules for PSL as specified below */
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<S05,S09>{
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/* Keywords */
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"assert" { FL; return yASSERT; }
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"cover" { FL; return yCOVER; }
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@ -487,8 +487,37 @@ escid \\[^ \t\f\r\n]+
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"within" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext); }
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}
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/* SystemVerilog 2009 */
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<S09,PSL>{
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/* Keywords */
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/* Generic unsupported warnings */
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"accept_on" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"checker" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"endchecker" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"eventually" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"global" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"implies" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"let" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"nexttime" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"reject_on" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"restrict" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"s_always" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"s_eventually" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"s_nexttime" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"s_until" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"s_until_with" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"strong" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"sync_accept_on" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"sync_reject_on" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"unique0" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"until" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"until_with" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"untyped" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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"weak" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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}
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/* Default PLI rule */
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<V95,V01,V05,S05,PSL>{
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<V95,V01,V05,S05,S09,PSL>{
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"$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext,yyleng);
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yylval.strp = PARSEP->newString(AstNode::encodeName(str));
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// Lookup unencoded name including the $, to avoid hitting normal signals
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@ -502,7 +531,7 @@ escid \\[^ \t\f\r\n]+
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/* PSL */
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/*Entry into PSL; mode change */
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<V95,V01,V05,S05>{
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<V95,V01,V05,S05,S09>{
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"psl" { yy_push_state(PSL); FL; return yPSL; }
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}
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@ -537,6 +566,9 @@ escid \\[^ \t\f\r\n]+
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/*"W" { FL; return yUNTIL; } */
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/*"X" { FL; return yNEXT; } */
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/*"X!" { FL; return yNEXTB; } */
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/*"restrict" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } S09 instead */
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/*"strong" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } S09 instead */
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/*"until" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } S09 instead */
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"%for" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"%if" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"abort" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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@ -570,14 +602,11 @@ escid \\[^ \t\f\r\n]+
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"next_event_e!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"prev" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"property" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"restrict" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"restrict_guarantee" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools
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"rose" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"sequence" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"stable" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"strong" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools
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"union" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"until" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"until!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"until!_" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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"until_" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); }
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@ -591,7 +620,7 @@ escid \\[^ \t\f\r\n]+
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/* Meta comments */
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/* Converted from //{cmt}verilator ...{cmt} by preprocessor */
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<V95,V01,V05,S05,PSL>{
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<V95,V01,V05,S05,S09,PSL>{
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"/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */
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"/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; }
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"/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; }
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@ -622,11 +651,11 @@ escid \\[^ \t\f\r\n]+
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/************************************************************************/
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/* Single character operator thingies */
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<V95,V01,V05,S05>{
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<V95,V01,V05,S05,S09>{
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"{" { FL; return yytext[0]; }
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"}" { FL; return yytext[0]; }
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}
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<V95,V01,V05,S05,PSL>{
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<V95,V01,V05,S05,S09,PSL>{
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"!" { FL; return yytext[0]; }
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"#" { FL; return yytext[0]; }
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"$" { FL; return yytext[0]; }
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@ -658,7 +687,7 @@ escid \\[^ \t\f\r\n]+
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/* Operators and multi-character symbols */
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/* Verilog 1995 Operators */
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<V95,V01,V05,S05,PSL>{
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<V95,V01,V05,S05,S09,PSL>{
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"&&" { FL; return yP_ANDAND; }
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"||" { FL; return yP_OROR; }
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"<=" { FL; return yP_LTE; }
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@ -680,7 +709,7 @@ escid \\[^ \t\f\r\n]+
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}
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/* Verilog 2001 Operators */
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<V01,V05,S05,PSL>{
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<V01,V05,S05,S09,PSL>{
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"<<<" { FL; return yP_SLEFT; }
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">>>" { FL; return yP_SSRIGHT; }
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"**" { FL; return yP_POW; }
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@ -690,7 +719,7 @@ escid \\[^ \t\f\r\n]+
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}
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/* SystemVerilog Operators */
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<S05>{
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<S05,S09>{
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"'" { FL; return yP_TICK; }
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"'{" { FL; return yP_TICKBRA; }
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"==?" { FL; return yP_WILDEQUAL; }
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@ -739,7 +768,7 @@ escid \\[^ \t\f\r\n]+
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}
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/* Identifiers and numbers */
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<V95,V01,V05,S05,PSL,VLT>{
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<V95,V01,V05,S05,S09,PSL,VLT>{
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{escid} { FL; yylval.strp = PARSEP->newString
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(AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash
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return yaID__LEX;
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@ -812,7 +841,7 @@ escid \\[^ \t\f\r\n]+
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/************************************************************************/
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/* Attributes */
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<V95,V01,V05,S05>{
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<V95,V01,V05,S05,S09>{
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"(*"/{ws}*[^)] { yymore(); yy_push_state(ATTRMODE); } // Doesn't match (*)
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}
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@ -829,7 +858,7 @@ escid \\[^ \t\f\r\n]+
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/* Preprocessor */
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/* Common for all SYSC header states */
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/* OPTIMIZE: we return one per line, make it one for the entire block */
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<V95,V01,V05,S05,PSL,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
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<V95,V01,V05,S05,S09,PSL,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
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"`accelerate" { } // Verilog-XL compatibility
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"`autoexpand_vectornets" { } // Verilog-XL compatibility
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"`celldefine" { PARSEP->inCellDefine(true); }
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@ -868,6 +897,7 @@ escid \\[^ \t\f\r\n]+
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"`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); PARSEP->pushBeginKeywords(YY_START); }
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"`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); PARSEP->pushBeginKeywords(YY_START); }
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"`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); }
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"`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); }
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"`end_keywords" { yy_pop_state(); if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
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/* Verilator */
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@ -898,7 +928,7 @@ escid \\[^ \t\f\r\n]+
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/************************************************************************/
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/* Default rules - leave last */
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<V95,V01,V05,S05,PSL,VLT>{
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<V95,V01,V05,S05,S09,PSL,VLT>{
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"`"[a-zA-Z_0-9]+ { FL; yyerrorf("Define or directive not defined: %s",yytext); }
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"//"[^\n]* { } /* throw away single line comments */
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. { FL; return yytext[0]; } /* return single char ops. */
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@ -5,35 +5,35 @@
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module t;
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reg [2:0] value;
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reg [31:0] global;
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reg [31:0] rglobal;
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reg [31:0] vec [1:0];
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reg [31:0] n;
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initial begin
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global = 1;
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rglobal = 1;
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value = 2;
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if (add(value) != 3'd3) $stop;
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if (global != 2) $stop;
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if (rglobal != 2) $stop;
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if (add(add(3'd1)) != 3'd3) $stop;
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if (global != 4) $stop;
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if (rglobal != 4) $stop;
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if (munge4(4'b0010) != 4'b1011) $stop;
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if (toint(2) != 3) $stop;
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if (global != 5) $stop;
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if (rglobal != 5) $stop;
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setit;
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incr(global,global,32'h10);
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if (global != 32'h17) $stop;
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incr(rglobal,rglobal,32'h10);
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if (rglobal != 32'h17) $stop;
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nop(32'h11);
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empty;
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empty();
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global = 32'h00000001;
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flipupperbit(global,4'd4);
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flipupperbit(global,4'd12);
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if (global !== 32'h10100001) $stop;
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rglobal = 32'h00000001;
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flipupperbit(rglobal,4'd4);
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flipupperbit(rglobal,4'd12);
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if (rglobal !== 32'h10100001) $stop;
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if (nil_func(32'h12,32'h12) != 32'h24) $stop;
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nil_task(32'h012,32'h112,global);
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if (global !== 32'h124) $stop;
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nil_task(32'h012,32'h112,rglobal);
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if (rglobal !== 32'h124) $stop;
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vec[0] = 32'h333;
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vec[1] = 32'habc;
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@ -58,7 +58,7 @@ module t;
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begin : named
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reg [31:0] flocal;
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flocal = 1;
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global = global + flocal;
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rglobal = rglobal + flocal;
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end : named // SystemVerilog end labels
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end
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endfunction
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@ -77,8 +77,8 @@ module t;
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task setit;
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reg [31:0] temp;
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begin
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temp = global + 32'h1;
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global = temp + 32'h1;
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temp = rglobal + 32'h1;
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rglobal = temp + 32'h1;
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end
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endtask
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@ -65,11 +65,11 @@ endmodule
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module global_mod;
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`INLINE_MODULE
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parameter INITVAL = 0;
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integer global;
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integer globali;
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initial global = INITVAL;
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initial globali = INITVAL;
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function [31:0] getName; input fake; getName = "gmod"; endfunction
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function [31:0] getGlob; input fake; getGlob = global; endfunction
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function [31:0] getGlob; input fake; getGlob = globali; endfunction
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endmodule
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module ma ();
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@ -17,7 +17,10 @@ module t (/*AUTOARG*/
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`end_keywords
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`begin_keywords "1364-2005"
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integer final; initial final = 1;
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`begin_keywords "1800-2005"
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`end_keywords
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`begin_keywords "1800-2005"
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integer global; initial global = 1;
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||||
`begin_keywords "1800-2009"
|
||||
final begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
end
|
||||
|
|
|
|||
|
|
@ -30,8 +30,8 @@ module t (/*AUTOARG*/
|
|||
cyc <= cyc + 1;
|
||||
//$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
|
||||
if (cyc==2) begin
|
||||
if (global_cell.global != 32'hf00d) $stop;
|
||||
if (global_cell2.global != 32'hf22d) $stop;
|
||||
if (global_cell.globali != 32'hf00d) $stop;
|
||||
if (global_cell2.globali != 32'hf22d) $stop;
|
||||
if (outb0c0 != 32'h00) $stop;
|
||||
if (outb0c1 != 32'h01) $stop;
|
||||
if (outb1c0 != 32'h10) $stop;
|
||||
|
|
@ -91,8 +91,8 @@ endmodule
|
|||
module global_mod;
|
||||
`INLINE_MODULE
|
||||
parameter INITVAL = 0;
|
||||
integer global;
|
||||
initial global = INITVAL;
|
||||
integer globali;
|
||||
initial globali = INITVAL;
|
||||
endmodule
|
||||
|
||||
module ma (
|
||||
|
|
@ -154,8 +154,8 @@ module mc (output reg [31:0] out);
|
|||
always @ (posedge t.clk) begin
|
||||
//$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc);
|
||||
if (reach_up_cyc==2) begin
|
||||
if (global_cell.global != 32'hf00d) $stop;
|
||||
if (global_cell2.global != 32'hf33d) $stop;
|
||||
if (global_cell.globali != 32'hf00d) $stop;
|
||||
if (global_cell2.globali != 32'hf33d) $stop;
|
||||
end
|
||||
if (reach_up_cyc==4) begin
|
||||
out[15:12] <= {P2[3:0]+P3[3:0]+4'd1};
|
||||
|
|
|
|||
Loading…
Reference in New Issue