diff --git a/Changes b/Changes index f3ecce13a..404f0f62c 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,9 @@ indicates the contributor was also the author of the fix; Thanks! * Verilator 3.800*** +** SystemVerilog 1800-2009 is now the default language. + Thus "global" etc are now keywords. See the --language option. + ** Support SystemVerilog types "byte", "chandle", "int", "longint", "shortint", "time", "var" and "void" in variables and functions. diff --git a/src/V3Options.h b/src/V3Options.h index 4b9376d31..c4df7496a 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -42,6 +42,7 @@ public: L1364_2001, L1364_2005, L1800_2005, + L1800_2009, // ***Add new elements below also*** MAX }; @@ -52,11 +53,12 @@ public: "1364-1995", "1364-2001", "1364-2005", - "1800-2005" + "1800-2005", + "1800-2009" }; return names[m_e]; }; - static V3LangCode mostRecent() { return V3LangCode(L1800_2005); } + static V3LangCode mostRecent() { return V3LangCode(L1800_2009); } bool legal() const { return m_e != ERROR; } // enum en m_e; diff --git a/src/verilog.l b/src/verilog.l index 3dcca8d1c..dc07e486f 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -32,7 +32,7 @@ extern void yyerror(const char*); extern void yyerrorf(const char* format, ...); -#define STATE_VERILOG_RECENT S05 // State name for most recent Verilog Version +#define STATE_VERILOG_RECENT S09 // State name for most recent Verilog Version #define PARSEP V3ParseImp::parsep() #define SYMP PARSEP->symp() @@ -131,7 +131,7 @@ void yyerrorf(const char* format, ...) { %a 15000 %o 25000 -%s V95 V01 V05 S05 +%s V95 V01 V05 S05 S09 %s STRING ATTRMODE TABLE %s PSL VLT %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR @@ -166,7 +166,7 @@ escid \\[^ \t\f\r\n]+ /************************************************************************/ /* Verilog 1995 */ -{ +{ {ws} { } /* otherwise ignore white-space */ {crnl} { NEXTLINE(); } /* Count line numbers */ /* Extensions to Verilog set, some specified by PSL */ @@ -327,7 +327,7 @@ escid \\[^ \t\f\r\n]+ } /* Verilog 2001 */ -{ +{ /* System Tasks */ "$signed" { FL; return yD_SIGNED; } "$unsigned" { FL; return yD_UNSIGNED; } @@ -358,13 +358,13 @@ escid \\[^ \t\f\r\n]+ } /* Verilog 2005 */ -{ +{ /* Keywords */ "uwire" { FL; return yWIRE; } } /* System Verilog 2005 */ -{ +{ /* System Tasks */ "$bits" { FL; return yD_BITS; } "$clog2" { FL; return yD_CLOG2; } @@ -472,8 +472,8 @@ escid \\[^ \t\f\r\n]+ "with" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } } - /* SystemVerilog ONLY not PSL; different rules for PSL as specified below */ -{ + /* SystemVerilog 2005 ONLY not PSL; different rules for PSL as specified below */ +{ /* Keywords */ "assert" { FL; return yASSERT; } "cover" { FL; return yCOVER; } @@ -487,8 +487,37 @@ escid \\[^ \t\f\r\n]+ "within" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext); } } + /* SystemVerilog 2009 */ +{ + /* Keywords */ + /* Generic unsupported warnings */ + "accept_on" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "checker" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "endchecker" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "eventually" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "global" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "implies" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "let" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "nexttime" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "reject_on" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "restrict" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "s_always" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "s_eventually" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "s_nexttime" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "s_until" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "s_until_with" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "strong" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "sync_accept_on" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "sync_reject_on" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "unique0" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "until" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "until_with" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "untyped" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } + "weak" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } +} + /* Default PLI rule */ -{ +{ "$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext,yyleng); yylval.strp = PARSEP->newString(AstNode::encodeName(str)); // Lookup unencoded name including the $, to avoid hitting normal signals @@ -502,7 +531,7 @@ escid \\[^ \t\f\r\n]+ /* PSL */ /*Entry into PSL; mode change */ -{ +{ "psl" { yy_push_state(PSL); FL; return yPSL; } } @@ -537,6 +566,9 @@ escid \\[^ \t\f\r\n]+ /*"W" { FL; return yUNTIL; } */ /*"X" { FL; return yNEXT; } */ /*"X!" { FL; return yNEXTB; } */ + /*"restrict" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } S09 instead */ + /*"strong" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } S09 instead */ + /*"until" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } S09 instead */ "%for" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } "%if" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } "abort" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } @@ -570,14 +602,11 @@ escid \\[^ \t\f\r\n]+ "next_event_e!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } "prev" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } "property" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } - "restrict" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } "restrict_guarantee" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools "rose" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } "sequence" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } "stable" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } - "strong" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools "union" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } - "until" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } "until!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } "until!_" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } "until_" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } @@ -591,7 +620,7 @@ escid \\[^ \t\f\r\n]+ /* Meta comments */ /* Converted from //{cmt}verilator ...{cmt} by preprocessor */ -{ +{ "/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */ "/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; } "/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; } @@ -622,11 +651,11 @@ escid \\[^ \t\f\r\n]+ /************************************************************************/ /* Single character operator thingies */ -{ +{ "{" { FL; return yytext[0]; } "}" { FL; return yytext[0]; } } -{ +{ "!" { FL; return yytext[0]; } "#" { FL; return yytext[0]; } "$" { FL; return yytext[0]; } @@ -658,7 +687,7 @@ escid \\[^ \t\f\r\n]+ /* Operators and multi-character symbols */ /* Verilog 1995 Operators */ -{ +{ "&&" { FL; return yP_ANDAND; } "||" { FL; return yP_OROR; } "<=" { FL; return yP_LTE; } @@ -680,7 +709,7 @@ escid \\[^ \t\f\r\n]+ } /* Verilog 2001 Operators */ -{ +{ "<<<" { FL; return yP_SLEFT; } ">>>" { FL; return yP_SSRIGHT; } "**" { FL; return yP_POW; } @@ -690,7 +719,7 @@ escid \\[^ \t\f\r\n]+ } /* SystemVerilog Operators */ -{ +{ "'" { FL; return yP_TICK; } "'{" { FL; return yP_TICKBRA; } "==?" { FL; return yP_WILDEQUAL; } @@ -739,7 +768,7 @@ escid \\[^ \t\f\r\n]+ } /* Identifiers and numbers */ -{ +{ {escid} { FL; yylval.strp = PARSEP->newString (AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash return yaID__LEX; @@ -812,7 +841,7 @@ escid \\[^ \t\f\r\n]+ /************************************************************************/ /* Attributes */ -{ +{ "(*"/{ws}*[^)] { yymore(); yy_push_state(ATTRMODE); } // Doesn't match (*) } @@ -829,7 +858,7 @@ escid \\[^ \t\f\r\n]+ /* Preprocessor */ /* Common for all SYSC header states */ /* OPTIMIZE: we return one per line, make it one for the entire block */ -{ +{ "`accelerate" { } // Verilog-XL compatibility "`autoexpand_vectornets" { } // Verilog-XL compatibility "`celldefine" { PARSEP->inCellDefine(true); } @@ -868,6 +897,7 @@ escid \\[^ \t\f\r\n]+ "`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); PARSEP->pushBeginKeywords(YY_START); } "`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); PARSEP->pushBeginKeywords(YY_START); } "`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); } + "`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); } "`end_keywords" { yy_pop_state(); if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); } /* Verilator */ @@ -898,7 +928,7 @@ escid \\[^ \t\f\r\n]+ /************************************************************************/ /* Default rules - leave last */ -{ +{ "`"[a-zA-Z_0-9]+ { FL; yyerrorf("Define or directive not defined: %s",yytext); } "//"[^\n]* { } /* throw away single line comments */ . { FL; return yytext[0]; } /* return single char ops. */ diff --git a/test_regress/t/t_func.v b/test_regress/t/t_func.v index 33e926137..ae85b951a 100644 --- a/test_regress/t/t_func.v +++ b/test_regress/t/t_func.v @@ -5,35 +5,35 @@ module t; reg [2:0] value; - reg [31:0] global; + reg [31:0] rglobal; reg [31:0] vec [1:0]; reg [31:0] n; initial begin - global = 1; + rglobal = 1; value = 2; if (add(value) != 3'd3) $stop; - if (global != 2) $stop; + if (rglobal != 2) $stop; if (add(add(3'd1)) != 3'd3) $stop; - if (global != 4) $stop; + if (rglobal != 4) $stop; if (munge4(4'b0010) != 4'b1011) $stop; if (toint(2) != 3) $stop; - if (global != 5) $stop; + if (rglobal != 5) $stop; setit; - incr(global,global,32'h10); - if (global != 32'h17) $stop; + incr(rglobal,rglobal,32'h10); + if (rglobal != 32'h17) $stop; nop(32'h11); empty; empty(); - global = 32'h00000001; - flipupperbit(global,4'd4); - flipupperbit(global,4'd12); - if (global !== 32'h10100001) $stop; + rglobal = 32'h00000001; + flipupperbit(rglobal,4'd4); + flipupperbit(rglobal,4'd12); + if (rglobal !== 32'h10100001) $stop; if (nil_func(32'h12,32'h12) != 32'h24) $stop; - nil_task(32'h012,32'h112,global); - if (global !== 32'h124) $stop; + nil_task(32'h012,32'h112,rglobal); + if (rglobal !== 32'h124) $stop; vec[0] = 32'h333; vec[1] = 32'habc; @@ -58,7 +58,7 @@ module t; begin : named reg [31:0] flocal; flocal = 1; - global = global + flocal; + rglobal = rglobal + flocal; end : named // SystemVerilog end labels end endfunction @@ -77,8 +77,8 @@ module t; task setit; reg [31:0] temp; begin - temp = global + 32'h1; - global = temp + 32'h1; + temp = rglobal + 32'h1; + rglobal = temp + 32'h1; end endtask diff --git a/test_regress/t/t_func_dotted.v b/test_regress/t/t_func_dotted.v index db26d460e..df17433a9 100644 --- a/test_regress/t/t_func_dotted.v +++ b/test_regress/t/t_func_dotted.v @@ -65,11 +65,11 @@ endmodule module global_mod; `INLINE_MODULE parameter INITVAL = 0; - integer global; + integer globali; - initial global = INITVAL; + initial globali = INITVAL; function [31:0] getName; input fake; getName = "gmod"; endfunction - function [31:0] getGlob; input fake; getGlob = global; endfunction + function [31:0] getGlob; input fake; getGlob = globali; endfunction endmodule module ma (); diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v index b50f36655..412767d61 100644 --- a/test_regress/t/t_preproc_kwd.v +++ b/test_regress/t/t_preproc_kwd.v @@ -17,7 +17,10 @@ module t (/*AUTOARG*/ `end_keywords `begin_keywords "1364-2005" integer final; initial final = 1; - `begin_keywords "1800-2005" +`end_keywords +`begin_keywords "1800-2005" + integer global; initial global = 1; + `begin_keywords "1800-2009" final begin $write("*-* All Finished *-*\n"); end diff --git a/test_regress/t/t_var_dotted.v b/test_regress/t/t_var_dotted.v index b9119fce2..06b3dd255 100644 --- a/test_regress/t/t_var_dotted.v +++ b/test_regress/t/t_var_dotted.v @@ -30,8 +30,8 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; //$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1); if (cyc==2) begin - if (global_cell.global != 32'hf00d) $stop; - if (global_cell2.global != 32'hf22d) $stop; + if (global_cell.globali != 32'hf00d) $stop; + if (global_cell2.globali != 32'hf22d) $stop; if (outb0c0 != 32'h00) $stop; if (outb0c1 != 32'h01) $stop; if (outb1c0 != 32'h10) $stop; @@ -91,8 +91,8 @@ endmodule module global_mod; `INLINE_MODULE parameter INITVAL = 0; - integer global; - initial global = INITVAL; + integer globali; + initial globali = INITVAL; endmodule module ma ( @@ -154,8 +154,8 @@ module mc (output reg [31:0] out); always @ (posedge t.clk) begin //$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc); if (reach_up_cyc==2) begin - if (global_cell.global != 32'hf00d) $stop; - if (global_cell2.global != 32'hf33d) $stop; + if (global_cell.globali != 32'hf00d) $stop; + if (global_cell2.globali != 32'hf33d) $stop; end if (reach_up_cyc==4) begin out[15:12] <= {P2[3:0]+P3[3:0]+4'd1};