From 506c36beed6c734ff4d6f9f7af529aaa2185a4d0 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 25 Apr 2008 11:48:18 +0000
Subject: [PATCH] Fix ranges on gate primitive instantiations

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1038 77ca24e4-aefa-0310-84f0-b9a241c72d87
---
 Changes                       |  2 ++
 bin/verilator                 |  2 +-
 src/verilog.y                 | 16 ++++++++--------
 test_regress/t/t_gate_basic.v |  7 ++++++-
 4 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/Changes b/Changes
index 3d98cb9da..710202a18 100644
--- a/Changes
+++ b/Changes
@@ -25,6 +25,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix internal error when params get non-constants. [Johan Wouters]
 
+**** Fix ranges on gate primitive instantiations. [Stefan Thiede]
+
 * Verilator 3.661 2008/04/04
 
 ***  The --enable-defenv configure option added in 3.660 is now the default.
diff --git a/bin/verilator b/bin/verilator
index c63244801..a1347ba05 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -1550,7 +1550,7 @@ them with a $write with the appropriate format specifier.
 
 =item $finish, $stop
 
-The rarely used optional exit code to finish and stop is ignored.
+The rarely used optional parameter to $finish and $stop is ignored.
 
 =item $fopen, $fclose, $fdisplay, $fwrite
 
diff --git a/src/verilog.y b/src/verilog.y
index 583eb0740..4644e6006 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1161,21 +1161,21 @@ gateXnorList:	gateXnor 				{ $$ = $1; }
 	|	gateXnor ',' gateXnor			{ $$ = $1->addNext($3); }
 	;
 
-gateBuf: 	gateIdE '(' varRefDotBit ',' expr ')'		{ $$ = new AstAssignW ($2,$3,$5); $$->allowImplicit(true); }
+gateBuf: 	gateIdE instRangeE '(' varRefDotBit ',' expr ')'		{ $$ = new AstAssignW ($3,$4,$6); $$->allowImplicit(true); }
 	;
-gateNot:	gateIdE '(' varRefDotBit ',' expr ')'		{ $$ = new AstAssignW ($2,$3,new AstNot($4,$5)); $$->allowImplicit(true); }
+gateNot:	gateIdE instRangeE '(' varRefDotBit ',' expr ')'		{ $$ = new AstAssignW ($3,$4,new AstNot($5,$6)); $$->allowImplicit(true); }
 	;
-gateAnd:	gateIdE '(' varRefDotBit ',' gateAndPinList ')'	{ $$ = new AstAssignW ($2,$3,$5); $$->allowImplicit(true); }
+gateAnd:	gateIdE instRangeE '(' varRefDotBit ',' gateAndPinList ')'	{ $$ = new AstAssignW ($3,$4,$6); $$->allowImplicit(true); }
 	;
-gateNand:	gateIdE '(' varRefDotBit ',' gateAndPinList ')'	{ $$ = new AstAssignW ($2,$3,new AstNot($4,$5)); $$->allowImplicit(true); }
+gateNand:	gateIdE instRangeE '(' varRefDotBit ',' gateAndPinList ')'	{ $$ = new AstAssignW ($3,$4,new AstNot($5,$6)); $$->allowImplicit(true); }
 	;
-gateOr:		gateIdE '(' varRefDotBit ',' gateOrPinList ')'	{ $$ = new AstAssignW ($2,$3,$5); $$->allowImplicit(true); }
+gateOr:		gateIdE instRangeE '(' varRefDotBit ',' gateOrPinList ')'	{ $$ = new AstAssignW ($3,$4,$6); $$->allowImplicit(true); }
 	;
-gateNor:	gateIdE '(' varRefDotBit ',' gateOrPinList ')'	{ $$ = new AstAssignW ($2,$3,new AstNot($4,$5)); $$->allowImplicit(true); }
+gateNor:	gateIdE instRangeE '(' varRefDotBit ',' gateOrPinList ')'	{ $$ = new AstAssignW ($3,$4,new AstNot($5,$6)); $$->allowImplicit(true); }
 	;
-gateXor:	gateIdE '(' varRefDotBit ',' gateXorPinList ')'	{ $$ = new AstAssignW ($2,$3,$5); $$->allowImplicit(true); }
+gateXor:	gateIdE instRangeE '(' varRefDotBit ',' gateXorPinList ')'	{ $$ = new AstAssignW ($3,$4,$6); $$->allowImplicit(true); }
 	;
-gateXnor:	gateIdE '(' varRefDotBit ',' gateXorPinList ')'	{ $$ = new AstAssignW ($2,$3,new AstNot($4,$5)); $$->allowImplicit(true); }
+gateXnor:	gateIdE instRangeE '(' varRefDotBit ',' gateXorPinList ')'	{ $$ = new AstAssignW ($3,$4,new AstNot($5,$6)); $$->allowImplicit(true); }
 	;
 
 gateIdE:	/*empty*/				{}
diff --git a/test_regress/t/t_gate_basic.v b/test_regress/t/t_gate_basic.v
index f8a3a4fbd..77ee9b7d8 100644
--- a/test_regress/t/t_gate_basic.v
+++ b/test_regress/t/t_gate_basic.v
@@ -21,13 +21,17 @@ module t (/*AUTOARG*/
    // verilator lint_off IMPLICIT
    not   NT0 (nt0, a[0]);
    and   #1       AN0 (an0, a[0], b[0]);
-   nand  #(2,3,4) ND0 (nd0, a[0], b[0], b[1]);
+   nand  #(2,3)   ND0 (nd0, a[0], b[0], b[1]);
    or    OR0 (or0, a[0], b[0]);
    nor   NR0 (nr0, a[0], b[0], b[2]);
    xor       (xo0, a[0], b[0]);
    xnor      (xn0, a[0], b[0], b[2]);
    // verilator lint_on IMPLICIT
 
+   parameter BITS=32;
+   wire [BITS-1:0] ba;
+   buf BARRAY [BITS-1:0] (ba, a);
+
 `ifdef verilator
    specify
       specparam CDS_LIBNAME  = "foobar";
@@ -65,6 +69,7 @@ module t (/*AUTOARG*/
 	    if (nr0 !== 1'b1) $stop;
 	    if (xo0 !== 1'b0) $stop;
 	    if (xn0 !== 1'b1) $stop;
+	    if (ba != 32'h18f6b034) $stop;
 	 end
 	 if (cyc==3) begin
 	    if (bf[0] !== 1'b1) $stop;