Commentary: Changes update

Changes

@@ -54,6 +54,7 @@ Verilator 5.047 devel
 * Support sequence `first_match` operator (#7392). [Yilou Wang]
 * Support nonconsecutive repetition [=N] in sequence expressions (#7397). [Yilou Wang]
 * Support per-process RNG for process::srandom() and object seeding (#7408) (#7415) (#7408). [Yilou Wang]
+* Support 2**n expressions in constraint randomization (#7422). [Yilou Wang]
 * Add VPI callback support to --main (#7145).
 * Add V3LiftExpr pass to lower impure expressions and calls (#7141) (#7164). [Geza Lore, Testorrent USA, Inc.]
 * Add --func-recursion-depth CLI option (#7175) (#7179).
@@ -66,6 +67,7 @@ Verilator 5.047 devel
 * Change array tracing to dump left index to right index (#7205). [Geza Lore, Testorrent USA, Inc.]
 * Change `--converge-limit` default to 10000 (#7209).
 * Remove DFG extract optimization pass (#7394). [Geza Lore, Testorrent USA, Inc.]
+* Optimize trace code for faster compiles on repeated types (#6707) (#6832). [Todd Strader]
 * Optimize size of trace declaration object code (#7150). [Szymon Gizler, Antmicro Ltd.]
 * Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.]
 * Optimize conditional merging across some impure statements (#7159). [Geza Lore, Testorrent USA, Inc.]
@@ -77,6 +79,7 @@ Verilator 5.047 devel
 * Optimize more patterns in DfgPeephole (#7332). [Geza Lore, Testorrent USA, Inc.]
 * Optimize read references in DFG (#7354). [Geza Lore, Testorrent USA, Inc.]
 * Optimize DFG only once, after scoping (#7362). [Geza Lore, Testorrent USA, Inc.]
+* Optimize more DFG peephole patterns (#7423). [Geza Lore, Testorrent USA, Inc.]
 * Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier]
 * Fix virtual interface member trigger convergence (#5116) (#7323). [Yilou Wang]
 * Fix shift width mismatch in constraint solver SMT emission (#5420) (#7265). [Yilou Wang]
@@ -139,6 +142,7 @@ Verilator 5.047 devel
 * Fix virtual interface function calls binding to wrong instance (#7363). [Yilou Wang]
 * Fix false ASSIGNIN on interface input port connections (#7365). [Yilou Wang]
 * Fix string `inside` queue (#7373).
+* Fix subclass with rand_mode(0) getting randomized (#7376) (#7383). [Yilou Wang]
 * Fix VPI access to Verilog `force`-ed signals (#7381). [Christian Hecken, Heidelberg University]
 * Fix sampling of hierarchical references (#7386). [Ryszard Rozak, Antmicro Ltd.]
 * Fix virtual class inheritance false error (#7403) (#7405). [Nikolay Puzanov]

test_regress/t/t_trace_split_struct.v

@@ -9,7 +9,10 @@
 
 bit global_bit;
 
-module t (clk, clk2);
+module t (
+    clk,
+    clk2
+);
   input clk;
   input clk2;
   integer cyc = 0;
@@ -39,7 +42,6 @@ module t (clk, clk2);
   always @(posedge clk2) begin
     v_strp.b1 <= cyc[1];
     v_strp2.b1 <= cyc[3];
-     for (int i = -1; i > -8; i--)
-       unpacked_array[i] = cyc[7:0];
+    for (int i = -1; i > -8; i--) unpacked_array[i] = cyc[7:0];
   end
 endmodule

test_regress/t/t_trace_struct_array_multi_inst.v

@@ -22,8 +22,14 @@ module t (
     end
   end
 
-  sub sub_a (.clk, .seed(cnt));
-  sub sub_b (.clk, .seed(cnt + 100));
+  sub sub_a (
+      .clk,
+      .seed(cnt)
+  );
+  sub sub_b (
+      .clk,
+      .seed(cnt + 100)
+  );
 endmodule
 
 module sub (
@@ -46,11 +52,15 @@ module sub (
   outer_t uarr[1:0];
 
   always @(posedge clk) begin
-    uarr[0] <= '{sub: '{x: seed[7:0], y: seed[15:8]},
+    uarr[0] <= '{
+        sub: '{x: seed[7:0], y: seed[15:8]},
         arr: '{seed[7:0], seed[7:0] + 8'd1},
-                 simple: seed[7:0]};
-    uarr[1] <= '{sub: '{x: ~seed[7:0], y: ~seed[15:8]},
+        simple: seed[7:0]
+    };
+    uarr[1] <= '{
+        sub: '{x: ~seed[7:0], y: ~seed[15:8]},
         arr: '{~seed[7:0], ~seed[7:0] + 8'd1},
-                 simple: ~seed[7:0]};
+        simple: ~seed[7:0]
+    };
   end
 endmodule

test_regress/t/t_trace_type_dupes.v

@@ -37,8 +37,7 @@ module t (/*AUTOARG*/
     always_comb loop_cyc = cyc + i;
     sub #(
         .data_t(pkg::some_struct_t)
-    )
-    the_sub (
+    ) the_sub (
         .a(loop_cyc[i%32]),
         .b(loop_cyc[(i+1)%32]),
         .x(x[i]),
@@ -49,9 +48,7 @@ module t (/*AUTOARG*/
     );
   end
 
-  intf
-  the_intf_a (.*),
-  the_intf_b (.*);
+  intf the_intf_a (.*), the_intf_b (.*);
 
   for (genvar m = 0; m < 4; m++) begin : gen_intf_loop
     always_comb begin
@@ -114,9 +111,7 @@ module sub #(
   some_unpacked_struct_t the_local_unpacked_struct;
 
   typedef union packed {
-    struct packed {
-      logic [7:0] field_0;
-    } union_a;
+    struct packed {logic [7:0] field_0;} union_a;
     struct packed {
       logic [3:0] field_1;
       logic [3:0] field_2;
@@ -148,20 +143,12 @@ module sub #(
         bar : '{cyc, cyc + 1, cyc + 2, cyc + 3},
         baz : cyc[15:0],
         qux : 128'(cyc),
-      sub_struct : '{
-        field_a : cyc[0],
-        field_b : cyc[5:0],
-        field_c : cyc[9:0]
-      }
+        sub_struct : '{field_a : cyc[0], field_b : cyc[5:0], field_c : cyc[9:0]}
     };
     for (int i = 0; i < 4; i++) the_structs[i] <= {$bits(pkg::some_struct_t) {cyc[i]}};
     the_local_struct <= cyc[2:0];
     the_typedefed_struct <= cyc[3:1];
-    the_local_unpacked_struct <= '{
-      field_a : cyc[0],
-      field_b : cyc[1],
-      field_c : cyc[2]
-    };
+    the_local_unpacked_struct <= '{field_a : cyc[0], field_b : cyc[1], field_c : cyc[2]};
     the_local_union <= cyc[7:0];
     for (int i = 0; i < 2; i++) begin
       the_logic_array[i] <= cyc + i;
@@ -178,8 +165,9 @@ module sub #(
   always_comb data = the_struct;
 endmodule
 
-interface intf
-  (input wire clk);
+interface intf (
+    input wire clk
+);
   logic [3:0][7:0] data;
   int data_typed;
   always_comb data_typed = data;