From 4fe121e5aa9a9d4ebe2033cdbe68a6658a2cb052 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 15 Apr 2026 17:46:08 -0400 Subject: [PATCH] Commentary: Changes update --- Changes | 4 + test_regress/t/t_trace_huge_array.v | 38 +++---- test_regress/t/t_trace_split_struct.v | 58 +++++----- test_regress/t/t_trace_struct_alias.v | 68 ++++++------ .../t/t_trace_struct_array_multi_inst.v | 30 +++-- test_regress/t/t_trace_type_alias.v | 60 +++++----- test_regress/t/t_trace_type_dupes.v | 104 ++++++++---------- 7 files changed, 183 insertions(+), 179 deletions(-) diff --git a/Changes b/Changes index d816b7ae3..f8ed05bde 100644 --- a/Changes +++ b/Changes @@ -54,6 +54,7 @@ Verilator 5.047 devel * Support sequence `first_match` operator (#7392). [Yilou Wang] * Support nonconsecutive repetition [=N] in sequence expressions (#7397). [Yilou Wang] * Support per-process RNG for process::srandom() and object seeding (#7408) (#7415) (#7408). [Yilou Wang] +* Support 2**n expressions in constraint randomization (#7422). [Yilou Wang] * Add VPI callback support to --main (#7145). * Add V3LiftExpr pass to lower impure expressions and calls (#7141) (#7164). [Geza Lore, Testorrent USA, Inc.] * Add --func-recursion-depth CLI option (#7175) (#7179). @@ -66,6 +67,7 @@ Verilator 5.047 devel * Change array tracing to dump left index to right index (#7205). [Geza Lore, Testorrent USA, Inc.] * Change `--converge-limit` default to 10000 (#7209). * Remove DFG extract optimization pass (#7394). [Geza Lore, Testorrent USA, Inc.] +* Optimize trace code for faster compiles on repeated types (#6707) (#6832). [Todd Strader] * Optimize size of trace declaration object code (#7150). [Szymon Gizler, Antmicro Ltd.] * Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.] * Optimize conditional merging across some impure statements (#7159). [Geza Lore, Testorrent USA, Inc.] @@ -77,6 +79,7 @@ Verilator 5.047 devel * Optimize more patterns in DfgPeephole (#7332). [Geza Lore, Testorrent USA, Inc.] * Optimize read references in DFG (#7354). [Geza Lore, Testorrent USA, Inc.] * Optimize DFG only once, after scoping (#7362). [Geza Lore, Testorrent USA, Inc.] +* Optimize more DFG peephole patterns (#7423). [Geza Lore, Testorrent USA, Inc.] * Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier] * Fix virtual interface member trigger convergence (#5116) (#7323). [Yilou Wang] * Fix shift width mismatch in constraint solver SMT emission (#5420) (#7265). [Yilou Wang] @@ -139,6 +142,7 @@ Verilator 5.047 devel * Fix virtual interface function calls binding to wrong instance (#7363). [Yilou Wang] * Fix false ASSIGNIN on interface input port connections (#7365). [Yilou Wang] * Fix string `inside` queue (#7373). +* Fix subclass with rand_mode(0) getting randomized (#7376) (#7383). [Yilou Wang] * Fix VPI access to Verilog `force`-ed signals (#7381). [Christian Hecken, Heidelberg University] * Fix sampling of hierarchical references (#7386). [Ryszard Rozak, Antmicro Ltd.] * Fix virtual class inheritance false error (#7403) (#7405). [Nikolay Puzanov] diff --git a/test_regress/t/t_trace_huge_array.v b/test_regress/t/t_trace_huge_array.v index aa71ff1d7..b3c06f3ef 100644 --- a/test_regress/t/t_trace_huge_array.v +++ b/test_regress/t/t_trace_huge_array.v @@ -4,26 +4,26 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; - int cyc = 0; + input clk; + int cyc = 0; - localparam max = 1000; - logic [31:0] foo [max:0]; - logic [max:0] [15:0] [31:0] bar; + localparam max = 1000; + logic [31:0] foo[max:0]; + logic [max:0][15:0][31:0] bar; - always_ff @(posedge clk) begin - cyc <= cyc + 1; - foo[0] <= cyc; - for (int i = 1; i <= max; i++) foo[i] <= foo[i-1]; - bar <= (bar << 32) | type(bar)'(cyc); - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always_ff @(posedge clk) begin + cyc <= cyc + 1; + foo[0] <= cyc; + for (int i = 1; i <= max; i++) foo[i] <= foo[i-1]; + bar <= (bar << 32) | type (bar)'(cyc); + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_trace_split_struct.v b/test_regress/t/t_trace_split_struct.v index 8e0f3e8b8..891f1ff47 100644 --- a/test_regress/t/t_trace_split_struct.v +++ b/test_regress/t/t_trace_split_struct.v @@ -9,37 +9,39 @@ bit global_bit; -module t (clk, clk2); - input clk; - input clk2; - integer cyc = 0; +module t ( + clk, + clk2 +); + input clk; + input clk2; + integer cyc = 0; - typedef struct packed { - bit b1; - bit b0; - } strp_t; + typedef struct packed { + bit b1; + bit b0; + } strp_t; - strp_t v_strp, v_strp2; - logic foo; + strp_t v_strp, v_strp2; + logic foo; - logic [7:0] unpacked_array[-7:0]; + logic [7:0] unpacked_array[-7:0]; - always @ (posedge clk) begin - cyc <= cyc + 1; - foo <= ~foo; - v_strp.b0 <= cyc[0]; - v_strp2.b0 <= cyc[2]; - unpacked_array[0] = cyc[8:1]; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + foo <= ~foo; + v_strp.b0 <= cyc[0]; + v_strp2.b0 <= cyc[2]; + unpacked_array[0] = cyc[8:1]; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always @(posedge clk2) begin - v_strp.b1 <= cyc[1]; - v_strp2.b1 <= cyc[3]; - for (int i = -1; i > -8; i--) - unpacked_array[i] = cyc[7:0]; - end + always @(posedge clk2) begin + v_strp.b1 <= cyc[1]; + v_strp2.b1 <= cyc[3]; + for (int i = -1; i > -8; i--) unpacked_array[i] = cyc[7:0]; + end endmodule diff --git a/test_regress/t/t_trace_struct_alias.v b/test_regress/t/t_trace_struct_alias.v index 3019a929f..c3dec9f3f 100644 --- a/test_regress/t/t_trace_struct_alias.v +++ b/test_regress/t/t_trace_struct_alias.v @@ -4,44 +4,44 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - int cyc; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; + int cyc; - typedef struct packed { - logic [7:0] a; - logic [7:0] b; - } strp_t; + typedef struct packed { + logic [7:0] a; + logic [7:0] b; + } strp_t; - strp_t s1; - strp_t s2; + strp_t s1; + strp_t s2; - strp_t s3; - logic [7:0] alias_of_s3a; - assign alias_of_s3a = s3.a; + strp_t s3; + logic [7:0] alias_of_s3a; + assign alias_of_s3a = s3.a; - strp_t s4; - strp_t s5; - assign s5 = s4; + strp_t s4; + strp_t s5; + assign s5 = s4; - logic [7:0] source_val; - strp_t s6; - assign s6.a = source_val; + logic [7:0] source_val; + strp_t s6; + assign s6.a = source_val; - always @(posedge clk) begin - cyc <= cyc + 1; - s1 <= {8'(cyc), 8'(cyc + 1)}; - s2 <= {8'(cyc + 2), 8'(cyc + 3)}; - s3 <= {8'(cyc + 4), 8'(cyc + 5)}; - s4 <= {8'(cyc + 6), 8'(cyc + 7)}; - source_val <= 8'(cyc + 8); - s6.b <= 8'(cyc + 9); - if (cyc == 9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + s1 <= {8'(cyc), 8'(cyc + 1)}; + s2 <= {8'(cyc + 2), 8'(cyc + 3)}; + s3 <= {8'(cyc + 4), 8'(cyc + 5)}; + s4 <= {8'(cyc + 6), 8'(cyc + 7)}; + source_val <= 8'(cyc + 8); + s6.b <= 8'(cyc + 9); + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_trace_struct_array_multi_inst.v b/test_regress/t/t_trace_struct_array_multi_inst.v index 0eabe6bf5..b82b37fbf 100644 --- a/test_regress/t/t_trace_struct_array_multi_inst.v +++ b/test_regress/t/t_trace_struct_array_multi_inst.v @@ -22,8 +22,14 @@ module t ( end end - sub sub_a (.clk, .seed(cnt)); - sub sub_b (.clk, .seed(cnt + 100)); + sub sub_a ( + .clk, + .seed(cnt) + ); + sub sub_b ( + .clk, + .seed(cnt + 100) + ); endmodule module sub ( @@ -38,19 +44,23 @@ module sub ( typedef struct packed { inner_t sub; - logic [1:0] [7:0] arr; + logic [1:0][7:0] arr; logic [7:0] simple; } outer_t; // Unpacked array of struct with nested sub-struct and packed array - outer_t uarr [1:0]; + outer_t uarr[1:0]; always @(posedge clk) begin - uarr[0] <= '{sub: '{x: seed[7:0], y: seed[15:8]}, - arr: '{seed[7:0], seed[7:0]+8'd1}, - simple: seed[7:0]}; - uarr[1] <= '{sub: '{x: ~seed[7:0], y: ~seed[15:8]}, - arr: '{~seed[7:0], ~seed[7:0]+8'd1}, - simple: ~seed[7:0]}; + uarr[0] <= '{ + sub: '{x: seed[7:0], y: seed[15:8]}, + arr: '{seed[7:0], seed[7:0] + 8'd1}, + simple: seed[7:0] + }; + uarr[1] <= '{ + sub: '{x: ~seed[7:0], y: ~seed[15:8]}, + arr: '{~seed[7:0], ~seed[7:0] + 8'd1}, + simple: ~seed[7:0] + }; end endmodule diff --git a/test_regress/t/t_trace_type_alias.v b/test_regress/t/t_trace_type_alias.v index a139451df..9a811abb4 100644 --- a/test_regress/t/t_trace_type_alias.v +++ b/test_regress/t/t_trace_type_alias.v @@ -6,41 +6,41 @@ module Sub #( parameter int data_width -)( +) ( input clk, - output logic [data_width-1:0] read_data + output logic [data_width-1:0] read_data ); - logic [0:0][data_width-1:0] read_data_2d; - always_ff @(posedge clk) read_data_2d <= $random; - always_comb read_data = read_data_2d[0]; + logic [0:0][data_width-1:0] read_data_2d; + always_ff @(posedge clk) read_data_2d <= $random; + always_comb read_data = read_data_2d[0]; endmodule module t (); - typedef struct packed { - logic [7:0] field_a; - logic [7:0] field_b; - logic [7:0] field_c; - logic field_d; - logic field_e; - logic field_f; - logic field_g; - logic field_h; - logic field_i; - logic field_j; - logic field_k; - } struct_t; - struct_t the_struct; - logic clk; + typedef struct packed { + logic [7:0] field_a; + logic [7:0] field_b; + logic [7:0] field_c; + logic field_d; + logic field_e; + logic field_f; + logic field_g; + logic field_h; + logic field_i; + logic field_j; + logic field_k; + } struct_t; + struct_t the_struct; + logic clk; - Sub #( - .data_width ($bits(struct_t)) - ) the_sub( - .clk, - .read_data (the_struct) - ); + Sub #( + .data_width($bits(struct_t)) + ) the_sub ( + .clk, + .read_data(the_struct) + ); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_trace_type_dupes.v b/test_regress/t/t_trace_type_dupes.v index 7cb009403..f0c783e72 100644 --- a/test_regress/t/t_trace_type_dupes.v +++ b/test_regress/t/t_trace_type_dupes.v @@ -13,10 +13,10 @@ `endif -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); input clk; int cyc; @@ -36,22 +36,19 @@ module t (/*AUTOARG*/ int loop_cyc; always_comb loop_cyc = cyc + i; sub #( - .data_t (pkg::some_struct_t) - ) - the_sub ( - .a (loop_cyc[i%32]), - .b (loop_cyc[(i+1)%32]), - .x (x[i]), - .out_2d_unpacked (), - .data (), - .cyc (loop_cyc), - .clk + .data_t(pkg::some_struct_t) + ) the_sub ( + .a(loop_cyc[i%32]), + .b(loop_cyc[(i+1)%32]), + .x(x[i]), + .out_2d_unpacked(), + .data(), + .cyc(loop_cyc), + .clk ); end - intf - the_intf_a (.*), - the_intf_b (.*); + intf the_intf_a (.*), the_intf_b (.*); for (genvar m = 0; m < 4; m++) begin : gen_intf_loop always_comb begin @@ -71,7 +68,7 @@ package pkg; typedef struct packed { logic foo; - logic [3:0] [31:0] bar; + logic [3:0][31:0] bar; logic [15:0] baz; logic [127:0] qux; some_sub_struct_t sub_struct; @@ -82,18 +79,18 @@ package pkg; endpackage module sub #( - parameter type data_t = bit -)( - input a, - input b, - output logic x, - output out_2d_unpacked [3][4], - output data_t data, - input int cyc, - input clk + parameter type data_t = bit +) ( + input a, + input b, + output logic x, + output out_2d_unpacked[3][4], + output data_t data, + input int cyc, + input clk ); pkg::some_struct_t the_struct; - pkg::some_struct_t the_structs [3:0]; + pkg::some_struct_t the_structs[3:0]; pkg::some_struct_t [2:0] the_packed_structs; typedef struct packed { @@ -114,9 +111,7 @@ module sub #( some_unpacked_struct_t the_local_unpacked_struct; typedef union packed { - struct packed { - logic [7:0] field_0; - } union_a; + struct packed {logic [7:0] field_0;} union_a; struct packed { logic [3:0] field_1; logic [3:0] field_2; @@ -128,13 +123,13 @@ module sub #( } some_union_t; some_union_t the_local_union; - typedef logic [1:0] [31:0] logic_array_t; - typedef logic [1:0] [31:0] logic_array_2_t; + typedef logic [1:0][31:0] logic_array_t; + typedef logic [1:0][31:0] logic_array_2_t; logic_array_t the_logic_array; logic_array_2_t the_other_logic_array; - logic [15:0] the_unpacked_array [5]; - logic the_2d_unpacked [3][4]; - string the_string_array [3:0]; + logic [15:0] the_unpacked_array[5]; + logic the_2d_unpacked[3][4]; + string the_string_array[3:0]; typedef logic [3:0] four_bit_t; typedef four_bit_t [1:0] two_fours_t; @@ -144,24 +139,16 @@ module sub #( always_ff @(posedge clk) begin x <= a ^ b; the_struct <= '{ - foo : cyc[0], - bar : '{cyc, cyc+1, cyc+2, cyc+3}, - baz : cyc[15:0], - qux : 128'(cyc), - sub_struct : '{ - field_a : cyc[0], - field_b : cyc[5:0], - field_c : cyc[9:0] - } + foo : cyc[0], + bar : '{cyc, cyc + 1, cyc + 2, cyc + 3}, + baz : cyc[15:0], + qux : 128'(cyc), + sub_struct : '{field_a : cyc[0], field_b : cyc[5:0], field_c : cyc[9:0]} }; - for (int i = 0; i < 4; i++) the_structs[i] <= {$bits(pkg::some_struct_t){cyc[i]}}; + for (int i = 0; i < 4; i++) the_structs[i] <= {$bits(pkg::some_struct_t) {cyc[i]}}; the_local_struct <= cyc[2:0]; the_typedefed_struct <= cyc[3:1]; - the_local_unpacked_struct <= '{ - field_a : cyc[0], - field_b : cyc[1], - field_c : cyc[2] - }; + the_local_unpacked_struct <= '{field_a : cyc[0], field_b : cyc[1], field_c : cyc[2]}; the_local_union <= cyc[7:0]; for (int i = 0; i < 2; i++) begin the_logic_array[i] <= cyc + i; @@ -169,18 +156,19 @@ module sub #( end for (int i = 0; i < 5; i++) the_unpacked_array[i] <= cyc[15:0]; for (int i = 0; i < 3; i++) - for (int j = 0; j < 4; j++) begin - the_2d_unpacked [i][j] <= ~(cyc[i] ^ cyc[j]); - out_2d_unpacked [i][j] <= cyc[i] ^ cyc[j]; - end + for (int j = 0; j < 4; j++) begin + the_2d_unpacked[i][j] <= ~(cyc[i] ^ cyc[j]); + out_2d_unpacked[i][j] <= cyc[i] ^ cyc[j]; + end end always_comb data = the_struct; endmodule -interface intf - (input wire clk); - logic [3:0] [7:0] data; +interface intf ( + input wire clk +); + logic [3:0][7:0] data; int data_typed; always_comb data_typed = data; endinterface