Fix V3Assert stale failsp after recursive iteration (#7500) (#7513)

Fixes #7500.
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Nikolai Kumar 2026-04-29 04:18:12 -05:00 committed by GitHub
parent 8f18f0cf22
commit 4ebc4f1eee
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3 changed files with 64 additions and 0 deletions

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@ -429,6 +429,11 @@ class AssertVisitor final : public VNVisitor {
const string& message = nodep->name();
AstNode* passsp = nodep->passsp();
if (passsp) passsp->unlinkFrBackWithNext();
if (AstAssert* const assertp = VN_CAST(nodep, Assert)) {
failsp = assertp->failsp();
} else if (AstAssertIntrinsic* const assertp = VN_CAST(nodep, AssertIntrinsic)) {
failsp = assertp->failsp();
}
if (failsp) failsp->unlinkFrBackWithNext();
bool selfDestruct = false;

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@ -0,0 +1,21 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
if not test.have_solver:
test.skip("No constraint solver installed")
test.compile(verilator_flags2=["--binary"])
test.execute()
test.passes()

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@ -0,0 +1,38 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Nikolai Kumar
// SPDX-License-Identifier: CC0-1.0
module t;
int x;
int pass_count, fail_count;
initial begin
pass_count = 0;
fail_count = 0;
assert((std::randomize(x) with {x inside {10, 20}; }) == 1)
pass_count++;
else
assert((std::randomize(x) with {x inside {1, 2}; }) == 1)
fail_count++; //Should not run
assert((std::randomize(x) with {x > 100; x inside {1, 2 , 3}; }) == 1)
pass_count++; //Should not run
else
assert((std::randomize(x) with {x inside {40, 50}; }) == 1)
fail_count++;
if(pass_count != 1) begin
$display("FAIL: pass_count=%0d expected 1", pass_count);
$stop;
end
if(fail_count != 1) begin
$display("FAIL: fail_count=%0d expected 1", fail_count);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule