From 4ebc4f1eeeebc19fd056da2cad99116aaa159c1d Mon Sep 17 00:00:00 2001
From: Nikolai Kumar <nikolai.kumar@gmail.com>
Date: Wed, 29 Apr 2026 04:18:12 -0500
Subject: [PATCH] Fix V3Assert stale failsp after recursive iteration (#7500)
 (#7513)

Fixes #7500.
---
 src/V3Assert.cpp                          |  5 +++
 test_regress/t/t_randomize_inside_cond.py | 21 +++++++++++++
 test_regress/t/t_randomize_inside_cond.v  | 38 +++++++++++++++++++++++
 3 files changed, 64 insertions(+)
 create mode 100755 test_regress/t/t_randomize_inside_cond.py
 create mode 100644 test_regress/t/t_randomize_inside_cond.v

diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp
index 22eea94a4..278e2995f 100644
--- a/src/V3Assert.cpp
+++ b/src/V3Assert.cpp
@@ -429,6 +429,11 @@ class AssertVisitor final : public VNVisitor {
         const string& message = nodep->name();
         AstNode* passsp = nodep->passsp();
         if (passsp) passsp->unlinkFrBackWithNext();
+        if (AstAssert* const assertp = VN_CAST(nodep, Assert)) {
+            failsp = assertp->failsp();
+        } else if (AstAssertIntrinsic* const assertp = VN_CAST(nodep, AssertIntrinsic)) {
+            failsp = assertp->failsp();
+        }
         if (failsp) failsp->unlinkFrBackWithNext();
 
         bool selfDestruct = false;
diff --git a/test_regress/t/t_randomize_inside_cond.py b/test_regress/t/t_randomize_inside_cond.py
new file mode 100755
index 000000000..81df8362d
--- /dev/null
+++ b/test_regress/t/t_randomize_inside_cond.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+if not test.have_solver:
+    test.skip("No constraint solver installed")
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_randomize_inside_cond.v b/test_regress/t/t_randomize_inside_cond.v
new file mode 100644
index 000000000..694b161e9
--- /dev/null
+++ b/test_regress/t/t_randomize_inside_cond.v
@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Nikolai Kumar
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  int x;
+  int pass_count, fail_count;
+
+  initial begin
+    pass_count = 0;
+    fail_count = 0;
+
+    assert((std::randomize(x) with {x inside {10, 20}; }) == 1)
+      pass_count++;
+    else
+      assert((std::randomize(x) with {x inside {1, 2}; }) == 1)
+      fail_count++; //Should not run
+
+    assert((std::randomize(x) with {x > 100; x inside {1, 2 , 3}; }) == 1)
+      pass_count++; //Should not run
+    else
+      assert((std::randomize(x) with {x inside {40, 50}; }) == 1)
+      fail_count++;
+
+    if(pass_count != 1) begin
+      $display("FAIL: pass_count=%0d expected 1", pass_count);
+      $stop;
+    end
+    if(fail_count != 1) begin
+      $display("FAIL: fail_count=%0d expected 1", fail_count);
+      $stop;
+    end
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule