luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Commentary: Fix broken links

This commit is contained in:
Wilson Snyder 2025-06-15 14:51:56 -04:00
parent d059806dbd
commit 4c2eb8c0b8
4 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
docs/guide/contributors.rst
View File

@ -23,8 +23,8 @@ Contributors
Many people have provided ideas and other assistance with Verilator. Many people have provided ideas and other assistance with Verilator.
Verilator is receiving significant development support from the `CHIPS Verilator is receiving significant development support from the `CHIPS
Alliance <https://chipsalliance.org>`_, `Antmicro Ltd Alliance <https://chipsalliance.org>`_, and `Antmicro Ltd
<https://antmicro.com>`_ and `Shunyao CAD <https://shunyaocad.com>`_. <https://antmicro.com>`_.
Previous major corporate sponsors of Verilator, by providing significant Previous major corporate sponsors of Verilator, by providing significant
contributions of time or funds include: Antmicro Ltd., Atmel Corporation, contributions of time or funds include: Antmicro Ltd., Atmel Corporation,

2
docs/guide/exe_verilator.rst
View File

@ -398,7 +398,7 @@ Summary:
Enables diagnostics output into a Static Analysis Results Interchange Enables diagnostics output into a Static Analysis Results Interchange
Format (SARIF) file, a standard, JSON-based format for the output of Format (SARIF) file, a standard, JSON-based format for the output of
static analysis tools such as linters. See static analysis tools such as linters. See
[SARIF](http://sarifweb.azurewebsites.net/), [SARIF](https://sarifweb.azurewebsites.net/),
[sarif-tools](https://github.com/microsoft/sarif-tools), and the [SARIF [sarif-tools](https://github.com/microsoft/sarif-tools), and the [SARIF
web-based viewer](https://microsoft.github.io/sarif-web-component/). web-based viewer](https://microsoft.github.io/sarif-web-component/).

2
docs/guide/install.rst
View File

@ -194,7 +194,7 @@ Install Z3
^^^^^^^^^^ ^^^^^^^^^^
In order to use constrained randomization the `Z3 Theorem Prover In order to use constrained randomization the `Z3 Theorem Prover
<https://github.com/z3prover/z3#readme>`__ must be installed, however this is <https://github.com/z3prover/z3>`__ must be installed, however this is
not required at Verilator build time. There are other compatible SMT solvers, not required at Verilator build time. There are other compatible SMT solvers,
like CVC5/CVC4, but they are not guaranteed to work. Since different solvers are like CVC5/CVC4, but they are not guaranteed to work. Since different solvers are
faster for different scenarios, the solver to use at run-time can be specified faster for different scenarios, the solver to use at run-time can be specified

8
docs/guide/warnings.rst
View File

@ -363,8 +363,8 @@ List Of Warnings
Warns that it is better style to use casez, and "?" in place of Warns that it is better style to use casez, and "?" in place of
"x"'s. See "x"'s. See
`http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf
<http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf>`_ <http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf>`_
Ignoring this warning will only suppress the lint check; it will Ignoring this warning will only suppress the lint check; it will
simulate correctly. simulate correctly.
@ -438,8 +438,8 @@ List Of Warnings
is suppressed, Verilator, like synthesis, will convert this to a is suppressed, Verilator, like synthesis, will convert this to a
non-delayed assignment, which may result in logic races or other non-delayed assignment, which may result in logic races or other
nasties. See nasties. See
`http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf `http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf
<http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf>`_ <http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf>`_
Ignoring this warning may make Verilator simulations differ from other Ignoring this warning may make Verilator simulations differ from other
simulators. simulators.