From 4c2eb8c0b8587e66899eb3bf6cd53ffbd1acc37e Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 15 Jun 2025 14:51:56 -0400 Subject: [PATCH] Commentary: Fix broken links --- docs/guide/contributors.rst | 4 ++-- docs/guide/exe_verilator.rst | 2 +- docs/guide/install.rst | 2 +- docs/guide/warnings.rst | 8 ++++---- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/docs/guide/contributors.rst b/docs/guide/contributors.rst index 504ca4698..3d6881f3f 100644 --- a/docs/guide/contributors.rst +++ b/docs/guide/contributors.rst @@ -23,8 +23,8 @@ Contributors Many people have provided ideas and other assistance with Verilator. Verilator is receiving significant development support from the `CHIPS -Alliance `_, `Antmicro Ltd -`_ and `Shunyao CAD `_. +Alliance `_, and `Antmicro Ltd +`_. Previous major corporate sponsors of Verilator, by providing significant contributions of time or funds include: Antmicro Ltd., Atmel Corporation, diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 8858e25dd..938152af8 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -398,7 +398,7 @@ Summary: Enables diagnostics output into a Static Analysis Results Interchange Format (SARIF) file, a standard, JSON-based format for the output of static analysis tools such as linters. See - [SARIF](http://sarifweb.azurewebsites.net/), + [SARIF](https://sarifweb.azurewebsites.net/), [sarif-tools](https://github.com/microsoft/sarif-tools), and the [SARIF web-based viewer](https://microsoft.github.io/sarif-web-component/). diff --git a/docs/guide/install.rst b/docs/guide/install.rst index d54e7c5d0..333dde197 100644 --- a/docs/guide/install.rst +++ b/docs/guide/install.rst @@ -194,7 +194,7 @@ Install Z3 ^^^^^^^^^^ In order to use constrained randomization the `Z3 Theorem Prover -`__ must be installed, however this is +`__ must be installed, however this is not required at Verilator build time. There are other compatible SMT solvers, like CVC5/CVC4, but they are not guaranteed to work. Since different solvers are faster for different scenarios, the solver to use at run-time can be specified diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index 3827c9b89..66ea9de5d 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -363,8 +363,8 @@ List Of Warnings Warns that it is better style to use casez, and "?" in place of "x"'s. See - `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf - `_ + `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf + `_ Ignoring this warning will only suppress the lint check; it will simulate correctly. @@ -438,8 +438,8 @@ List Of Warnings is suppressed, Verilator, like synthesis, will convert this to a non-delayed assignment, which may result in logic races or other nasties. See - `http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf - `_ + `http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf + `_ Ignoring this warning may make Verilator simulations differ from other simulators.