diff --git a/Makefile.in b/Makefile.in index 164e7768f..c77a1c338 100644 --- a/Makefile.in +++ b/Makefile.in @@ -577,7 +577,7 @@ MBAKE = mbake MBAKE_FLAGS = format --config ./.bake.toml format-exec: - -chmod a+x test_regress/t/*.py + -chmod a+x test_regress/t/t_*.py -chmod a-x test_regress/t/*.v format-make mbake: diff --git a/include/verilated_saif_c.cpp b/include/verilated_saif_c.cpp index bcec00c76..abff785ce 100644 --- a/include/verilated_saif_c.cpp +++ b/include/verilated_saif_c.cpp @@ -88,14 +88,15 @@ public: class VerilatedSaifActivityVar final { // MEMBERS - uint64_t m_lastTime = 0; // Last time when variable value was updated + uint64_t m_lastTime; // Last time when variable value was updated VerilatedSaifActivityBit* m_bits; // Pointer to variable bits objects uint32_t m_width; // Width of variable (in bits) public: // CONSTRUCTORS - VerilatedSaifActivityVar(uint32_t width, VerilatedSaifActivityBit* bits) - : m_bits{bits} + VerilatedSaifActivityVar(uint64_t startTime, uint32_t width, VerilatedSaifActivityBit* bits) + : m_lastTime{startTime} + , m_bits{bits} , m_width{width} {} VerilatedSaifActivityVar(VerilatedSaifActivityVar&&) = default; @@ -203,7 +204,7 @@ class VerilatedSaifActivityAccumulator final { public: // METHODS void declare(uint32_t code, const std::string& absoluteScopePath, std::string variableName, - int bits, bool array, int arraynum); + int bits, bool array, int arraynum, uint64_t startTime); // CONSTRUCTORS VerilatedSaifActivityAccumulator() = default; @@ -252,7 +253,7 @@ VerilatedSaifActivityBit& VerilatedSaifActivityVar::bit(const std::size_t index) void VerilatedSaifActivityAccumulator::declare(uint32_t code, const std::string& absoluteScopePath, std::string variableName, int bits, bool array, - int arraynum) { + int arraynum, uint64_t startTime) { const size_t block_size = 1024; if (m_activityArena.empty() || m_activityArena.back().size() + bits > m_activityArena.back().capacity()) { @@ -268,7 +269,7 @@ void VerilatedSaifActivityAccumulator::declare(uint32_t code, const std::string& variableName += ']'; } m_scopeToActivities[absoluteScopePath].emplace_back(code, variableName); - m_activity.emplace(code, VerilatedSaifActivityVar{static_cast(bits), + m_activity.emplace(code, VerilatedSaifActivityVar{startTime, static_cast(bits), m_activityArena.back().data() + bitsIdx}); } @@ -277,18 +278,18 @@ void VerilatedSaifActivityAccumulator::declare(uint32_t code, const std::string& //============================================================================= // VerilatedSaif implementation -VerilatedSaif::VerilatedSaif(void* filep) { - m_activityAccumulators.emplace_back(std::make_unique()); -} +VerilatedSaif::VerilatedSaif(void* filep) {} void VerilatedSaif::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) { const VerilatedLockGuard lock{m_mutex}; if (isOpen()) return; + m_startTime = currentTime(); m_filename = filename; // "" is ok, as someone may overload open m_filep = ::open(m_filename.c_str(), O_CREAT | O_WRONLY | O_TRUNC | O_LARGEFILE | O_NONBLOCK | O_CLOEXEC, 0666); m_isOpen = true; + m_activityAccumulators.emplace_back(std::make_unique()); initializeSaifFileContents(); @@ -328,7 +329,7 @@ void VerilatedSaif::close() VL_MT_SAFE_EXCLUDES(m_mutex) { void VerilatedSaif::finalizeSaifFileContents() { printStr("(DURATION "); - printStr(std::to_string(currentTime())); + printStr(std::to_string(currentTime() - m_startTime)); printStr(")\n"); incrementIndent(); @@ -419,7 +420,7 @@ bool VerilatedSaif::printActivityStats(VerilatedSaifActivityVar& activity, // We only have two-value logic so TZ, TX and TB will always be 0 printStr(" (T0 "); - printStr(std::to_string(currentTime() - bit.highTime())); + printStr(std::to_string(currentTime() - m_startTime - bit.highTime())); printStr(") (T1 "); printStr(std::to_string(bit.highTime())); printStr(") (TZ 0) (TX 0) (TB 0) (TC "); @@ -451,7 +452,8 @@ void VerilatedSaif::printStr(const std::string& str) { void VerilatedSaif::writeBuffered(bool force) { if (VL_UNLIKELY(m_buffer.size() >= WRITE_BUFFER_SIZE || force)) { if (VL_UNLIKELY(!m_buffer.empty())) { - ::write(m_filep, m_buffer.data(), m_buffer.size()); + const ssize_t n = ::write(m_filep, m_buffer.data(), m_buffer.size()); + assert(n == static_cast(m_buffer.size())); m_buffer = ""; m_buffer.reserve(WRITE_BUFFER_SIZE * 2); } @@ -544,7 +546,7 @@ void VerilatedSaif::declare(const uint32_t code, uint32_t fidx, const char* name m_currentScope->addActivityVar(code, variableName); accumulator.declare(code, m_currentScope->path(), std::move(variableName), bits, array, - arraynum); + arraynum, m_startTime); } // versions to call when the sig is not array member diff --git a/include/verilated_saif_c.h b/include/verilated_saif_c.h index b3a46fa6c..af7766b9e 100644 --- a/include/verilated_saif_c.h +++ b/include/verilated_saif_c.h @@ -51,6 +51,7 @@ private: int m_filep = 0; // File we're writing to bool m_isOpen = false; // True indicates open file + uint64_t m_startTime = 0; // Time file was opened std::string m_filename; // Filename we're writing to (if open) std::string m_buffer; // Write data buffer diff --git a/test_regress/driver.py b/test_regress/driver.py index 5fb8d3e5e..da0e79fa0 100755 --- a/test_regress/driver.py +++ b/test_regress/driver.py @@ -1697,6 +1697,13 @@ class VlTest: self._ok = False return self._ok + def parse_name(self, regex: str): + basename = os.path.basename(test.py_filename) + match = re.match(regex, basename.partition(".")[0]) + if match is None: + test.error(f"Invalid test file name '{basename}") + return match.groups() + def passes(self, is_ok=True): if not self.errors: self._ok = is_ok @@ -2562,6 +2569,17 @@ class VlTest: self.copy_if_golden(fn1, fn2) self.error("SAIF files miscompare") + def trace_identical(self, traceFn: str, goldenFn: str, ignore_attr: bool = False) -> None: + match traceFn.rpartition(".")[-1]: + case "vcd": + self.vcd_identical(traceFn, goldenFn, ignore_attr) + case "fst": + self.fst_identical(traceFn, goldenFn, ignore_attr) + case "saif": + self.saif_identical(traceFn, goldenFn) + case _: + self.error("Unknown trace file format " + traceFn) + def _vcd_read(self, filename: str) -> dict: data = {} with open(filename, 'r', encoding='latin-1') as fh: diff --git a/test_regress/t/t_hier_block_sc_trace_fst.py b/test_regress/t/t_hier_block_sc_trace_fst.py deleted file mode 100755 index 3ce35e02c..000000000 --- a/test_regress/t/t_hier_block_sc_trace_fst.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.priority(30) -test.scenarios('vlt_all') -test.top_filename = "t/t_hier_block.v" - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -test.clean_objs() - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. - -test.compile(v_flags2=['t/t_hier_block.cpp'], - verilator_flags2=[ - '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - "--CFLAGS", '"-O0 -ggdb"', "--trace-fst" - ], - threads=(6 if test.vltmt else 1)) - -test.execute() - -test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") -test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") -test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") -test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) -test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.py b/test_regress/t/t_hier_block_sc_trace_vcd.py deleted file mode 100755 index 3611b93bf..000000000 --- a/test_regress/t/t_hier_block_sc_trace_vcd.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.priority(30) -test.scenarios('vlt_all') -test.top_filename = "t/t_hier_block.v" - -# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. -test.clean_objs() - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. - -test.compile(v_flags2=['t/t_hier_block.cpp'], - verilator_flags2=[ - '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - "--CFLAGS", '"-O0 -ggdb"', "--trace-vcd" - ], - threads=(6 if test.vltmt else 1)) - -test.execute() - -test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") -test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") -test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") -test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) -test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_hier_block_trace_fst.py b/test_regress/t/t_hier_block_trace_fst.py deleted file mode 100755 index 354bc4beb..000000000 --- a/test_regress/t/t_hier_block_trace_fst.py +++ /dev/null @@ -1,63 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -noinline = "noinl" in test.name -notop = "notop" in test.name -if not noinline and not notop: - test.priority(30) -test.scenarios('vlt_all') -test.top_filename = "t/t_hier_block.v" - -verilator_common_flags = [ - 't/t_hier_block.cpp', - '--Wno-TIMESCALEMOD', - '--trace-fst', - '--trace-underscore', # Should not trace handle - "--trace-max-width", - "0", - "--trace-max-array", - "0", - "--trace-structs", -] - -verilator_hier_flags = verilator_common_flags + ['--hierarchical'] -if noinline: - verilator_hier_flags.extend(["+define+NO_INLINE"]) -main_top_name = "top" -if notop: - main_top_name = "" - -# Compile hierarchically -test.vm_prefix = "Vhier" -test.main_filename = test.obj_dir + "/Vhier__main.cpp" -test.compile(verilator_flags2=verilator_hier_flags, main_top_name=main_top_name) - -# Compile non-hierarchically -test.vm_prefix = "Vnonh" -test.main_filename = test.obj_dir + "/Vnonh__main.cpp" -test.compile(verilator_flags2=verilator_common_flags, main_top_name=main_top_name) - -trace_hier = test.trace_filename.replace("simx", "hier") -trace_nonh = test.trace_filename.replace("simx", "nonh") - -# Run the hierarchical model -test.execute(executable=test.obj_dir + "/Vhier") -test.run(cmd=["mv", test.trace_filename, trace_hier]) -# Run the non-hierarchical model -test.execute(executable=test.obj_dir + "/Vnonh") -test.run(cmd=["mv", test.trace_filename, trace_nonh]) - -# The two models must match - ignore enum type attributes which can differ -test.fst_identical(trace_hier, trace_nonh, ignore_attr=True) -# The hierarchical must match the reference -test.fst_identical(trace_hier, test.golden_filename.replace("_noinl", "")) - -test.passes() diff --git a/test_regress/t/t_hier_block_trace_saif.py b/test_regress/t/t_hier_block_trace_saif.py deleted file mode 100755 index 6ccf85977..000000000 --- a/test_regress/t/t_hier_block_trace_saif.py +++ /dev/null @@ -1,63 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -noinline = "noinl" in test.name -notop = "notop" in test.name -if not noinline and not notop: - test.priority(30) -test.scenarios('vlt_all') -test.top_filename = "t/t_hier_block.v" - -verilator_common_flags = [ - 't/t_hier_block.cpp', - '--Wno-TIMESCALEMOD', - '--trace-saif', - '--trace-underscore', # Should not trace handle - "--trace-max-width", - "0", - "--trace-max-array", - "0", - "--trace-structs", -] - -verilator_hier_flags = verilator_common_flags + ['--hierarchical'] -if noinline: - verilator_hier_flags.extend(["+define+NO_INLINE"]) -main_top_name = "top" -if notop: - main_top_name = "" - -# Compile hierarchically -test.vm_prefix = "Vhier" -test.main_filename = test.obj_dir + "/Vhier__main.cpp" -test.compile(verilator_flags2=verilator_hier_flags, main_top_name=main_top_name) - -# Compile non-hierarchically -test.vm_prefix = "Vnonh" -test.main_filename = test.obj_dir + "/Vnonh__main.cpp" -test.compile(verilator_flags2=verilator_common_flags, main_top_name=main_top_name) - -trace_hier = test.trace_filename.replace("simx", "hier") -trace_nonh = test.trace_filename.replace("simx", "nonh") - -# Run the hierarchical model -test.execute(executable=test.obj_dir + "/Vhier") -test.run(cmd=["mv", test.trace_filename, trace_hier]) -# Run the non-hierarchical model -test.execute(executable=test.obj_dir + "/Vnonh") -test.run(cmd=["mv", test.trace_filename, trace_nonh]) - -# The two models must match -test.saif_identical(trace_hier, trace_nonh) -# The hierarchical must match the reference -test.saif_identical(trace_hier, test.golden_filename.replace("_noinl", "")) - -test.passes() diff --git a/test_regress/t/t_hier_block_trace_vcd.py b/test_regress/t/t_hier_block_trace_vcd.py deleted file mode 100755 index cb02ad46a..000000000 --- a/test_regress/t/t_hier_block_trace_vcd.py +++ /dev/null @@ -1,77 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -import re - -noinline = "noinl" in test.name -notop = "notop" in test.name -if not noinline and not notop: - test.priority(30) -test.scenarios('vlt_all') -test.top_filename = "t/t_hier_block.v" - -verilator_common_flags = [ - 't/t_hier_block.cpp', - '--Wno-TIMESCALEMOD', - '--trace-vcd', - '--trace-underscore', # Should not trace handle - "--trace-max-width", - "0", - "--trace-max-array", - "0", - "--trace-structs", -] - -verilator_hier_flags = verilator_common_flags + ['--hierarchical'] -if noinline: - verilator_hier_flags.extend(["+define+NO_INLINE"]) -main_top_name = "top" -if notop: - main_top_name = "" - -# Compile hierarchically -test.vm_prefix = "Vhier" -test.main_filename = test.obj_dir + "/Vhier__main.cpp" -test.compile(verilator_flags2=verilator_hier_flags, main_top_name=main_top_name) - -# Compile non-hierarchically -test.vm_prefix = "Vnonh" -test.main_filename = test.obj_dir + "/Vnonh__main.cpp" -test.compile(verilator_flags2=verilator_common_flags, main_top_name=main_top_name) - -trace_hier = test.trace_filename.replace("simx", "hier") -trace_nonh = test.trace_filename.replace("simx", "nonh") - -# Run the hierarchical model -test.execute(executable=test.obj_dir + "/Vhier") -test.run(cmd=["mv", test.trace_filename, trace_hier]) -# Run the non-hierarchical model -test.execute(executable=test.obj_dir + "/Vnonh") -test.run(cmd=["mv", test.trace_filename, trace_nonh]) - -# Scope structure must match exactly -with open(trace_nonh, 'r', encoding='utf8') as fnonh, open(trace_hier, 'r', - encoding='utf8') as fhier: - for la, lb in zip(fnonh, fhier): - la = re.sub(r'^(\s*\$var\s+\S+\s+\S+\s+)\S+(.*)$', r'\1CODE\2', la) - lb = re.sub(r'^(\s*\$var\s+\S+\s+\S+\s+)\S+(.*)$', r'\1CODE\2', lb) - if la != lb: - test.error_keep_going("VCD header mismatch: '{}' !~ '{}'".format( - la.strip(), lb.strip())) - if "enddefinitions" in la: - break - -# The two models must match -test.vcd_identical(trace_hier, trace_nonh) -# The hierarchical must match the reference -test.vcd_identical(trace_hier, test.golden_filename.replace("_noinl", "")) - -test.passes() diff --git a/test_regress/t/t_hier_block_trace_vcd_statful_pkg.py b/test_regress/t/t_hier_block_trace_vcd_statful_pkg.py deleted file mode 100755 index 00737a861..000000000 --- a/test_regress/t/t_hier_block_trace_vcd_statful_pkg.py +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.priority(30) -test.scenarios('vlt_all') -test.top_filename = "t/t_hier_block.v" - -test.compile(verilator_flags2=[ - 't/t_hier_block.cpp', '--Wno-TIMESCALEMOD', '--trace-vcd', '--trace-underscore', - "--trace-max-width", "0", "--trace-max-array", "0", "--trace-structs", "--hierarchical", - "+define+STATEFUL_PKG" -]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_hier_trace.py b/test_regress/t/t_hier_trace.py deleted file mode 100755 index a8d887dae..000000000 --- a/test_regress/t/t_hier_trace.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=[ - '--trace-vcd', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', - '--hierarchical', '-F t/t_hier_trace_sub/top.vc' -]) - -test.execute(all_run_flags=['-j 4']) - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_hier_trace_noinl.py b/test_regress/t/t_hier_trace_noinl.py deleted file mode 100755 index eb440b805..000000000 --- a/test_regress/t/t_hier_trace_noinl.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_hier_trace.v" - -test.compile(verilator_flags2=[ - '--trace-vcd', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', - '--hierarchical', '--fno-inline', '-F t/t_hier_trace_sub/top.vc' -]) - -test.execute(all_run_flags=['-j 4']) - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_interface_ref_trace.py b/test_regress/t/t_interface_ref_trace.py deleted file mode 100755 index 9653f752c..000000000 --- a/test_regress/t/t_interface_ref_trace.py +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=['--trace-structs --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_interface_ref_trace_fst.py b/test_regress/t/t_interface_ref_trace_fst.py deleted file mode 100755 index 6010b9ac7..000000000 --- a/test_regress/t/t_interface_ref_trace_fst.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_interface_ref_trace.v" - -test.compile(verilator_flags2=['--trace-structs --trace-fst']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.py b/test_regress/t/t_interface_ref_trace_fst_sc.py deleted file mode 100755 index 66033f639..000000000 --- a/test_regress/t/t_interface_ref_trace_fst_sc.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_interface_ref_trace.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--trace-structs --trace-fst --sc']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) -test.passes() diff --git a/test_regress/t/t_interface_ref_trace_inla.py b/test_regress/t/t_interface_ref_trace_inla.py deleted file mode 100755 index 0dea85d0d..000000000 --- a/test_regress/t/t_interface_ref_trace_inla.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_interface_ref_trace.v" -test.golden_filename = "t/t_interface_ref_trace.out" - -test.compile(v_flags2=['+define+NO_INLINE_A'], verilator_flags2=['--trace-structs --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_interface_ref_trace_inlab.py b/test_regress/t/t_interface_ref_trace_inlab.py deleted file mode 100755 index 99bf3ce29..000000000 --- a/test_regress/t/t_interface_ref_trace_inlab.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_interface_ref_trace.v" -test.golden_filename = "t/t_interface_ref_trace.out" - -test.compile(v_flags2=['+define+NO_INLINE_A +define+NO_INLINE_B'], - verilator_flags2=['--trace-structs --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_interface_ref_trace_inlb.py b/test_regress/t/t_interface_ref_trace_inlb.py deleted file mode 100755 index cf60c2d4f..000000000 --- a/test_regress/t/t_interface_ref_trace_inlb.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_interface_ref_trace.v" -test.golden_filename = "t/t_interface_ref_trace.out" - -test.compile(v_flags2=['+define+NO_INLINE_B'], verilator_flags2=['--trace-structs --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_interface_ref_trace_noinl.out b/test_regress/t/t_interface_ref_trace_noinl.out deleted file mode 100644 index c46aa5d53..000000000 --- a/test_regress/t/t_interface_ref_trace_noinl.out +++ /dev/null @@ -1,674 +0,0 @@ -$version Generated by VerilatedVcd $end -$timescale 1ps $end - $scope module top $end - $var wire 1 0 clk $end - $scope module t $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $scope module intf_1 $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 $ value [31:0] $end - $scope module the_struct $end - $var wire 32 % val100 [31:0] $end - $var wire 32 & val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 1 value [31:0] $end - $upscope $end - $upscope $end - $scope module intf_2 $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 ' value [31:0] $end - $scope module the_struct $end - $var wire 32 ( val100 [31:0] $end - $var wire 32 ) val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 2 value [31:0] $end - $upscope $end - $upscope $end - $scope module s1 $end - $scope module intf_for_struct $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 $ value [31:0] $end - $scope module the_struct $end - $var wire 32 % val100 [31:0] $end - $var wire 32 & val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 1 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $scope module s2 $end - $scope module intf_for_struct $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 ' value [31:0] $end - $scope module the_struct $end - $var wire 32 ( val100 [31:0] $end - $var wire 32 ) val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 2 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $scope module c1 $end - $scope module intf_for_check $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 $ value [31:0] $end - $scope module the_struct $end - $var wire 32 % val100 [31:0] $end - $var wire 32 & val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 1 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $scope module c2 $end - $scope module intf_for_check $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 ' value [31:0] $end - $scope module the_struct $end - $var wire 32 ( val100 [31:0] $end - $var wire 32 ) val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 2 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $scope module a $end - $scope module intf_one $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 $ value [31:0] $end - $scope module the_struct $end - $var wire 32 % val100 [31:0] $end - $var wire 32 & val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 1 value [31:0] $end - $upscope $end - $upscope $end - $scope module intf_two $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 ' value [31:0] $end - $scope module the_struct $end - $var wire 32 ( val100 [31:0] $end - $var wire 32 ) val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 2 value [31:0] $end - $upscope $end - $upscope $end - $scope module intf_in_sub_all $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 * value [31:0] $end - $scope module the_struct $end - $var wire 32 + val100 [31:0] $end - $var wire 32 , val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 3 value [31:0] $end - $upscope $end - $upscope $end - $scope module ac1 $end - $scope module intf_for_check $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 $ value [31:0] $end - $scope module the_struct $end - $var wire 32 % val100 [31:0] $end - $var wire 32 & val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 1 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $scope module ac2 $end - $scope module intf_for_check $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 ' value [31:0] $end - $scope module the_struct $end - $var wire 32 ( val100 [31:0] $end - $var wire 32 ) val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 2 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $scope module as3 $end - $scope module intf_for_struct $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 * value [31:0] $end - $scope module the_struct $end - $var wire 32 + val100 [31:0] $end - $var wire 32 , val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 3 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $scope module ac3 $end - $scope module intf_for_check $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 * value [31:0] $end - $scope module the_struct $end - $var wire 32 + val100 [31:0] $end - $var wire 32 , val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 3 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module abcdefghijklmnopqrstuvwxyz $end - $scope module intf_one $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 ' value [31:0] $end - $scope module the_struct $end - $var wire 32 ( val100 [31:0] $end - $var wire 32 ) val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 2 value [31:0] $end - $upscope $end - $upscope $end - $scope module intf_two $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 $ value [31:0] $end - $scope module the_struct $end - $var wire 32 % val100 [31:0] $end - $var wire 32 & val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 1 value [31:0] $end - $upscope $end - $upscope $end - $scope module intf_in_sub_all $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 - value [31:0] $end - $scope module the_struct $end - $var wire 32 . val100 [31:0] $end - $var wire 32 / val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 4 value [31:0] $end - $upscope $end - $upscope $end - $scope module ac1 $end - $scope module intf_for_check $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 ' value [31:0] $end - $scope module the_struct $end - $var wire 32 ( val100 [31:0] $end - $var wire 32 ) val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 2 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $scope module ac2 $end - $scope module intf_for_check $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 $ value [31:0] $end - $scope module the_struct $end - $var wire 32 % val100 [31:0] $end - $var wire 32 & val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 1 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $scope module as3 $end - $scope module intf_for_struct $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 - value [31:0] $end - $scope module the_struct $end - $var wire 32 . val100 [31:0] $end - $var wire 32 / val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 4 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $scope module ac3 $end - $scope module intf_for_check $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 32 - value [31:0] $end - $scope module the_struct $end - $var wire 32 . val100 [31:0] $end - $var wire 32 / val200 [31:0] $end - $upscope $end - $scope module inner $end - $var wire 32 # cyc [31:0] $end - $var wire 32 4 value [31:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end -$enddefinitions $end - - -#0 -b00000000000000000000000000000000 # -b00000000000000000000000000000001 $ -b00000000000000000000000001100101 % -b00000000000000000000000011001001 & -b00000000000000000000000000000010 ' -b00000000000000000000000001100110 ( -b00000000000000000000000011001010 ) -b00000000000000000000001111101001 * -b00000000000000000000010001001101 + -b00000000000000000000010010110001 , -b00000000000000000000001111101010 - -b00000000000000000000010001001110 . -b00000000000000000000010010110010 / -00 -b00000000000000000000000000000000 1 -b00000000000000000000000000000000 2 -b00000000000000000000000000000000 3 -b00000000000000000000000000000000 4 -#10 -b00000000000000000000000000000001 # -b00000000000000000000000000000010 $ -b00000000000000000000000001100110 % -b00000000000000000000000011001010 & -b00000000000000000000000000000011 ' -b00000000000000000000000001100111 ( -b00000000000000000000000011001011 ) -b00000000000000000000001111101010 * -b00000000000000000000010001001110 + -b00000000000000000000010010110010 , -b00000000000000000000001111101011 - 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-b00000000000000000000010001011010 . -b00000000000000000000010010111110 / -10 -#125 -00 -#130 -b00000000000000000000000000001101 # -b00000000000000000000000000001110 $ -b00000000000000000000000001110010 % -b00000000000000000000000011010110 & -b00000000000000000000000000001111 ' -b00000000000000000000000001110011 ( -b00000000000000000000000011010111 ) -b00000000000000000000001111110110 * -b00000000000000000000010001011010 + -b00000000000000000000010010111110 , -b00000000000000000000001111110111 - -b00000000000000000000010001011011 . -b00000000000000000000010010111111 / -10 -#135 -00 -#140 -b00000000000000000000000000001110 # -b00000000000000000000000000001111 $ -b00000000000000000000000001110011 % -b00000000000000000000000011010111 & -b00000000000000000000000000010000 ' -b00000000000000000000000001110100 ( -b00000000000000000000000011011000 ) -b00000000000000000000001111110111 * -b00000000000000000000010001011011 + -b00000000000000000000010010111111 , -b00000000000000000000001111111000 - -b00000000000000000000010001011100 . -b00000000000000000000010011000000 / -10 -#145 -00 -#150 -b00000000000000000000000000001111 # -b00000000000000000000000000010000 $ -b00000000000000000000000001110100 % -b00000000000000000000000011011000 & -b00000000000000000000000000010001 ' -b00000000000000000000000001110101 ( -b00000000000000000000000011011001 ) -b00000000000000000000001111111000 * -b00000000000000000000010001011100 + -b00000000000000000000010011000000 , -b00000000000000000000001111111001 - -b00000000000000000000010001011101 . -b00000000000000000000010011000001 / -10 -#155 -00 -#160 -b00000000000000000000000000010000 # -b00000000000000000000000000010001 $ -b00000000000000000000000001110101 % -b00000000000000000000000011011001 & -b00000000000000000000000000010010 ' -b00000000000000000000000001110110 ( -b00000000000000000000000011011010 ) -b00000000000000000000001111111001 * -b00000000000000000000010001011101 + -b00000000000000000000010011000001 , -b00000000000000000000001111111010 - -b00000000000000000000010001011110 . -b00000000000000000000010011000010 / -10 -#165 -00 -#170 -b00000000000000000000000000010001 # -b00000000000000000000000000010010 $ -b00000000000000000000000001110110 % -b00000000000000000000000011011010 & -b00000000000000000000000000010011 ' -b00000000000000000000000001110111 ( -b00000000000000000000000011011011 ) -b00000000000000000000001111111010 * -b00000000000000000000010001011110 + -b00000000000000000000010011000010 , -b00000000000000000000001111111011 - -b00000000000000000000010001011111 . -b00000000000000000000010011000011 / -10 -#175 -00 -#180 -b00000000000000000000000000010010 # -b00000000000000000000000000010011 $ -b00000000000000000000000001110111 % -b00000000000000000000000011011011 & -b00000000000000000000000000010100 ' -b00000000000000000000000001111000 ( -b00000000000000000000000011011100 ) -b00000000000000000000001111111011 * -b00000000000000000000010001011111 + -b00000000000000000000010011000011 , -b00000000000000000000001111111100 - -b00000000000000000000010001100000 . -b00000000000000000000010011000100 / -10 -#185 -00 -#190 -b00000000000000000000000000010011 # -b00000000000000000000000000010100 $ -b00000000000000000000000001111000 % -b00000000000000000000000011011100 & -b00000000000000000000000000010101 ' -b00000000000000000000000001111001 ( -b00000000000000000000000011011101 ) -b00000000000000000000001111111100 * -b00000000000000000000010001100000 + -b00000000000000000000010011000100 , -b00000000000000000000001111111101 - -b00000000000000000000010001100001 . -b00000000000000000000010011000101 / -10 -#195 -00 -#200 -b00000000000000000000000000010100 # -b00000000000000000000000000010101 $ -b00000000000000000000000001111001 % -b00000000000000000000000011011101 & -b00000000000000000000000000010110 ' -b00000000000000000000000001111010 ( -b00000000000000000000000011011110 ) -b00000000000000000000001111111101 * -b00000000000000000000010001100001 + -b00000000000000000000010011000101 , -b00000000000000000000001111111110 - -b00000000000000000000010001100010 . -b00000000000000000000010011000110 / -10 -#205 -00 -#210 -b00000000000000000000000000010101 # -b00000000000000000000000000010110 $ -b00000000000000000000000001111010 % -b00000000000000000000000011011110 & -b00000000000000000000000000010111 ' -b00000000000000000000000001111011 ( -b00000000000000000000000011011111 ) -b00000000000000000000001111111110 * -b00000000000000000000010001100010 + -b00000000000000000000010011000110 , -b00000000000000000000001111111111 - -b00000000000000000000010001100011 . -b00000000000000000000010011000111 / -10 diff --git a/test_regress/t/t_interface_ref_trace_noinl.py b/test_regress/t/t_interface_ref_trace_noinl.py deleted file mode 100755 index 537d3408e..000000000 --- a/test_regress/t/t_interface_ref_trace_noinl.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_interface_ref_trace.v" -# Should be the same as the inlined version, but might have declarations -# in a different order. Sadly vcddiff can't check equivalence -# test.golden_filename = "t/t_interface_ref_trace.out" - -test.compile(verilator_flags2=['-fno-inline --trace-structs --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_interface_ref_trace_noinl_notrace.py b/test_regress/t/t_interface_ref_trace_noinl_notrace.py deleted file mode 100755 index 9e768b778..000000000 --- a/test_regress/t/t_interface_ref_trace_noinl_notrace.py +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_interface_ref_trace.v" - -test.compile(verilator_flags2=['-fno-inline']) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_interface_ref_trace_saif.py b/test_regress/t/t_interface_ref_trace_saif.py deleted file mode 100755 index 8ed547ac1..000000000 --- a/test_regress/t/t_interface_ref_trace_saif.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_interface_ref_trace.v" -test.golden_filename = "t/t_interface_ref_trace_saif.out" - -test.compile(verilator_flags2=['--trace-structs --trace-saif']) - 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under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary --trace-vcd -Wno-MINTYPMAXDLY"]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_timing_trace_fst.py b/test_regress/t/t_timing_trace_fst.py deleted file mode 100755 index 9e3c60240..000000000 --- a/test_regress/t/t_timing_trace_fst.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_timing_trace.v" - -test.compile(verilator_flags2=["--binary --trace-fst -Wno-MINTYPMAXDLY"]) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_timing_trace_saif.py b/test_regress/t/t_timing_trace_saif.py deleted file mode 100755 index d4db413f3..000000000 --- a/test_regress/t/t_timing_trace_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_timing_trace.v" - -test.compile(verilator_flags2=["--exe --main --timing --trace-saif -Wno-MINTYPMAXDLY"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_abort.py b/test_regress/t/t_trace_abort.py deleted file mode 100755 index 2ce07b064..000000000 --- a/test_regress/t/t_trace_abort.py +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.compile(verilator_flags2=['--cc --trace-vcd']) - -test.execute(fails=True) - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_abort_fst.out b/test_regress/t/t_trace_abort_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_abort_fst.out rename to test_regress/t/t_trace_abort_cc_fst.out diff --git a/test_regress/t/t_trace_abort_cc_fst.py b/test_regress/t/t_trace_abort_cc_fst.py new file mode 100755 index 000000000..a6ad9fbef --- /dev/null +++ b/test_regress/t/t_trace_abort_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_abort_common + +test.scenarios('vlt_all') + +trace_abort_common.run(test) diff --git a/test_regress/t/t_trace_abort_saif.out b/test_regress/t/t_trace_abort_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_abort_saif.out rename to test_regress/t/t_trace_abort_cc_saif.out diff --git a/test_regress/t/t_trace_abort_cc_saif.py b/test_regress/t/t_trace_abort_cc_saif.py new file mode 100755 index 000000000..a6ad9fbef --- /dev/null +++ b/test_regress/t/t_trace_abort_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_abort_common + +test.scenarios('vlt_all') + +trace_abort_common.run(test) diff --git a/test_regress/t/t_trace_abort.out b/test_regress/t/t_trace_abort_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_abort.out rename to test_regress/t/t_trace_abort_cc_vcd.out diff --git a/test_regress/t/t_trace_abort_cc_vcd.py b/test_regress/t/t_trace_abort_cc_vcd.py new file mode 100755 index 000000000..a6ad9fbef --- /dev/null +++ b/test_regress/t/t_trace_abort_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_abort_common + +test.scenarios('vlt_all') + +trace_abort_common.run(test) diff --git a/test_regress/t/t_trace_abort_fst.py b/test_regress/t/t_trace_abort_fst.py deleted file mode 100755 index 86cb92b46..000000000 --- a/test_regress/t/t_trace_abort_fst.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t/t_trace_abort.v" - -test.compile(verilator_flags2=['--cc --trace-fst']) - -test.execute(fails=True) - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_abort_fst_sc.py b/test_regress/t/t_trace_abort_fst_sc.py deleted file mode 100755 index 11117a842..000000000 --- a/test_regress/t/t_trace_abort_fst_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t/t_trace_abort.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-fst']) - -test.execute(fails=True) - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_abort_saif.py b/test_regress/t/t_trace_abort_saif.py deleted file mode 100755 index 3d5f8c1dd..000000000 --- a/test_regress/t/t_trace_abort_saif.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t/t_trace_abort.v" -test.golden_filename = "t/t_trace_abort_saif.out" - -test.compile(verilator_flags2=['--cc --trace-saif']) - -test.execute(fails=True) - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_abort_fst_sc.out b/test_regress/t/t_trace_abort_sc_fst.out similarity index 100% rename from test_regress/t/t_trace_abort_fst_sc.out rename to test_regress/t/t_trace_abort_sc_fst.out diff --git a/test_regress/t/t_trace_abort_sc_fst.py b/test_regress/t/t_trace_abort_sc_fst.py new file mode 100755 index 000000000..a6ad9fbef --- /dev/null +++ b/test_regress/t/t_trace_abort_sc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_abort_common + +test.scenarios('vlt_all') + +trace_abort_common.run(test) diff --git a/test_regress/t/t_trace_array.py b/test_regress/t/t_trace_array.py deleted file mode 100755 index 5a6c2da8b..000000000 --- a/test_regress/t/t_trace_array.py +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=['--cc --trace-vcd --trace-structs --trace-max-width 0']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_fst.out b/test_regress/t/t_trace_array_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_array_fst.out rename to test_regress/t/t_trace_array_cc_fst.out diff --git a/test_regress/t/t_trace_array_cc_fst.py b/test_regress/t/t_trace_array_cc_fst.py new file mode 100755 index 000000000..499943a69 --- /dev/null +++ b/test_regress/t/t_trace_array_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test) diff --git a/test_regress/t/t_trace_array_cc_fst_portable.py b/test_regress/t/t_trace_array_cc_fst_portable.py new file mode 100755 index 000000000..95435ce0e --- /dev/null +++ b/test_regress/t/t_trace_array_cc_fst_portable.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"]) diff --git a/test_regress/t/t_trace_array_cc_fst_threads_1.py b/test_regress/t/t_trace_array_cc_fst_threads_1.py new file mode 100755 index 000000000..65d3ec5da --- /dev/null +++ b/test_regress/t/t_trace_array_cc_fst_threads_1.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_array_cc_fst_threads_2.py b/test_regress/t/t_trace_array_cc_fst_threads_2.py new file mode 100755 index 000000000..233ae9130 --- /dev/null +++ b/test_regress/t/t_trace_array_cc_fst_threads_2.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test, verilator_flags2=["--trace-threads", "2"]) diff --git a/test_regress/t/t_trace_array_saif.out b/test_regress/t/t_trace_array_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_array_saif.out rename to test_regress/t/t_trace_array_cc_saif.out diff --git a/test_regress/t/t_trace_array_cc_saif.py b/test_regress/t/t_trace_array_cc_saif.py new file mode 100755 index 000000000..499943a69 --- /dev/null +++ b/test_regress/t/t_trace_array_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test) diff --git a/test_regress/t/t_trace_array_cc_saif_portable.py b/test_regress/t/t_trace_array_cc_saif_portable.py new file mode 100755 index 000000000..95435ce0e --- /dev/null +++ b/test_regress/t/t_trace_array_cc_saif_portable.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"]) diff --git a/test_regress/t/t_trace_array_cc_saif_threads_1.py b/test_regress/t/t_trace_array_cc_saif_threads_1.py new file mode 100755 index 000000000..65d3ec5da --- /dev/null +++ b/test_regress/t/t_trace_array_cc_saif_threads_1.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_array.out b/test_regress/t/t_trace_array_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_array.out rename to test_regress/t/t_trace_array_cc_vcd.out diff --git a/test_regress/t/t_trace_array_cc_vcd.py b/test_regress/t/t_trace_array_cc_vcd.py new file mode 100755 index 000000000..499943a69 --- /dev/null +++ b/test_regress/t/t_trace_array_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test) diff --git a/test_regress/t/t_trace_array_cc_vcd_threads_1.py b/test_regress/t/t_trace_array_cc_vcd_threads_1.py new file mode 100755 index 000000000..65d3ec5da --- /dev/null +++ b/test_regress/t/t_trace_array_cc_vcd_threads_1.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_array_fst.py b/test_regress/t/t_trace_array_fst.py deleted file mode 100755 index 9d4d511f1..000000000 --- a/test_regress/t/t_trace_array_fst.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" - -test.compile(verilator_flags2=['--cc --trace-fst --trace-structs --trace-max-width 0']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_fst_portable.py b/test_regress/t/t_trace_array_fst_portable.py deleted file mode 100755 index ad8ce0000..000000000 --- a/test_regress/t/t_trace_array_fst_portable.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst.out" - -test.compile(verilator_flags2=[ - '--cc --trace-fst --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY' -]) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_fst_portable_sc.py b/test_regress/t/t_trace_array_fst_portable_sc.py deleted file mode 100755 index c7fa01c2e..000000000 --- a/test_regress/t/t_trace_array_fst_portable_sc.py +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst_sc.out" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=[ - '--sc --trace-fst --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY' -]) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_fst_sc.py b/test_regress/t/t_trace_array_fst_sc.py deleted file mode 100755 index ade50f8f3..000000000 --- a/test_regress/t/t_trace_array_fst_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-fst --trace-structs --trace-max-width 0']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_1.py b/test_regress/t/t_trace_array_fst_threads_1.py deleted file mode 100755 index 9850941a4..000000000 --- a/test_regress/t/t_trace_array_fst_threads_1.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst.out" - -test.compile( - verilator_flags2=['--cc --trace-fst --trace-threads 1 --trace-structs --trace-max-width 0']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_1_sc.py b/test_regress/t/t_trace_array_fst_threads_1_sc.py deleted file mode 100755 index d1288dc04..000000000 --- a/test_regress/t/t_trace_array_fst_threads_1_sc.py +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst_sc.out" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile( - verilator_flags2=['--sc --trace-fst --trace-threads 1 --trace-structs --trace-max-width 0']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_2.py b/test_regress/t/t_trace_array_fst_threads_2.py deleted file mode 100755 index bcd82d977..000000000 --- a/test_regress/t/t_trace_array_fst_threads_2.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst.out" - -test.compile( - verilator_flags2=['--cc --trace-fst --trace-threads 2 --trace-structs --trace-max-width 0']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_fst_threads_2_sc.py b/test_regress/t/t_trace_array_fst_threads_2_sc.py deleted file mode 100755 index ba21ee799..000000000 --- a/test_regress/t/t_trace_array_fst_threads_2_sc.py +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_fst_sc.out" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile( - verilator_flags2=['--sc --trace-fst --trace-threads 2 --trace-structs --trace-max-width 0']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_saif.py b/test_regress/t/t_trace_array_saif.py deleted file mode 100755 index 971a83073..000000000 --- a/test_regress/t/t_trace_array_saif.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_saif.out" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --trace-max-width 0']) - -test.execute() - -# saif_identical is very slow, so require exact match -test.files_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_saif_portable.py b/test_regress/t/t_trace_array_saif_portable.py deleted file mode 100755 index 83f1a69e1..000000000 --- a/test_regress/t/t_trace_array_saif_portable.py +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_saif.out" - -# Don't pass --trace-max-width 0, we shrink the file intentionally -test.compile(verilator_flags2=[ - '--cc --trace-saif --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY' -]) - -test.execute() - -# saif_identical is very slow, so require exact match -test.files_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_saif_threads_1.py b/test_regress/t/t_trace_array_saif_threads_1.py deleted file mode 100755 index 578dea917..000000000 --- a/test_regress/t/t_trace_array_saif_threads_1.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_saif.out" - -test.compile( - verilator_flags2=['--cc --trace-saif --trace-threads 1 --trace-structs --trace-max-width 0']) - -test.execute() - -# saif_identical is very slow, so require exact match -test.files_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_saif_threads_2.py b/test_regress/t/t_trace_array_saif_threads_2.py deleted file mode 100755 index a021561be..000000000 --- a/test_regress/t/t_trace_array_saif_threads_2.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array_saif.out" - -test.compile( - verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs --trace-max-width 0']) - -test.execute() - -# saif_identical is very slow, so require exact match -test.files_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_array_fst_sc.out b/test_regress/t/t_trace_array_sc_fst.out similarity index 100% rename from test_regress/t/t_trace_array_fst_sc.out rename to test_regress/t/t_trace_array_sc_fst.out diff --git a/test_regress/t/t_trace_array_sc_fst.py b/test_regress/t/t_trace_array_sc_fst.py new file mode 100755 index 000000000..499943a69 --- /dev/null +++ b/test_regress/t/t_trace_array_sc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test) diff --git a/test_regress/t/t_trace_array_sc_fst_portable.py b/test_regress/t/t_trace_array_sc_fst_portable.py new file mode 100755 index 000000000..95435ce0e --- /dev/null +++ b/test_regress/t/t_trace_array_sc_fst_portable.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"]) diff --git a/test_regress/t/t_trace_array_sc_fst_threads_1.py b/test_regress/t/t_trace_array_sc_fst_threads_1.py new file mode 100755 index 000000000..65d3ec5da --- /dev/null +++ b/test_regress/t/t_trace_array_sc_fst_threads_1.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_array_sc_fst_threads_2.py b/test_regress/t/t_trace_array_sc_fst_threads_2.py new file mode 100755 index 000000000..233ae9130 --- /dev/null +++ b/test_regress/t/t_trace_array_sc_fst_threads_2.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_array_common + +test.scenarios('vlt_all') + +trace_array_common.run(test, verilator_flags2=["--trace-threads", "2"]) diff --git a/test_regress/t/t_trace_array_threads_1.py b/test_regress/t/t_trace_array_threads_1.py deleted file mode 100755 index 7a46dccae..000000000 --- a/test_regress/t/t_trace_array_threads_1.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_array.v" -test.golden_filename = "t/t_trace_array.out" - -test.compile( - verilator_flags2=['--cc --trace-vcd --trace-threads 1 --trace-structs --trace-max-width 0']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_ascendingrange.py b/test_regress/t/t_trace_ascendingrange.py deleted file mode 100755 index 13da9fc7d..000000000 --- a/test_regress/t/t_trace_ascendingrange.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# Strangely, asking for more threads makes it go away. -test.compile(verilator_flags2=['--cc --trace-vcd --trace-params -Wno-ASCRANGE'], - threads=(6 if test.vltmt else 1)) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_ascendingrange_fst.out b/test_regress/t/t_trace_ascendingrange_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_ascendingrange_fst.out rename to test_regress/t/t_trace_ascendingrange_cc_fst.out diff --git a/test_regress/t/t_trace_ascendingrange_cc_fst.py b/test_regress/t/t_trace_ascendingrange_cc_fst.py new file mode 100755 index 000000000..41bbbddf8 --- /dev/null +++ b/test_regress/t/t_trace_ascendingrange_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_ascendingrange_common + +test.scenarios('vlt_all') + +trace_ascendingrange_common.run(test) diff --git a/test_regress/t/t_trace_ascendingrange_saif.out b/test_regress/t/t_trace_ascendingrange_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_ascendingrange_saif.out rename to test_regress/t/t_trace_ascendingrange_cc_saif.out diff --git a/test_regress/t/t_trace_ascendingrange_cc_saif.py b/test_regress/t/t_trace_ascendingrange_cc_saif.py new file mode 100755 index 000000000..41bbbddf8 --- /dev/null +++ b/test_regress/t/t_trace_ascendingrange_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_ascendingrange_common + +test.scenarios('vlt_all') + +trace_ascendingrange_common.run(test) diff --git a/test_regress/t/t_trace_ascendingrange.out b/test_regress/t/t_trace_ascendingrange_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_ascendingrange.out rename to test_regress/t/t_trace_ascendingrange_cc_vcd.out diff --git a/test_regress/t/t_trace_ascendingrange_cc_vcd.py b/test_regress/t/t_trace_ascendingrange_cc_vcd.py new file mode 100755 index 000000000..41bbbddf8 --- /dev/null +++ b/test_regress/t/t_trace_ascendingrange_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_ascendingrange_common + +test.scenarios('vlt_all') + +trace_ascendingrange_common.run(test) diff --git a/test_regress/t/t_trace_ascendingrange_fst.py b/test_regress/t/t_trace_ascendingrange_fst.py deleted file mode 100755 index f9aeccc2c..000000000 --- a/test_regress/t/t_trace_ascendingrange_fst.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_ascendingrange.v" - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# Strangely, asking for more threads makes it go away. -test.compile(verilator_flags2=['--cc --trace-fst --trace-params -Wno-ASCRANGE'], - threads=(6 if test.vltmt else 1)) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_ascendingrange_fst_sc.py b/test_regress/t/t_trace_ascendingrange_fst_sc.py deleted file mode 100755 index ca8083273..000000000 --- a/test_regress/t/t_trace_ascendingrange_fst_sc.py +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_ascendingrange.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# Strangely, asking for more threads makes it go away. -test.compile(verilator_flags2=['--sc --trace-fst --trace-params -Wno-ASCRANGE'], - threads=(6 if test.vltmt else 1)) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_ascendingrange_saif.py b/test_regress/t/t_trace_ascendingrange_saif.py deleted file mode 100755 index 31d24956a..000000000 --- a/test_regress/t/t_trace_ascendingrange_saif.py +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_ascendingrange.v" -test.golden_filename = "t/t_trace_ascendingrange_saif.out" - -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# Strangely, asking for more threads makes it go away. -test.compile(verilator_flags2=['--cc --trace-saif --trace-params -Wno-ASCRANGE'], - threads=(6 if test.vltmt else 1)) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_ascendingrange_fst_sc.out b/test_regress/t/t_trace_ascendingrange_sc_fst.out similarity index 100% rename from test_regress/t/t_trace_ascendingrange_fst_sc.out rename to test_regress/t/t_trace_ascendingrange_sc_fst.out diff --git a/test_regress/t/t_trace_ascendingrange_sc_fst.py b/test_regress/t/t_trace_ascendingrange_sc_fst.py new file mode 100755 index 000000000..41bbbddf8 --- /dev/null +++ b/test_regress/t/t_trace_ascendingrange_sc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_ascendingrange_common + +test.scenarios('vlt_all') + +trace_ascendingrange_common.run(test) diff --git a/test_regress/t/t_trace_fst.v b/test_regress/t/t_trace_basic.v similarity index 93% rename from test_regress/t/t_trace_fst.v rename to test_regress/t/t_trace_basic.v index ddc6af821..c43b5b656 100644 --- a/test_regress/t/t_trace_fst.v +++ b/test_regress/t/t_trace_basic.v @@ -4,20 +4,26 @@ // SPDX-FileCopyrightText: 2018 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 -module t ( /*AUTOARG*/ - // Outputs - state, - // Inouts - fst_inout, - // Inputs +module t ( clk +`ifndef SYSTEMC + ,fst_inout + ,state +`endif ); input clk; +`ifndef SYSTEMC + output state; + inout fst_inout; +`endif + + wire clk; + wire [4:0] state; + wire fst_inout; int cyc; reg rstn; - output [4:0] state; parameter real fst_gparam_real = 1.23; localparam real fst_lparam_real = 4.56; @@ -45,7 +51,6 @@ module t ( /*AUTOARG*/ wor fst_wor; wire fst_wire; uwire fst_uwire; - inout fst_inout; Test test ( /*AUTOINST*/ // Outputs diff --git a/test_regress/t/t_trace_fst.out b/test_regress/t/t_trace_basic_cc_fst.out similarity index 99% rename from test_regress/t/t_trace_fst.out rename to test_regress/t/t_trace_basic_cc_fst.out index 9544822be..162ce3ec0 100644 --- a/test_regress/t/t_trace_fst.out +++ b/test_regress/t/t_trace_basic_cc_fst.out @@ -1,5 +1,5 @@ $date - Tue Feb 17 01:32:42 2026 + Thu Mar 12 09:10:51 2026 $end $version @@ -14,9 +14,10 @@ $var wire 5 " state [4:0] $end $var wire 1 # fst_inout $end $scope module t $end $var wire 1 ! clk $end +$var wire 5 " state [4:0] $end +$var wire 1 # fst_inout $end $var int 32 $ cyc [31:0] $end $var logic 1 % rstn $end -$var wire 5 " state [4:0] $end $var real_parameter 64 & fst_gparam_real $end $var real_parameter 64 ' fst_lparam_real $end $var real 64 & fst_real $end @@ -41,7 +42,6 @@ $var triand 1 6 fst_wand $end $var trior 1 7 fst_wor $end $var wire 1 8 fst_wire $end $var wire 1 9 fst_uwire $end -$var wire 1 # fst_inout $end $scope module test $end $var wire 1 ! clk $end $var wire 1 % rstn $end diff --git a/test_regress/t/t_trace_basic_cc_fst.py b/test_regress/t/t_trace_basic_cc_fst.py new file mode 100755 index 000000000..a95b13c4a --- /dev/null +++ b/test_regress/t/t_trace_basic_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_cc_fst_cmake.py b/test_regress/t/t_trace_basic_cc_fst_cmake.py new file mode 100755 index 000000000..fa52fde4c --- /dev/null +++ b/test_regress/t/t_trace_basic_cc_fst_cmake.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_saif.out b/test_regress/t/t_trace_basic_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_saif.out rename to test_regress/t/t_trace_basic_cc_saif.out index a2f83dfc1..69ee93d2d 100644 --- a/test_regress/t/t_trace_saif.out +++ b/test_regress/t/t_trace_basic_cc_saif.out @@ -19,6 +19,12 @@ (INSTANCE t (NET (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) + (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) + (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) (cyc\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) (cyc\[2\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25)) @@ -52,11 +58,6 @@ (cyc\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) - (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) - (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) - (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (fst_gparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) @@ -542,7 +543,6 @@ (fst_wor (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_uwire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE test (NET diff --git a/test_regress/t/t_trace_basic_cc_saif.py b/test_regress/t/t_trace_basic_cc_saif.py new file mode 100755 index 000000000..a95b13c4a --- /dev/null +++ b/test_regress/t/t_trace_basic_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_cc_saif_cmake.py b/test_regress/t/t_trace_basic_cc_saif_cmake.py new file mode 100755 index 000000000..fa52fde4c --- /dev/null +++ b/test_regress/t/t_trace_basic_cc_saif_cmake.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_basic_cc_vcd.out b/test_regress/t/t_trace_basic_cc_vcd.out new file mode 100644 index 000000000..8c62a5081 --- /dev/null +++ b/test_regress/t/t_trace_basic_cc_vcd.out @@ -0,0 +1,1124 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 & clk $end + $var wire 5 ' state [4:0] $end + $var wire 1 , fst_inout $end + $scope module t $end + $var wire 1 & clk $end + $var wire 5 ' state [4:0] $end + $var wire 1 , fst_inout $end + $var wire 32 ( cyc [31:0] $end + $var wire 1 ) rstn $end + $var real 64 - fst_gparam_real $end + $var real 64 / fst_lparam_real $end + $var real 64 - fst_real $end + $var wire 32 1 fst_integer [31:0] $end + $var wire 1 2 fst_bit $end + $var wire 1 3 fst_logic $end + $var wire 32 4 fst_int [31:0] $end + $var wire 16 5 fst_shortint [15:0] $end + $var wire 64 6 fst_longint [63:0] $end + $var wire 8 8 fst_byte [7:0] $end + $var wire 64 * fst_time [63:0] $end + $var wire 32 9 fst_parameter [31:0] $end + $var wire 32 : fst_lparam [31:0] $end + $var wire 1 , fst_supply0 $end + $var wire 1 ; fst_supply1 $end + $var wire 1 , fst_tri0 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+b01101 % +1& +b11101 ' +b00000000000000000000000001100001 ( +b0000000000000000000000000000000000000000000000000000001111001010 * +#975 +0& +#980 +b01001 " +b11010 # +b01101 $ +b10010 % +1& +b11010 ' +b00000000000000000000000001100010 ( +b0000000000000000000000000000000000000000000000000000001111010100 * +#985 +0& +#990 +b10000 " +b01101 # +b10010 $ +b01001 % +1& +b01101 ' +b00000000000000000000000001100011 ( +b0000000000000000000000000000000000000000000000000000001111011110 * +#995 +0& +#1000 +b01000 " +b10010 # +b01001 $ +b10000 % +1& +b10010 ' +b00000000000000000000000001100100 ( +b0000000000000000000000000000000000000000000000000000001111101000 * diff --git a/test_regress/t/t_trace_basic_cc_vcd.py b/test_regress/t/t_trace_basic_cc_vcd.py new file mode 100755 index 000000000..a95b13c4a --- /dev/null +++ b/test_regress/t/t_trace_basic_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_cc_vcd_cmake.py b/test_regress/t/t_trace_basic_cc_vcd_cmake.py new file mode 100755 index 000000000..fa52fde4c --- /dev/null +++ b/test_regress/t/t_trace_basic_cc_vcd_cmake.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_basic_sc_fst.out b/test_regress/t/t_trace_basic_sc_fst.out new file mode 100644 index 000000000..1f6fe9a66 --- /dev/null +++ b/test_regress/t/t_trace_basic_sc_fst.out @@ -0,0 +1,1131 @@ +$date + Thu Mar 12 09:11:07 2026 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var wire 5 " state [4:0] $end +$var wire 1 # fst_inout $end +$var int 32 $ cyc [31:0] $end +$var logic 1 % rstn $end +$var real_parameter 64 & fst_gparam_real $end +$var real_parameter 64 ' fst_lparam_real $end +$var real 64 & fst_real $end +$var integer 32 ( fst_integer [31:0] $end +$var bit 1 ) fst_bit $end +$var logic 1 * fst_logic $end +$var int 32 + fst_int [31:0] $end +$var shortint 16 , fst_shortint [15:0] $end +$var longint 64 - fst_longint [63:0] $end +$var byte 8 . fst_byte [7:0] $end +$var time 64 / fst_time [63:0] $end +$var parameter 32 0 fst_parameter [31:0] $end +$var parameter 32 1 fst_lparam [31:0] $end +$var supply0 1 2 fst_supply0 $end +$var supply1 1 3 fst_supply1 $end +$var tri0 1 2 fst_tri0 $end +$var tri1 1 3 fst_tri1 $end +$var tri 1 4 fst_tri $end +$var triand 1 5 fst_triand $end +$var trior 1 6 fst_trior $end +$var triand 1 7 fst_wand $end +$var trior 1 8 fst_wor $end +$var wire 1 9 fst_wire $end +$var wire 1 : fst_uwire $end +$scope module test $end +$var wire 1 ! clk $end +$var wire 1 % rstn $end +$var wire 5 " state [4:0] $end +$var logic 5 ; state_w [4:0] $end +$var logic 5 < state_array[0] [4:0] $end +$var logic 5 = state_array[1] [4:0] $end +$var logic 5 > state_array[2] [4:0] $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b00000 > +b00000 = +b00000 < +b00000 ; +0: +09 +08 +07 +06 +05 +04 +13 +02 +b00000000000000000000000111001000 1 +b00000000000000000000000001111011 0 +b0000000000000000000000000000000000000000000000000000000000000000 / +b00000000 . +b0000000000000000000000000000000000000000000000000000000000000000 - +b0000000000000000 , +b00000000000000000000000000000000 + +0* +0) +b00000000000000000000000000000000 ( +r4.56 ' +r1.23 & +0% +b00000000000000000000000000000000 $ +0# +b00000 " +0! +$end +#10 +1! +b00001 " +b00000000000000000000000000000001 $ +b0000000000000000000000000000000000000000000000000000000000001010 / +b10100 ; +b00001 < +b00001 = +b00001 > +#15 +0! +#20 +1! +b0000000000000000000000000000000000000000000000000000000000010100 / +b00000000000000000000000000000010 $ +#25 +0! +#30 +1! +b00000000000000000000000000000011 $ +b0000000000000000000000000000000000000000000000000000000000011110 / +#35 +0! +#40 +1! +b0000000000000000000000000000000000000000000000000000000000101000 / +b00000000000000000000000000000100 $ +#45 +0! +#50 +1! +b00000000000000000000000000000101 $ +b0000000000000000000000000000000000000000000000000000000000110010 / +#55 +0! +#60 +1! +b0000000000000000000000000000000000000000000000000000000000111100 / +b00000000000000000000000000000110 $ +#65 +0! +#70 +1! +b00000000000000000000000000000111 $ +b0000000000000000000000000000000000000000000000000000000001000110 / +#75 +0! +#80 +1! +b0000000000000000000000000000000000000000000000000000000001010000 / +b00000000000000000000000000001000 $ +#85 +0! +#90 +1! +b00000000000000000000000000001001 $ +b0000000000000000000000000000000000000000000000000000000001011010 / +#95 +0! +#100 +1! +b0000000000000000000000000000000000000000000000000000000001100100 / +b00000000000000000000000000001010 $ +#105 +0! +#110 +1! +b00000000000000000000000000001011 $ +b0000000000000000000000000000000000000000000000000000000001101110 / +1% +#115 +0! +#120 +1! +b0000000000000000000000000000000000000000000000000000000001111000 / +b00000000000000000000000000001100 $ +b10100 > +b01010 ; +#125 +0! +#130 +1! +b00101 ; +b01010 > +b00000000000000000000000000001101 $ +b0000000000000000000000000000000000000000000000000000000010000010 / +b10100 = +#135 +0! +#140 +1! +b01010 = +b0000000000000000000000000000000000000000000000000000000010001100 / +b00000000000000000000000000001110 $ +b00101 > +b10110 ; +b10100 < +b10100 " +#145 +0! +#150 +1! +b01010 " +b01010 < +b01011 ; +b10110 > +b00000000000000000000000000001111 $ +b0000000000000000000000000000000000000000000000000000000010010110 / +b00101 = +#155 +0! +#160 +1! +b10110 = +b0000000000000000000000000000000000000000000000000000000010100000 / +b00000000000000000000000000010000 $ +b01011 > +b10001 ; +b00101 < +b00101 " +#165 +0! +#170 +1! +b10110 " +b10110 < +b11100 ; +b10001 > +b00000000000000000000000000010001 $ +b0000000000000000000000000000000000000000000000000000000010101010 / +b01011 = +#175 +0! +#180 +1! +b10001 = +b0000000000000000000000000000000000000000000000000000000010110100 / +b00000000000000000000000000010010 $ +b11100 > +b01110 ; +b01011 < +b01011 " +#185 +0! +#190 +1! +b10001 " +b10001 < +b00111 ; +b01110 > +b00000000000000000000000000010011 $ +b0000000000000000000000000000000000000000000000000000000010111110 / +b11100 = +#195 +0! +#200 +1! +b01110 = +b0000000000000000000000000000000000000000000000000000000011001000 / +b00000000000000000000000000010100 $ +b00111 > +b10111 ; +b11100 < +b11100 " +#205 +0! +#210 +1! +b01110 " +b01110 < +b11111 ; +b10111 > +b00000000000000000000000000010101 $ +b0000000000000000000000000000000000000000000000000000000011010010 / +b00111 = +#215 +0! +#220 +1! +b10111 = +b0000000000000000000000000000000000000000000000000000000011011100 / +b00000000000000000000000000010110 $ +b11111 > +b11011 ; +b00111 < +b00111 " +#225 +0! +#230 +1! +b10111 " +b10111 < +b11001 ; +b11011 > +b00000000000000000000000000010111 $ +b0000000000000000000000000000000000000000000000000000000011100110 / +b11111 = +#235 +0! +#240 +1! +b11011 = +b0000000000000000000000000000000000000000000000000000000011110000 / +b00000000000000000000000000011000 $ +b11001 > +b11000 ; +b11111 < +b11111 " +#245 +0! +#250 +1! +b11011 " +b11011 < +b01100 ; +b11000 > +b00000000000000000000000000011001 $ +b0000000000000000000000000000000000000000000000000000000011111010 / +b11001 = +#255 +0! +#260 +1! +b11000 = +b0000000000000000000000000000000000000000000000000000000100000100 / +b00000000000000000000000000011010 $ +b01100 > +b00110 ; +b11001 < +b11001 " +#265 +0! +#270 +1! +b11000 " +b11000 < +b00011 ; +b00110 > +b00000000000000000000000000011011 $ +b0000000000000000000000000000000000000000000000000000000100001110 / +b01100 = +#275 +0! +#280 +1! +b00110 = +b0000000000000000000000000000000000000000000000000000000100011000 / +b00000000000000000000000000011100 $ +b00011 > +b10101 ; +b01100 < +b01100 " +#285 +0! +#290 +1! +b00110 " +b00110 < +b11110 ; +b10101 > +b00000000000000000000000000011101 $ +b0000000000000000000000000000000000000000000000000000000100100010 / +b00011 = +#295 +0! +#300 +1! +b10101 = +b0000000000000000000000000000000000000000000000000000000100101100 / +b00000000000000000000000000011110 $ +b11110 > +b01111 ; +b00011 < +b00011 " +#305 +0! +#310 +1! +b10101 " +b10101 < +b10011 ; +b01111 > +b00000000000000000000000000011111 $ +b0000000000000000000000000000000000000000000000000000000100110110 / +b11110 = +#315 +0! +#320 +1! +b01111 = +b0000000000000000000000000000000000000000000000000000000101000000 / +b00000000000000000000000000100000 $ +b10011 > +b11101 ; +b11110 < +b11110 " +#325 +0! +#330 +1! +b01111 " +b01111 < +b11010 ; +b11101 > +b00000000000000000000000000100001 $ +b0000000000000000000000000000000000000000000000000000000101001010 / +b10011 = +#335 +0! +#340 +1! +b11101 = +b0000000000000000000000000000000000000000000000000000000101010100 / +b00000000000000000000000000100010 $ +b11010 > +b01101 ; +b10011 < +b10011 " +#345 +0! +#350 +1! +b11101 " +b11101 < +b10010 ; +b01101 > +b00000000000000000000000000100011 $ +b0000000000000000000000000000000000000000000000000000000101011110 / +b11010 = +#355 +0! +#360 +1! +b01101 = +b0000000000000000000000000000000000000000000000000000000101101000 / +b00000000000000000000000000100100 $ +b10010 > +b01001 ; +b11010 < +b11010 " +#365 +0! +#370 +1! +b01101 " +b01101 < +b10000 ; +b01001 > +b00000000000000000000000000100101 $ +b0000000000000000000000000000000000000000000000000000000101110010 / +b10010 = +#375 +0! +#380 +1! +b01001 = +b0000000000000000000000000000000000000000000000000000000101111100 / +b00000000000000000000000000100110 $ +b10000 > +b01000 ; +b10010 < +b10010 " +#385 +0! +#390 +1! +b01001 " +b01001 < +b00100 ; +b01000 > +b00000000000000000000000000100111 $ +b0000000000000000000000000000000000000000000000000000000110000110 / +b10000 = +#395 +0! +#400 +1! +b01000 = +b0000000000000000000000000000000000000000000000000000000110010000 / +b00000000000000000000000000101000 $ +b00100 > +b00010 ; +b10000 < +b10000 " +#405 +0! +#410 +1! +b01000 " +b01000 < +b00001 ; +b00010 > +b00000000000000000000000000101001 $ +b0000000000000000000000000000000000000000000000000000000110011010 / +b00100 = +#415 +0! +#420 +1! +b00010 = +b0000000000000000000000000000000000000000000000000000000110100100 / +b00000000000000000000000000101010 $ +b00001 > +b10100 ; +b00100 < +b00100 " +#425 +0! +#430 +1! +b00010 " +b00010 < +b01010 ; +b10100 > +b00000000000000000000000000101011 $ +b0000000000000000000000000000000000000000000000000000000110101110 / +b00001 = +#435 +0! +#440 +1! +b10100 = +b0000000000000000000000000000000000000000000000000000000110111000 / +b00000000000000000000000000101100 $ +b01010 > +b00101 ; +b00001 < +b00001 " +#445 +0! +#450 +1! +b10100 " +b10100 < +b10110 ; +b00101 > +b00000000000000000000000000101101 $ +b0000000000000000000000000000000000000000000000000000000111000010 / +b01010 = +#455 +0! +#460 +1! +b00101 = +b0000000000000000000000000000000000000000000000000000000111001100 / +b00000000000000000000000000101110 $ +b10110 > +b01011 ; +b01010 < +b01010 " +#465 +0! +#470 +1! +b00101 " +b00101 < +b10001 ; +b01011 > +b00000000000000000000000000101111 $ +b0000000000000000000000000000000000000000000000000000000111010110 / +b10110 = +#475 +0! +#480 +1! +b01011 = +b0000000000000000000000000000000000000000000000000000000111100000 / +b00000000000000000000000000110000 $ +b10001 > +b11100 ; +b10110 < +b10110 " +#485 +0! +#490 +1! +b01011 " +b01011 < +b01110 ; +b11100 > +b00000000000000000000000000110001 $ +b0000000000000000000000000000000000000000000000000000000111101010 / +b10001 = +#495 +0! +#500 +1! +b11100 = +b0000000000000000000000000000000000000000000000000000000111110100 / +b00000000000000000000000000110010 $ +b01110 > +b00111 ; +b10001 < +b10001 " +#505 +0! +#510 +1! +b11100 " +b11100 < +b10111 ; +b00111 > +b00000000000000000000000000110011 $ +b0000000000000000000000000000000000000000000000000000000111111110 / +b01110 = +#515 +0! +#520 +1! +b00111 = +b0000000000000000000000000000000000000000000000000000001000001000 / +b00000000000000000000000000110100 $ +b10111 > +b11111 ; +b01110 < +b01110 " +#525 +0! +#530 +1! +b00111 " +b00111 < +b11011 ; +b11111 > +b00000000000000000000000000110101 $ +b0000000000000000000000000000000000000000000000000000001000010010 / +b10111 = +#535 +0! +#540 +1! +b11111 = +b0000000000000000000000000000000000000000000000000000001000011100 / +b00000000000000000000000000110110 $ +b11011 > +b11001 ; +b10111 < +b10111 " +#545 +0! +#550 +1! +b11111 " +b11111 < +b11000 ; +b11001 > +b00000000000000000000000000110111 $ +b0000000000000000000000000000000000000000000000000000001000100110 / +b11011 = +#555 +0! +#560 +1! +b11001 = +b0000000000000000000000000000000000000000000000000000001000110000 / +b00000000000000000000000000111000 $ +b11000 > +b01100 ; +b11011 < +b11011 " +#565 +0! +#570 +1! +b11001 " +b11001 < +b00110 ; +b01100 > +b00000000000000000000000000111001 $ +b0000000000000000000000000000000000000000000000000000001000111010 / +b11000 = +#575 +0! +#580 +1! +b01100 = +b0000000000000000000000000000000000000000000000000000001001000100 / +b00000000000000000000000000111010 $ +b00110 > +b00011 ; +b11000 < +b11000 " +#585 +0! +#590 +1! +b01100 " +b01100 < +b10101 ; +b00011 > +b00000000000000000000000000111011 $ +b0000000000000000000000000000000000000000000000000000001001001110 / +b00110 = +#595 +0! +#600 +1! +b00011 = +b0000000000000000000000000000000000000000000000000000001001011000 / +b00000000000000000000000000111100 $ +b10101 > +b11110 ; +b00110 < +b00110 " +#605 +0! +#610 +1! +b00011 " +b00011 < +b01111 ; +b11110 > +b00000000000000000000000000111101 $ +b0000000000000000000000000000000000000000000000000000001001100010 / +b10101 = +#615 +0! +#620 +1! +b11110 = +b0000000000000000000000000000000000000000000000000000001001101100 / +b00000000000000000000000000111110 $ +b01111 > +b10011 ; +b10101 < +b10101 " +#625 +0! +#630 +1! +b11110 " +b11110 < +b11101 ; +b10011 > +b00000000000000000000000000111111 $ +b0000000000000000000000000000000000000000000000000000001001110110 / +b01111 = +#635 +0! +#640 +1! +b10011 = +b0000000000000000000000000000000000000000000000000000001010000000 / +b00000000000000000000000001000000 $ +b11101 > +b11010 ; +b01111 < +b01111 " +#645 +0! +#650 +1! +b10011 " +b10011 < +b01101 ; +b11010 > +b00000000000000000000000001000001 $ +b0000000000000000000000000000000000000000000000000000001010001010 / +b11101 = +#655 +0! +#660 +1! +b11010 = +b0000000000000000000000000000000000000000000000000000001010010100 / +b00000000000000000000000001000010 $ +b01101 > +b10010 ; +b11101 < +b11101 " +#665 +0! +#670 +1! +b11010 " +b11010 < +b01001 ; +b10010 > +b00000000000000000000000001000011 $ +b0000000000000000000000000000000000000000000000000000001010011110 / +b01101 = +#675 +0! +#680 +1! +b10010 = +b0000000000000000000000000000000000000000000000000000001010101000 / +b00000000000000000000000001000100 $ +b01001 > +b10000 ; +b01101 < +b01101 " +#685 +0! +#690 +1! +b10010 " +b10010 < +b01000 ; +b10000 > +b00000000000000000000000001000101 $ +b0000000000000000000000000000000000000000000000000000001010110010 / +b01001 = +#695 +0! +#700 +1! +b10000 = +b0000000000000000000000000000000000000000000000000000001010111100 / +b00000000000000000000000001000110 $ +b01000 > +b00100 ; +b01001 < +b01001 " +#705 +0! +#710 +1! +b10000 " +b10000 < +b00010 ; +b00100 > +b00000000000000000000000001000111 $ +b0000000000000000000000000000000000000000000000000000001011000110 / +b01000 = +#715 +0! +#720 +1! +b00100 = +b0000000000000000000000000000000000000000000000000000001011010000 / +b00000000000000000000000001001000 $ +b00010 > +b00001 ; +b01000 < +b01000 " +#725 +0! +#730 +1! +b00100 " +b00100 < +b10100 ; +b00001 > +b00000000000000000000000001001001 $ +b0000000000000000000000000000000000000000000000000000001011011010 / +b00010 = +#735 +0! +#740 +1! +b00001 = +b0000000000000000000000000000000000000000000000000000001011100100 / +b00000000000000000000000001001010 $ +b10100 > +b01010 ; +b00010 < +b00010 " +#745 +0! +#750 +1! +b00001 " +b00001 < +b00101 ; +b01010 > +b00000000000000000000000001001011 $ +b0000000000000000000000000000000000000000000000000000001011101110 / +b10100 = +#755 +0! +#760 +1! +b01010 = +b0000000000000000000000000000000000000000000000000000001011111000 / +b00000000000000000000000001001100 $ +b00101 > +b10110 ; +b10100 < +b10100 " +#765 +0! +#770 +1! +b01010 " +b01010 < +b01011 ; +b10110 > +b00000000000000000000000001001101 $ +b0000000000000000000000000000000000000000000000000000001100000010 / +b00101 = +#775 +0! +#780 +1! +b10110 = +b0000000000000000000000000000000000000000000000000000001100001100 / +b00000000000000000000000001001110 $ +b01011 > +b10001 ; +b00101 < +b00101 " +#785 +0! +#790 +1! +b10110 " +b10110 < +b11100 ; +b10001 > +b00000000000000000000000001001111 $ +b0000000000000000000000000000000000000000000000000000001100010110 / +b01011 = +#795 +0! +#800 +1! +b10001 = +b0000000000000000000000000000000000000000000000000000001100100000 / +b00000000000000000000000001010000 $ +b11100 > +b01110 ; +b01011 < +b01011 " +#805 +0! +#810 +1! +b10001 " +b10001 < +b00111 ; +b01110 > +b00000000000000000000000001010001 $ +b0000000000000000000000000000000000000000000000000000001100101010 / +b11100 = +#815 +0! +#820 +1! +b01110 = +b0000000000000000000000000000000000000000000000000000001100110100 / +b00000000000000000000000001010010 $ +b00111 > +b10111 ; +b11100 < +b11100 " +#825 +0! +#830 +1! +b01110 " +b01110 < +b11111 ; +b10111 > +b00000000000000000000000001010011 $ +b0000000000000000000000000000000000000000000000000000001100111110 / +b00111 = +#835 +0! +#840 +1! +b10111 = +b0000000000000000000000000000000000000000000000000000001101001000 / +b00000000000000000000000001010100 $ +b11111 > +b11011 ; +b00111 < +b00111 " +#845 +0! +#850 +1! +b10111 " +b10111 < +b11001 ; +b11011 > +b00000000000000000000000001010101 $ +b0000000000000000000000000000000000000000000000000000001101010010 / +b11111 = +#855 +0! +#860 +1! +b11011 = +b0000000000000000000000000000000000000000000000000000001101011100 / +b00000000000000000000000001010110 $ +b11001 > +b11000 ; +b11111 < +b11111 " +#865 +0! +#870 +1! +b11011 " +b11011 < +b01100 ; +b11000 > +b00000000000000000000000001010111 $ +b0000000000000000000000000000000000000000000000000000001101100110 / +b11001 = +#875 +0! +#880 +1! +b11000 = +b0000000000000000000000000000000000000000000000000000001101110000 / +b00000000000000000000000001011000 $ +b01100 > +b00110 ; +b11001 < +b11001 " +#885 +0! +#890 +1! +b11000 " +b11000 < +b00011 ; +b00110 > +b00000000000000000000000001011001 $ +b0000000000000000000000000000000000000000000000000000001101111010 / +b01100 = +#895 +0! +#900 +1! +b00110 = +b0000000000000000000000000000000000000000000000000000001110000100 / +b00000000000000000000000001011010 $ +b00011 > +b10101 ; +b01100 < +b01100 " +#905 +0! +#910 +1! +b00110 " +b00110 < +b11110 ; +b10101 > +b00000000000000000000000001011011 $ +b0000000000000000000000000000000000000000000000000000001110001110 / +b00011 = +#915 +0! +#920 +1! +b10101 = +b0000000000000000000000000000000000000000000000000000001110011000 / +b00000000000000000000000001011100 $ +b11110 > +b01111 ; +b00011 < +b00011 " +#925 +0! +#930 +1! +b10101 " +b10101 < +b10011 ; +b01111 > +b00000000000000000000000001011101 $ +b0000000000000000000000000000000000000000000000000000001110100010 / +b11110 = +#935 +0! +#940 +1! +b01111 = +b0000000000000000000000000000000000000000000000000000001110101100 / +b00000000000000000000000001011110 $ +b10011 > +b11101 ; +b11110 < +b11110 " +#945 +0! +#950 +1! +b01111 " +b01111 < +b11010 ; +b11101 > +b00000000000000000000000001011111 $ +b0000000000000000000000000000000000000000000000000000001110110110 / +b10011 = +#955 +0! +#960 +1! +b11101 = +b0000000000000000000000000000000000000000000000000000001111000000 / +b00000000000000000000000001100000 $ +b11010 > +b01101 ; +b10011 < +b10011 " +#965 +0! +#970 +1! +b11101 " +b11101 < +b10010 ; +b01101 > +b00000000000000000000000001100001 $ +b0000000000000000000000000000000000000000000000000000001111001010 / +b11010 = +#975 +0! +#980 +1! +b01101 = +b0000000000000000000000000000000000000000000000000000001111010100 / +b00000000000000000000000001100010 $ +b10010 > +b01001 ; +b11010 < +b11010 " +#985 +0! +#990 +1! +b01101 " +b01101 < +b10000 ; +b01001 > +b00000000000000000000000001100011 $ +b0000000000000000000000000000000000000000000000000000001111011110 / +b10010 = +#995 +0! +#1000 +1! +b01001 = +b0000000000000000000000000000000000000000000000000000001111101000 / +b00000000000000000000000001100100 $ +b10000 > +b01000 ; +b10010 < +b10010 " +#1004 diff --git a/test_regress/t/t_trace_basic_sc_fst.py b/test_regress/t/t_trace_basic_sc_fst.py new file mode 100755 index 000000000..a95b13c4a --- /dev/null +++ b/test_regress/t/t_trace_basic_sc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_sc_fst_cmake.py b/test_regress/t/t_trace_basic_sc_fst_cmake.py new file mode 100755 index 000000000..fa52fde4c --- /dev/null +++ b/test_regress/t/t_trace_basic_sc_fst_cmake.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_saif_sc.out b/test_regress/t/t_trace_basic_sc_saif.out similarity index 87% rename from test_regress/t/t_trace_saif_sc.out rename to test_regress/t/t_trace_basic_sc_saif.out index 840660324..ee0493181 100644 --- a/test_regress/t/t_trace_saif_sc.out +++ b/test_regress/t/t_trace_basic_sc_saif.out @@ -10,6 +10,12 @@ (INSTANCE t (NET (clk (T0 505) (T1 499) (TZ 0) (TX 0) (TB 0) (TC 199)) + (state\[0\] (T0 414) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state\[1\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) + (state\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state\[3\] (T0 544) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) + (state\[4\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) + (fst_inout (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) (cyc\[1\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) (cyc\[2\] (T0 520) (T1 484) (TZ 0) (TX 0) (TB 0) (TC 25)) @@ -389,6 +395,70 @@ (fst_byte\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[1\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) + (fst_time\[2\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) + (fst_time\[3\] (T0 500) (T1 504) (TZ 0) (TX 0) (TB 0) (TC 75)) + (fst_time\[4\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 62)) + (fst_time\[5\] (T0 520) (T1 484) (TZ 0) (TX 0) (TB 0) (TC 31)) + (fst_time\[6\] (T0 520) (T1 484) (TZ 0) (TX 0) (TB 0) (TC 15)) + (fst_time\[7\] (T0 510) (T1 494) (TZ 0) (TX 0) (TB 0) (TC 7)) + (fst_time\[8\] (T0 510) (T1 494) (TZ 0) (TX 0) (TB 0) (TC 3)) + (fst_time\[9\] (T0 520) (T1 484) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_time\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + 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(TX 0) (TB 0) (TC 0)) + (fst_time\[42\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[43\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[44\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[45\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[46\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[47\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[48\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[49\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[50\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[51\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[52\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[53\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[54\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[55\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[56\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[57\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[58\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[59\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[60\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[61\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[62\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_time\[63\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[0\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[1\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) @@ -458,12 +528,12 @@ (fst_tri0 (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_tri1 (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_triand (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_trior (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_wand (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (fst_wor (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wire (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (state\[0\] (T0 414) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state\[1\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) - (state\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state\[3\] (T0 544) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) - (state\[4\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) + (fst_uwire (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE test (NET diff --git a/test_regress/t/t_trace_basic_sc_saif.py b/test_regress/t/t_trace_basic_sc_saif.py new file mode 100755 index 000000000..a95b13c4a --- /dev/null +++ b/test_regress/t/t_trace_basic_sc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_sc_saif_cmake.py b/test_regress/t/t_trace_basic_sc_saif_cmake.py new file mode 100755 index 000000000..fa52fde4c --- /dev/null +++ b/test_regress/t/t_trace_basic_sc_saif_cmake.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_basic_sc_vcd.out b/test_regress/t/t_trace_basic_sc_vcd.out new file mode 100644 index 000000000..7632f245b --- /dev/null +++ b/test_regress/t/t_trace_basic_sc_vcd.out @@ -0,0 +1,1123 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $scope module t $end + $var wire 1 ' clk $end + $var wire 5 " state [4:0] $end + $var wire 1 , fst_inout $end + $var wire 32 ( cyc [31:0] $end + $var wire 1 ) rstn $end + $var real 64 - fst_gparam_real $end + $var real 64 / fst_lparam_real $end + $var real 64 - fst_real $end + $var wire 32 1 fst_integer [31:0] $end + $var wire 1 2 fst_bit $end + $var wire 1 3 fst_logic $end + $var wire 32 4 fst_int [31:0] $end + $var wire 16 5 fst_shortint [15:0] $end + $var wire 64 6 fst_longint [63:0] $end + $var wire 8 8 fst_byte [7:0] $end + $var wire 64 * fst_time [63:0] $end + $var wire 32 9 fst_parameter [31:0] $end + $var wire 32 : fst_lparam [31:0] $end + $var wire 1 ; fst_supply0 $end + $var wire 1 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+b11010 % +b01101 & +1' +b00000000000000000000000001100001 ( +b0000000000000000000000000000000000000000000000000000001111001010 * +#975 +0' +#980 +b11010 " +b01001 # +b11010 $ +b01101 % +b10010 & +1' +b00000000000000000000000001100010 ( +b0000000000000000000000000000000000000000000000000000001111010100 * +#985 +0' +#990 +b01101 " +b10000 # +b01101 $ +b10010 % +b01001 & +1' +b00000000000000000000000001100011 ( +b0000000000000000000000000000000000000000000000000000001111011110 * +#995 +0' +#1000 +b10010 " +b01000 # +b10010 $ +b01001 % +b10000 & +1' +b00000000000000000000000001100100 ( +b0000000000000000000000000000000000000000000000000000001111101000 * +#1004 diff --git a/test_regress/t/t_trace_basic_sc_vcd.py b/test_regress/t/t_trace_basic_sc_vcd.py new file mode 100755 index 000000000..a95b13c4a --- /dev/null +++ b/test_regress/t/t_trace_basic_sc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test) diff --git a/test_regress/t/t_trace_basic_sc_vcd_cmake.py b/test_regress/t/t_trace_basic_sc_vcd_cmake.py new file mode 100755 index 000000000..fa52fde4c --- /dev/null +++ b/test_regress/t/t_trace_basic_sc_vcd_cmake.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_basic_common + +test.scenarios('vlt_all') + +trace_basic_common.run(test, cmake=True) diff --git a/test_regress/t/t_trace_cat.cpp b/test_regress/t/t_trace_cat.cpp index 7743ed677..54e285d67 100644 --- a/test_regress/t/t_trace_cat.cpp +++ b/test_regress/t/t_trace_cat.cpp @@ -7,7 +7,7 @@ // SPDX-License-Identifier: CC0-1.0 #include -#include +#include VL_STRINGIFY(TRACE_HEADER_C) #include @@ -22,7 +22,8 @@ double sc_time_stamp() { return (double)main_time; } const char* trace_name() { static char name[1000]; - VL_SNPRINTF(name, 1000, VL_STRINGIFY(TEST_OBJ_DIR) "/simpart_%04d.vcd", (int)main_time); + VL_SNPRINTF(name, 1000, VL_STRINGIFY(TEST_OBJ_DIR) "/simx_part_%04d." VL_STRINGIFY(TRACE_FMT), + (int)main_time); return name; } @@ -33,7 +34,7 @@ int main(int argc, char** argv) { std::unique_ptr top{new VM_PREFIX{"top"}}; - std::unique_ptr tfp{new VerilatedVcdC}; + std::unique_ptr tfp{new VERILATED_TRACE_C}; top->trace(tfp.get(), 99); // Test for traceCapable - randomly-ish selected this test @@ -48,14 +49,14 @@ int main(int argc, char** argv) { top->eval(); if ((main_time % 100) == 0) { -#if defined(T_TRACE_CAT) +#if defined(TRACE_OPENNEXT) tfp->openNext(true); -#elif defined(T_TRACE_CAT_REOPEN) +#elif defined(TRACE_REOPEN) tfp->close(); tfp->open(trace_name()); -#elif defined(T_TRACE_CAT_RENEW) +#elif defined(TRACE_RENEW) tfp->close(); - tfp.reset(new VerilatedVcdC); + tfp.reset(new VERILATED_TRACE_C); top->trace(tfp.get(), 99); tfp->open(trace_name()); #else diff --git a/test_regress/t/t_trace_cat.out b/test_regress/t/t_trace_cat.out deleted file mode 100644 index b564e6bde..000000000 --- a/test_regress/t/t_trace_cat.out +++ /dev/null @@ -1,488 +0,0 @@ -$version Generated by VerilatedVcd $end -$timescale 1ps $end - - $scope module top $end - $var wire 1 # clk $end - $scope module t $end - $var wire 1 # clk $end - $var wire 32 $ cyc [31:0] $end - $upscope $end - $upscope $end -$enddefinitions $end - - -#0 -1# -b00000000000000000000000000000000 $ -#1 -0# -#2 -1# -b00000000000000000000000000000001 $ -#3 -0# -#4 -1# -b00000000000000000000000000000010 $ -#5 -0# -#6 -1# -b00000000000000000000000000000011 $ -#7 -0# -#8 -1# -b00000000000000000000000000000100 $ -#9 -0# -#10 -1# -b00000000000000000000000000000101 $ -#11 -0# -#12 -1# -b00000000000000000000000000000110 $ -#13 -0# -#14 -1# -b00000000000000000000000000000111 $ -#15 -0# -#16 -1# -b00000000000000000000000000001000 $ -#17 -0# -#18 -1# -b00000000000000000000000000001001 $ -#19 -0# -#20 -1# -b00000000000000000000000000001010 $ -#21 -0# -#22 -1# -b00000000000000000000000000001011 $ -#23 -0# -#24 -1# -b00000000000000000000000000001100 $ -#25 -0# -#26 -1# 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can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.compile(make_top_shell=False, - make_main=False, - v_flags2=["--trace-vcd --exe", test.pli_filename]) - -test.execute() - -os.system("cat " + test.obj_dir + "/simpart_0000.vcd " + " " + test.obj_dir + - "/simpart_0000_cat*.vcd > " + test.obj_dir + "/simall.vcd") - -test.vcd_identical(test.obj_dir + "/simall.vcd", test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_cat.v b/test_regress/t/t_trace_cat.v index d27661a43..05b64fdb0 100644 --- a/test_regress/t/t_trace_cat.v +++ b/test_regress/t/t_trace_cat.v @@ -10,6 +10,8 @@ module t ( integer cyc; initial cyc = 0; + integer unchanged; + initial unchanged = 42; always @(posedge clk) begin cyc <= cyc + 1; diff --git a/test_regress/t/t_trace_cat_fst.py b/test_regress/t/t_trace_cat_fst.py deleted file mode 100755 index a06f27bb3..000000000 --- a/test_regress/t/t_trace_cat_fst.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.compile(make_top_shell=False, - make_main=False, - v_flags2=["--trace-fst --exe", test.pli_filename]) - -test.execute() - -test.fst_identical(test.obj_dir + "/simpart_0000.fst", "t/" + test.name + "__0000.out") -test.fst_identical(test.obj_dir + "/simpart_0100.fst", "t/" + test.name + "__0100.out") - -test.passes() diff --git a/test_regress/t/t_trace_cat_fst.v b/test_regress/t/t_trace_cat_fst.v deleted file mode 100644 index 05b64fdb0..000000000 --- a/test_regress/t/t_trace_cat_fst.v +++ /dev/null @@ -1,19 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2013 Wilson Snyder -// SPDX-License-Identifier: CC0-1.0 - -module t ( - input wire clk -); - - integer cyc; - initial cyc = 0; - integer unchanged; - initial unchanged = 42; - - always @(posedge clk) begin - cyc <= cyc + 1; - end -endmodule diff --git a/test_regress/t/t_trace_cat_renew.out b/test_regress/t/t_trace_cat_opennext_vcd.out similarity index 55% rename from test_regress/t/t_trace_cat_renew.out rename to test_regress/t/t_trace_cat_opennext_vcd.out index 51fb48a1c..dfa77a1a1 100644 --- a/test_regress/t/t_trace_cat_renew.out +++ b/test_regress/t/t_trace_cat_opennext_vcd.out @@ -1,765 +1,490 @@ $version Generated by VerilatedVcd $end -$date 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-b00000000000000000000000010010101 # -1$ -#297 -0$ -#298 -b00000000000000000000000010010110 # -1$ -#299 -0$ +0" diff --git a/test_regress/t/t_trace_cat_opennext_vcd.py b/test_regress/t/t_trace_cat_opennext_vcd.py new file mode 100755 index 000000000..e1fda3adb --- /dev/null +++ b/test_regress/t/t_trace_cat_opennext_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_cat_common + +test.scenarios('vlt_all') + +trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_renew.py b/test_regress/t/t_trace_cat_renew.py deleted file mode 100755 index 251b94f4f..000000000 --- a/test_regress/t/t_trace_cat_renew.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.pli_filename = "t/t_trace_cat.cpp" -test.top_filename = "t/t_trace_cat.v" - -test.compile(make_top_shell=False, - make_main=False, - v_flags2=["--trace-vcd --exe", test.pli_filename]) - -test.execute() - -test.vcd_identical(test.obj_dir + "/simpart_0000.vcd", "t/" + test.name + "__0000.out") -test.vcd_identical(test.obj_dir + "/simpart_0100.vcd", "t/" + test.name + "__0100.out") - -test.passes() diff --git a/test_regress/t/t_trace_cat_renew__0000.out b/test_regress/t/t_trace_cat_renew__0000.out deleted file mode 100644 index 4243f33b4..000000000 --- a/test_regress/t/t_trace_cat_renew__0000.out +++ /dev/null @@ -1,263 +0,0 @@ -$version Generated by VerilatedVcd $end -$timescale 1ps $end - - $scope module top $end - $var wire 1 # clk $end - $scope module t $end - $var wire 1 # clk $end - $var wire 32 $ cyc [31:0] $end - $upscope $end - $upscope $end -$enddefinitions $end - - -#0 -1# -b00000000000000000000000000000000 $ -#1 -0# -#2 -1# -b00000000000000000000000000000001 $ -#3 -0# -#4 -1# -b00000000000000000000000000000010 $ -#5 -0# -#6 -1# -b00000000000000000000000000000011 $ -#7 -0# -#8 -1# -b00000000000000000000000000000100 $ -#9 -0# -#10 -1# -b00000000000000000000000000000101 $ -#11 -0# -#12 -1# -b00000000000000000000000000000110 $ -#13 -0# -#14 -1# -b00000000000000000000000000000111 $ -#15 -0# -#16 -1# -b00000000000000000000000000001000 $ -#17 -0# -#18 -1# -b00000000000000000000000000001001 $ -#19 -0# -#20 -1# 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-b00000000000000000000000000101110 $ -#93 -0# -#94 -1# -b00000000000000000000000000101111 $ -#95 -0# -#96 -1# -b00000000000000000000000000110000 $ -#97 -0# -#98 -1# -b00000000000000000000000000110001 $ -#99 -0# diff --git a/test_regress/t/t_trace_cat_renew__0100.out b/test_regress/t/t_trace_cat_renew__0100.out deleted file mode 100644 index e529569d4..000000000 --- a/test_regress/t/t_trace_cat_renew__0100.out +++ /dev/null @@ -1,237 +0,0 @@ -$version Generated by VerilatedVcd $end -$timescale 1ps $end - $scope module top $end - $var wire 1 # clk $end - $scope module t $end - $var wire 1 # clk $end - $var wire 32 $ cyc [31:0] $end - $upscope $end - $upscope $end -$enddefinitions $end - - -#100 -1# -b00000000000000000000000000110010 $ -#101 -0# -#102 -1# -b00000000000000000000000000110011 $ -#103 -0# -#104 -1# -b00000000000000000000000000110100 $ -#105 -0# -#106 -1# -b00000000000000000000000000110101 $ -#107 -0# -#108 -1# -b00000000000000000000000000110110 $ -#109 -0# -#110 -1# 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-b00000000000000000000000001011001 $ -#179 -0# -#180 -1# -b00000000000000000000000001011010 $ -#181 -0# -#182 -1# -b00000000000000000000000001011011 $ -#183 -0# -#184 -1# -b00000000000000000000000001011100 $ -#185 -0# -#186 -1# -b00000000000000000000000001011101 $ -#187 -0# -#188 -1# -b00000000000000000000000001011110 $ -#189 -0# diff --git a/test_regress/t/t_trace_cat_renew_fst.py b/test_regress/t/t_trace_cat_renew_fst.py new file mode 100755 index 000000000..e1fda3adb --- /dev/null +++ b/test_regress/t/t_trace_cat_renew_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_cat_common + +test.scenarios('vlt_all') + +trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_fst__0000.out b/test_regress/t/t_trace_cat_renew_fst_part_0000.out similarity index 100% rename from test_regress/t/t_trace_cat_fst__0000.out rename to test_regress/t/t_trace_cat_renew_fst_part_0000.out diff --git a/test_regress/t/t_trace_cat_fst__0100.out b/test_regress/t/t_trace_cat_renew_fst_part_0100.out similarity index 100% rename from test_regress/t/t_trace_cat_fst__0100.out rename to test_regress/t/t_trace_cat_renew_fst_part_0100.out diff --git a/test_regress/t/t_trace_cat_renew_saif.py b/test_regress/t/t_trace_cat_renew_saif.py new file mode 100755 index 000000000..e1fda3adb --- /dev/null +++ b/test_regress/t/t_trace_cat_renew_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_cat_common + +test.scenarios('vlt_all') + +trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_renew_saif_part_0000.out b/test_regress/t/t_trace_cat_renew_saif_part_0000.out new file mode 100644 index 000000000..b0e5e8900 --- /dev/null +++ b/test_regress/t/t_trace_cat_renew_saif_part_0000.out @@ -0,0 +1,83 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 99) + (INSTANCE top + (NET + (clk (T0 49) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 100)) + ) + (INSTANCE t + (NET + (clk (T0 49) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 100)) + (cyc\[0\] (T0 50) (T1 49) (TZ 0) (TX 0) (TB 0) (TC 49)) + (cyc\[1\] (T0 51) (T1 48) (TZ 0) (TX 0) (TB 0) (TC 24)) + (cyc\[2\] (T0 51) (T1 48) (TZ 0) (TX 0) (TB 0) (TC 12)) + (cyc\[3\] (T0 51) (T1 48) (TZ 0) (TX 0) (TB 0) (TC 6)) + (cyc\[4\] (T0 64) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 3)) + (cyc\[5\] (T0 64) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 1)) + (cyc\[6\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[7\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[8\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[9\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[10\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[11\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[12\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[13\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[14\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[15\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[16\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[17\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[18\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[19\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[20\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[21\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[22\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[23\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[24\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[25\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[26\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[27\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[28\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[29\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[30\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[31\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[0\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[1\] (T0 0) (T1 99) (TZ 0) (TX 0) (TB 0) (TC 1)) + (unchanged\[2\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[3\] (T0 0) (T1 99) (TZ 0) (TX 0) (TB 0) (TC 1)) + (unchanged\[4\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[5\] (T0 0) (T1 99) (TZ 0) (TX 0) (TB 0) (TC 1)) + (unchanged\[6\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[7\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[8\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[9\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[10\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[11\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[12\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[13\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[14\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[15\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[16\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[17\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[18\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[19\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[20\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[21\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[22\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[23\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[24\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[25\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[26\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[27\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[28\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[29\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[30\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[31\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + ) +) diff --git a/test_regress/t/t_trace_cat_renew_saif_part_0100.out b/test_regress/t/t_trace_cat_renew_saif_part_0100.out new file mode 100644 index 000000000..cf4af2681 --- /dev/null +++ b/test_regress/t/t_trace_cat_renew_saif_part_0100.out @@ -0,0 +1,83 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 189) + (INSTANCE top + (NET + (clk (T0 144) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 90)) + ) + (INSTANCE t + (NET + (clk (T0 144) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 90)) + (cyc\[0\] (T0 145) (T1 44) (TZ 0) (TX 0) (TB 0) (TC 44)) + (cyc\[1\] (T0 144) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 23)) + (cyc\[2\] (T0 144) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 11)) + (cyc\[3\] (T0 144) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 5)) + (cyc\[4\] (T0 132) (T1 57) (TZ 0) (TX 0) (TB 0) (TC 3)) + (cyc\[5\] (T0 161) (T1 28) (TZ 0) (TX 0) (TB 0) (TC 2)) + (cyc\[6\] (T0 128) (T1 61) (TZ 0) (TX 0) (TB 0) (TC 1)) + (cyc\[7\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[8\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[9\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[10\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[11\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[12\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[13\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[14\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[15\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[16\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[17\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[18\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[19\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[20\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[21\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[22\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[23\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[24\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[25\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[26\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[27\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[28\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[29\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[30\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[31\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[0\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[1\] (T0 100) (T1 89) (TZ 0) (TX 0) (TB 0) (TC 1)) + (unchanged\[2\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[3\] (T0 100) (T1 89) (TZ 0) (TX 0) (TB 0) (TC 1)) + (unchanged\[4\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[5\] (T0 100) (T1 89) (TZ 0) (TX 0) (TB 0) (TC 1)) + (unchanged\[6\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[7\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[8\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[9\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[10\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[11\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[12\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[13\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[14\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[15\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[16\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[17\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[18\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[19\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[20\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[21\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[22\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[23\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[24\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[25\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[26\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[27\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[28\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[29\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[30\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[31\] (T0 189) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + ) +) diff --git a/test_regress/t/t_trace_cat_renew_vcd.py b/test_regress/t/t_trace_cat_renew_vcd.py new file mode 100755 index 000000000..e1fda3adb --- /dev/null +++ b/test_regress/t/t_trace_cat_renew_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_cat_common + +test.scenarios('vlt_all') + +trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_renew_vcd_part_0000.out b/test_regress/t/t_trace_cat_renew_vcd_part_0000.out new file mode 100644 index 000000000..4af2c7cad --- /dev/null +++ b/test_regress/t/t_trace_cat_renew_vcd_part_0000.out @@ -0,0 +1,264 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 " clk $end + $scope module t $end + $var wire 1 " clk $end + $var wire 32 # cyc [31:0] $end + $var wire 32 $ unchanged [31:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +1" +b00000000000000000000000000000000 # +b00000000000000000000000000101010 $ +#1 +0" +#2 +1" +b00000000000000000000000000000001 # +#3 +0" +#4 +1" +b00000000000000000000000000000010 # +#5 +0" +#6 +1" +b00000000000000000000000000000011 # +#7 +0" +#8 +1" +b00000000000000000000000000000100 # +#9 +0" +#10 +1" +b00000000000000000000000000000101 # +#11 +0" +#12 +1" +b00000000000000000000000000000110 # +#13 +0" +#14 +1" +b00000000000000000000000000000111 # +#15 +0" +#16 +1" +b00000000000000000000000000001000 # +#17 +0" +#18 +1" +b00000000000000000000000000001001 # +#19 +0" +#20 +1" +b00000000000000000000000000001010 # +#21 +0" +#22 +1" +b00000000000000000000000000001011 # +#23 +0" +#24 +1" +b00000000000000000000000000001100 # +#25 +0" +#26 +1" +b00000000000000000000000000001101 # +#27 +0" +#28 +1" +b00000000000000000000000000001110 # +#29 +0" +#30 +1" +b00000000000000000000000000001111 # +#31 +0" +#32 +1" +b00000000000000000000000000010000 # +#33 +0" +#34 +1" +b00000000000000000000000000010001 # +#35 +0" +#36 +1" +b00000000000000000000000000010010 # +#37 +0" +#38 +1" +b00000000000000000000000000010011 # +#39 +0" +#40 +1" +b00000000000000000000000000010100 # +#41 +0" +#42 +1" +b00000000000000000000000000010101 # +#43 +0" +#44 +1" +b00000000000000000000000000010110 # +#45 +0" +#46 +1" +b00000000000000000000000000010111 # +#47 +0" +#48 +1" +b00000000000000000000000000011000 # +#49 +0" +#50 +1" +b00000000000000000000000000011001 # +#51 +0" +#52 +1" +b00000000000000000000000000011010 # +#53 +0" +#54 +1" +b00000000000000000000000000011011 # +#55 +0" +#56 +1" +b00000000000000000000000000011100 # +#57 +0" +#58 +1" +b00000000000000000000000000011101 # +#59 +0" +#60 +1" +b00000000000000000000000000011110 # +#61 +0" +#62 +1" +b00000000000000000000000000011111 # +#63 +0" +#64 +1" +b00000000000000000000000000100000 # +#65 +0" +#66 +1" +b00000000000000000000000000100001 # +#67 +0" +#68 +1" +b00000000000000000000000000100010 # +#69 +0" +#70 +1" +b00000000000000000000000000100011 # +#71 +0" +#72 +1" +b00000000000000000000000000100100 # +#73 +0" +#74 +1" +b00000000000000000000000000100101 # +#75 +0" +#76 +1" +b00000000000000000000000000100110 # +#77 +0" +#78 +1" +b00000000000000000000000000100111 # +#79 +0" +#80 +1" +b00000000000000000000000000101000 # +#81 +0" +#82 +1" +b00000000000000000000000000101001 # +#83 +0" +#84 +1" +b00000000000000000000000000101010 # +#85 +0" +#86 +1" +b00000000000000000000000000101011 # +#87 +0" +#88 +1" +b00000000000000000000000000101100 # +#89 +0" +#90 +1" +b00000000000000000000000000101101 # +#91 +0" +#92 +1" +b00000000000000000000000000101110 # +#93 +0" +#94 +1" +b00000000000000000000000000101111 # +#95 +0" +#96 +1" +b00000000000000000000000000110000 # +#97 +0" +#98 +1" +b00000000000000000000000000110001 # +#99 +0" diff --git a/test_regress/t/t_trace_cat_renew_vcd_part_0100.out b/test_regress/t/t_trace_cat_renew_vcd_part_0100.out new file mode 100644 index 000000000..4cca416fe --- /dev/null +++ b/test_regress/t/t_trace_cat_renew_vcd_part_0100.out @@ -0,0 +1,239 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 " clk $end + $scope module t $end + $var wire 1 " clk $end + $var wire 32 # cyc [31:0] $end + $var wire 32 $ unchanged [31:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#100 +1" +b00000000000000000000000000110010 # +b00000000000000000000000000101010 $ +#101 +0" +#102 +1" +b00000000000000000000000000110011 # +#103 +0" +#104 +1" +b00000000000000000000000000110100 # +#105 +0" +#106 +1" +b00000000000000000000000000110101 # +#107 +0" +#108 +1" +b00000000000000000000000000110110 # +#109 +0" +#110 +1" +b00000000000000000000000000110111 # +#111 +0" +#112 +1" +b00000000000000000000000000111000 # +#113 +0" +#114 +1" +b00000000000000000000000000111001 # +#115 +0" +#116 +1" +b00000000000000000000000000111010 # +#117 +0" +#118 +1" +b00000000000000000000000000111011 # +#119 +0" +#120 +1" +b00000000000000000000000000111100 # +#121 +0" +#122 +1" +b00000000000000000000000000111101 # +#123 +0" +#124 +1" +b00000000000000000000000000111110 # +#125 +0" +#126 +1" +b00000000000000000000000000111111 # +#127 +0" +#128 +1" +b00000000000000000000000001000000 # +#129 +0" +#130 +1" +b00000000000000000000000001000001 # +#131 +0" +#132 +1" +b00000000000000000000000001000010 # +#133 +0" +#134 +1" +b00000000000000000000000001000011 # +#135 +0" +#136 +1" +b00000000000000000000000001000100 # +#137 +0" +#138 +1" +b00000000000000000000000001000101 # +#139 +0" +#140 +1" +b00000000000000000000000001000110 # +#141 +0" +#142 +1" +b00000000000000000000000001000111 # +#143 +0" +#144 +1" +b00000000000000000000000001001000 # +#145 +0" +#146 +1" +b00000000000000000000000001001001 # +#147 +0" +#148 +1" +b00000000000000000000000001001010 # +#149 +0" +#150 +1" +b00000000000000000000000001001011 # +#151 +0" +#152 +1" +b00000000000000000000000001001100 # +#153 +0" +#154 +1" +b00000000000000000000000001001101 # +#155 +0" +#156 +1" +b00000000000000000000000001001110 # +#157 +0" +#158 +1" +b00000000000000000000000001001111 # +#159 +0" +#160 +1" +b00000000000000000000000001010000 # +#161 +0" +#162 +1" +b00000000000000000000000001010001 # +#163 +0" +#164 +1" +b00000000000000000000000001010010 # +#165 +0" +#166 +1" +b00000000000000000000000001010011 # +#167 +0" +#168 +1" +b00000000000000000000000001010100 # +#169 +0" +#170 +1" +b00000000000000000000000001010101 # +#171 +0" +#172 +1" +b00000000000000000000000001010110 # +#173 +0" +#174 +1" +b00000000000000000000000001010111 # +#175 +0" +#176 +1" +b00000000000000000000000001011000 # +#177 +0" +#178 +1" +b00000000000000000000000001011001 # +#179 +0" +#180 +1" +b00000000000000000000000001011010 # +#181 +0" +#182 +1" +b00000000000000000000000001011011 # +#183 +0" +#184 +1" +b00000000000000000000000001011100 # +#185 +0" +#186 +1" +b00000000000000000000000001011101 # +#187 +0" +#188 +1" +b00000000000000000000000001011110 # +#189 +0" diff --git a/test_regress/t/t_trace_cat_reopen.out b/test_regress/t/t_trace_cat_reopen.out deleted file mode 100644 index 51fb48a1c..000000000 --- a/test_regress/t/t_trace_cat_reopen.out +++ /dev/null @@ -1,765 +0,0 @@ -$version Generated by VerilatedVcd $end -$date Sat Feb 23 20:18:07 2013 - $end -$timescale 1ps $end - - $scope module top $end - $var wire 1 $ clk $end - $scope module t $end - $var wire 1 $ clk $end - $var wire 32 # cyc [31:0] $end - $upscope $end - $upscope $end -$enddefinitions $end - - -#0 -b00000000000000000000000000000001 # -1$ -#1 -0$ -#2 -b00000000000000000000000000000010 # -1$ -#3 -0$ -#4 -b00000000000000000000000000000011 # -1$ -#5 -0$ -#6 -b00000000000000000000000000000100 # -1$ -#7 -0$ -#8 -b00000000000000000000000000000101 # -1$ -#9 -0$ -#10 -b00000000000000000000000000000110 # -1$ -#11 -0$ -#12 -b00000000000000000000000000000111 # -1$ -#13 -0$ -#14 -b00000000000000000000000000001000 # -1$ -#15 -0$ -#16 -b00000000000000000000000000001001 # -1$ -#17 -0$ -#18 -b00000000000000000000000000001010 # -1$ -#19 -0$ -#20 -b00000000000000000000000000001011 # -1$ -#21 -0$ -#22 -b00000000000000000000000000001100 # -1$ -#23 -0$ -#24 -b00000000000000000000000000001101 # -1$ -#25 -0$ -#26 -b00000000000000000000000000001110 # -1$ -#27 -0$ -#28 -b00000000000000000000000000001111 # -1$ -#29 -0$ -#30 -b00000000000000000000000000010000 # -1$ -#31 -0$ -#32 -b00000000000000000000000000010001 # -1$ -#33 -0$ -#34 -b00000000000000000000000000010010 # -1$ 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it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.pli_filename = "t/t_trace_cat.cpp" -test.top_filename = "t/t_trace_cat.v" - -test.compile(make_top_shell=False, - make_main=False, - v_flags2=["--trace-vcd --exe", test.pli_filename]) - -test.execute() - -test.vcd_identical(test.obj_dir + "/simpart_0000.vcd", "t/" + test.name + "__0000.out") -test.vcd_identical(test.obj_dir + "/simpart_0100.vcd", "t/" + test.name + "__0100.out") - -test.passes() diff --git a/test_regress/t/t_trace_cat_reopen__0000.out b/test_regress/t/t_trace_cat_reopen__0000.out deleted file mode 100644 index 4243f33b4..000000000 --- a/test_regress/t/t_trace_cat_reopen__0000.out +++ /dev/null @@ -1,263 +0,0 @@ -$version Generated by VerilatedVcd $end -$timescale 1ps $end - - $scope module top $end - $var wire 1 # clk $end - $scope module t $end - $var wire 1 # clk $end - $var wire 32 $ cyc [31:0] $end - $upscope $end - $upscope $end -$enddefinitions $end - - -#0 -1# -b00000000000000000000000000000000 $ -#1 -0# -#2 -1# -b00000000000000000000000000000001 $ -#3 -0# -#4 -1# -b00000000000000000000000000000010 $ -#5 -0# -#6 -1# -b00000000000000000000000000000011 $ -#7 -0# -#8 -1# -b00000000000000000000000000000100 $ -#9 -0# -#10 -1# -b00000000000000000000000000000101 $ -#11 -0# -#12 -1# -b00000000000000000000000000000110 $ -#13 -0# -#14 -1# -b00000000000000000000000000000111 $ -#15 -0# -#16 -1# -b00000000000000000000000000001000 $ -#17 -0# -#18 -1# -b00000000000000000000000000001001 $ -#19 -0# -#20 -1# -b00000000000000000000000000001010 $ -#21 -0# -#22 -1# -b00000000000000000000000000001011 $ -#23 -0# -#24 -1# -b00000000000000000000000000001100 $ -#25 -0# -#26 -1# -b00000000000000000000000000001101 $ -#27 -0# -#28 -1# -b00000000000000000000000000001110 $ -#29 -0# -#30 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b/test_regress/t/t_trace_cat_reopen__0100.out deleted file mode 100644 index de350d664..000000000 --- a/test_regress/t/t_trace_cat_reopen__0100.out +++ /dev/null @@ -1,238 +0,0 @@ -$version Generated by VerilatedVcd $end -$timescale 1ps $end - - $scope module top $end - $var wire 1 # clk $end - $scope module t $end - $var wire 1 # clk $end - $var wire 32 $ cyc [31:0] $end - $upscope $end - $upscope $end -$enddefinitions $end - - -#100 -1# -b00000000000000000000000000110010 $ -#101 -0# -#102 -1# -b00000000000000000000000000110011 $ -#103 -0# -#104 -1# -b00000000000000000000000000110100 $ -#105 -0# -#106 -1# -b00000000000000000000000000110101 $ -#107 -0# -#108 -1# -b00000000000000000000000000110110 $ -#109 -0# -#110 -1# -b00000000000000000000000000110111 $ -#111 -0# -#112 -1# -b00000000000000000000000000111000 $ -#113 -0# -#114 -1# -b00000000000000000000000000111001 $ -#115 -0# -#116 -1# -b00000000000000000000000000111010 $ -#117 -0# -#118 -1# -b00000000000000000000000000111011 $ -#119 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-b00000000000000000000000001011110 $ -#189 -0# diff --git a/test_regress/t/t_trace_cat_reopen_fst.py b/test_regress/t/t_trace_cat_reopen_fst.py new file mode 100755 index 000000000..e1fda3adb --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_cat_common + +test.scenarios('vlt_all') + +trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_reopen_fst_part_0000.out b/test_regress/t/t_trace_cat_reopen_fst_part_0000.out new file mode 100644 index 000000000..bff2d2b8b --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen_fst_part_0000.out @@ -0,0 +1,272 @@ +$date + Wed Feb 23 00:00:47 2022 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$var wire 1 ! clk $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc [31:0] $end +$var integer 32 # unchanged [31:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b00000000000000000000000000101010 # +b00000000000000000000000000000000 " +1! +$end +#1 +0! +#2 +1! +b00000000000000000000000000000001 " +#3 +0! +#4 +1! +b00000000000000000000000000000010 " +#5 +0! +#6 +1! +b00000000000000000000000000000011 " +#7 +0! +#8 +1! +b00000000000000000000000000000100 " +#9 +0! +#10 +1! +b00000000000000000000000000000101 " +#11 +0! +#12 +1! +b00000000000000000000000000000110 " +#13 +0! +#14 +1! +b00000000000000000000000000000111 " +#15 +0! +#16 +1! +b00000000000000000000000000001000 " +#17 +0! +#18 +1! +b00000000000000000000000000001001 " +#19 +0! +#20 +1! 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+b00000000000000000000000000101110 " +#93 +0! +#94 +1! +b00000000000000000000000000101111 " +#95 +0! +#96 +1! +b00000000000000000000000000110000 " +#97 +0! +#98 +1! +b00000000000000000000000000110001 " +#99 +0! diff --git a/test_regress/t/t_trace_cat_reopen_fst_part_0100.out b/test_regress/t/t_trace_cat_reopen_fst_part_0100.out new file mode 100644 index 000000000..911261625 --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen_fst_part_0100.out @@ -0,0 +1,247 @@ +$date + Wed Feb 23 00:26:16 2022 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$var wire 1 ! clk $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc [31:0] $end +$var integer 32 # unchanged [31:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#100 +$dumpvars +b00000000000000000000000000101010 # +b00000000000000000000000000110010 " +1! +$end +#101 +0! +#102 +1! +b00000000000000000000000000110011 " +#103 +0! +#104 +1! +b00000000000000000000000000110100 " +#105 +0! +#106 +1! +b00000000000000000000000000110101 " +#107 +0! +#108 +1! +b00000000000000000000000000110110 " +#109 +0! +#110 +1! +b00000000000000000000000000110111 " +#111 +0! +#112 +1! +b00000000000000000000000000111000 " +#113 +0! +#114 +1! +b00000000000000000000000000111001 " +#115 +0! +#116 +1! +b00000000000000000000000000111010 " +#117 +0! +#118 +1! +b00000000000000000000000000111011 " +#119 +0! +#120 +1! +b00000000000000000000000000111100 " +#121 +0! +#122 +1! +b00000000000000000000000000111101 " +#123 +0! +#124 +1! +b00000000000000000000000000111110 " +#125 +0! +#126 +1! +b00000000000000000000000000111111 " +#127 +0! +#128 +1! +b00000000000000000000000001000000 " +#129 +0! +#130 +1! +b00000000000000000000000001000001 " +#131 +0! +#132 +1! +b00000000000000000000000001000010 " +#133 +0! +#134 +1! +b00000000000000000000000001000011 " +#135 +0! +#136 +1! +b00000000000000000000000001000100 " +#137 +0! +#138 +1! +b00000000000000000000000001000101 " +#139 +0! +#140 +1! +b00000000000000000000000001000110 " +#141 +0! +#142 +1! +b00000000000000000000000001000111 " +#143 +0! +#144 +1! +b00000000000000000000000001001000 " +#145 +0! +#146 +1! +b00000000000000000000000001001001 " +#147 +0! +#148 +1! +b00000000000000000000000001001010 " +#149 +0! +#150 +1! +b00000000000000000000000001001011 " +#151 +0! +#152 +1! +b00000000000000000000000001001100 " +#153 +0! +#154 +1! +b00000000000000000000000001001101 " +#155 +0! +#156 +1! +b00000000000000000000000001001110 " +#157 +0! +#158 +1! +b00000000000000000000000001001111 " +#159 +0! +#160 +1! +b00000000000000000000000001010000 " +#161 +0! +#162 +1! +b00000000000000000000000001010001 " +#163 +0! +#164 +1! +b00000000000000000000000001010010 " +#165 +0! +#166 +1! +b00000000000000000000000001010011 " +#167 +0! +#168 +1! +b00000000000000000000000001010100 " +#169 +0! +#170 +1! +b00000000000000000000000001010101 " +#171 +0! +#172 +1! +b00000000000000000000000001010110 " +#173 +0! +#174 +1! +b00000000000000000000000001010111 " +#175 +0! +#176 +1! +b00000000000000000000000001011000 " +#177 +0! +#178 +1! +b00000000000000000000000001011001 " +#179 +0! +#180 +1! +b00000000000000000000000001011010 " +#181 +0! +#182 +1! +b00000000000000000000000001011011 " +#183 +0! +#184 +1! +b00000000000000000000000001011100 " +#185 +0! +#186 +1! +b00000000000000000000000001011101 " +#187 +0! +#188 +1! +b00000000000000000000000001011110 " +#189 +0! diff --git a/test_regress/t/t_trace_cat_reopen_saif.py b/test_regress/t/t_trace_cat_reopen_saif.py new file mode 100755 index 000000000..e1fda3adb --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_cat_common + +test.scenarios('vlt_all') + +trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_reopen_saif_part_0000.out b/test_regress/t/t_trace_cat_reopen_saif_part_0000.out new file mode 100644 index 000000000..b0e5e8900 --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen_saif_part_0000.out @@ -0,0 +1,83 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 99) + (INSTANCE top + (NET + (clk (T0 49) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 100)) + ) + (INSTANCE t + (NET + (clk (T0 49) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 100)) + (cyc\[0\] (T0 50) (T1 49) (TZ 0) (TX 0) (TB 0) (TC 49)) + (cyc\[1\] (T0 51) (T1 48) (TZ 0) (TX 0) (TB 0) (TC 24)) + (cyc\[2\] (T0 51) (T1 48) (TZ 0) (TX 0) (TB 0) (TC 12)) + (cyc\[3\] (T0 51) (T1 48) (TZ 0) (TX 0) (TB 0) (TC 6)) + (cyc\[4\] (T0 64) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 3)) + (cyc\[5\] (T0 64) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 1)) + (cyc\[6\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[7\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[8\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[9\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[10\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[11\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[12\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[13\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[14\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[15\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[16\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[17\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[18\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[19\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[20\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[21\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[22\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[23\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[24\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[25\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[26\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[27\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[28\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[29\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[30\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[31\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[0\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[1\] (T0 0) (T1 99) (TZ 0) (TX 0) (TB 0) (TC 1)) + (unchanged\[2\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[3\] (T0 0) (T1 99) (TZ 0) (TX 0) (TB 0) (TC 1)) + (unchanged\[4\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[5\] (T0 0) (T1 99) (TZ 0) (TX 0) (TB 0) (TC 1)) + (unchanged\[6\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[7\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[8\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[9\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[10\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[11\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[12\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[13\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[14\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[15\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[16\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[17\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[18\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[19\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[20\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[21\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[22\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[23\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[24\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[25\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[26\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[27\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[28\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[29\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[30\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[31\] (T0 99) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + ) +) diff --git a/test_regress/t/t_trace_cat_reopen_saif_part_0100.out b/test_regress/t/t_trace_cat_reopen_saif_part_0100.out new file mode 100644 index 000000000..f615b30c0 --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen_saif_part_0100.out @@ -0,0 +1,83 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 90) + (INSTANCE top + (NET + (clk (T0 45) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 90)) + ) + (INSTANCE t + (NET + (clk (T0 45) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 90)) + (cyc\[0\] (T0 46) (T1 44) (TZ 0) (TX 0) (TB 0) (TC 44)) + (cyc\[1\] (T0 45) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 23)) + (cyc\[2\] (T0 45) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 11)) + (cyc\[3\] (T0 45) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 5)) + (cyc\[4\] (T0 33) (T1 57) (TZ 0) (TX 0) (TB 0) (TC 3)) + (cyc\[5\] (T0 62) (T1 28) (TZ 0) (TX 0) (TB 0) (TC 2)) + (cyc\[6\] (T0 29) (T1 61) (TZ 0) (TX 0) (TB 0) (TC 1)) + (cyc\[7\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[8\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[9\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[10\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[11\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[12\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[13\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[14\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[15\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[16\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[17\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[18\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[19\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[20\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[21\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[22\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[23\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[24\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[25\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[26\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[27\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[28\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[29\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[30\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[31\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[0\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[1\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[2\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[3\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[4\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[5\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[6\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[7\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[8\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[9\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[10\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[11\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[12\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[13\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[14\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[15\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[16\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[17\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[18\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[19\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[20\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[21\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[22\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[23\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[24\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[25\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[26\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[27\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[28\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[29\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[30\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (unchanged\[31\] (T0 90) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + ) +) diff --git a/test_regress/t/t_trace_cat_reopen_vcd.py b/test_regress/t/t_trace_cat_reopen_vcd.py new file mode 100755 index 000000000..e1fda3adb --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_cat_common + +test.scenarios('vlt_all') + +trace_cat_common.run(test) diff --git a/test_regress/t/t_trace_cat_reopen_vcd_part_0000.out b/test_regress/t/t_trace_cat_reopen_vcd_part_0000.out new file mode 100644 index 000000000..4af2c7cad --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen_vcd_part_0000.out @@ -0,0 +1,264 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 " clk $end + $scope module t $end + $var wire 1 " clk $end + $var wire 32 # cyc [31:0] $end + $var wire 32 $ unchanged [31:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +1" +b00000000000000000000000000000000 # +b00000000000000000000000000101010 $ +#1 +0" +#2 +1" +b00000000000000000000000000000001 # +#3 +0" +#4 +1" +b00000000000000000000000000000010 # +#5 +0" +#6 +1" +b00000000000000000000000000000011 # +#7 +0" +#8 +1" +b00000000000000000000000000000100 # +#9 +0" +#10 +1" +b00000000000000000000000000000101 # +#11 +0" +#12 +1" +b00000000000000000000000000000110 # +#13 +0" +#14 +1" +b00000000000000000000000000000111 # +#15 +0" +#16 +1" +b00000000000000000000000000001000 # +#17 +0" +#18 +1" +b00000000000000000000000000001001 # +#19 +0" +#20 +1" +b00000000000000000000000000001010 # +#21 +0" +#22 +1" +b00000000000000000000000000001011 # +#23 +0" +#24 +1" +b00000000000000000000000000001100 # +#25 +0" +#26 +1" +b00000000000000000000000000001101 # +#27 +0" +#28 +1" +b00000000000000000000000000001110 # +#29 +0" +#30 +1" +b00000000000000000000000000001111 # +#31 +0" +#32 +1" +b00000000000000000000000000010000 # +#33 +0" +#34 +1" +b00000000000000000000000000010001 # +#35 +0" +#36 +1" +b00000000000000000000000000010010 # +#37 +0" +#38 +1" +b00000000000000000000000000010011 # +#39 +0" +#40 +1" +b00000000000000000000000000010100 # +#41 +0" +#42 +1" +b00000000000000000000000000010101 # +#43 +0" +#44 +1" +b00000000000000000000000000010110 # +#45 +0" +#46 +1" +b00000000000000000000000000010111 # +#47 +0" +#48 +1" +b00000000000000000000000000011000 # +#49 +0" +#50 +1" +b00000000000000000000000000011001 # +#51 +0" +#52 +1" +b00000000000000000000000000011010 # +#53 +0" +#54 +1" +b00000000000000000000000000011011 # +#55 +0" +#56 +1" +b00000000000000000000000000011100 # +#57 +0" +#58 +1" +b00000000000000000000000000011101 # +#59 +0" +#60 +1" +b00000000000000000000000000011110 # +#61 +0" +#62 +1" +b00000000000000000000000000011111 # +#63 +0" +#64 +1" +b00000000000000000000000000100000 # +#65 +0" +#66 +1" +b00000000000000000000000000100001 # +#67 +0" +#68 +1" +b00000000000000000000000000100010 # +#69 +0" +#70 +1" +b00000000000000000000000000100011 # +#71 +0" +#72 +1" +b00000000000000000000000000100100 # +#73 +0" +#74 +1" +b00000000000000000000000000100101 # +#75 +0" +#76 +1" +b00000000000000000000000000100110 # +#77 +0" +#78 +1" +b00000000000000000000000000100111 # +#79 +0" +#80 +1" +b00000000000000000000000000101000 # +#81 +0" +#82 +1" +b00000000000000000000000000101001 # +#83 +0" +#84 +1" +b00000000000000000000000000101010 # +#85 +0" +#86 +1" +b00000000000000000000000000101011 # +#87 +0" +#88 +1" +b00000000000000000000000000101100 # +#89 +0" +#90 +1" +b00000000000000000000000000101101 # +#91 +0" +#92 +1" +b00000000000000000000000000101110 # +#93 +0" +#94 +1" +b00000000000000000000000000101111 # +#95 +0" +#96 +1" +b00000000000000000000000000110000 # +#97 +0" +#98 +1" +b00000000000000000000000000110001 # +#99 +0" diff --git a/test_regress/t/t_trace_cat_reopen_vcd_part_0100.out b/test_regress/t/t_trace_cat_reopen_vcd_part_0100.out new file mode 100644 index 000000000..4cca416fe --- /dev/null +++ b/test_regress/t/t_trace_cat_reopen_vcd_part_0100.out @@ -0,0 +1,239 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 " clk $end + $scope module t $end + $var wire 1 " clk $end + $var wire 32 # cyc [31:0] $end + $var wire 32 $ unchanged [31:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#100 +1" +b00000000000000000000000000110010 # +b00000000000000000000000000101010 $ +#101 +0" +#102 +1" +b00000000000000000000000000110011 # +#103 +0" +#104 +1" +b00000000000000000000000000110100 # +#105 +0" +#106 +1" +b00000000000000000000000000110101 # +#107 +0" +#108 +1" +b00000000000000000000000000110110 # +#109 +0" +#110 +1" +b00000000000000000000000000110111 # +#111 +0" +#112 +1" +b00000000000000000000000000111000 # +#113 +0" +#114 +1" +b00000000000000000000000000111001 # +#115 +0" +#116 +1" +b00000000000000000000000000111010 # +#117 +0" +#118 +1" +b00000000000000000000000000111011 # +#119 +0" +#120 +1" +b00000000000000000000000000111100 # +#121 +0" +#122 +1" +b00000000000000000000000000111101 # +#123 +0" +#124 +1" +b00000000000000000000000000111110 # +#125 +0" +#126 +1" +b00000000000000000000000000111111 # +#127 +0" +#128 +1" +b00000000000000000000000001000000 # +#129 +0" +#130 +1" +b00000000000000000000000001000001 # +#131 +0" +#132 +1" +b00000000000000000000000001000010 # +#133 +0" +#134 +1" +b00000000000000000000000001000011 # +#135 +0" +#136 +1" +b00000000000000000000000001000100 # +#137 +0" +#138 +1" +b00000000000000000000000001000101 # +#139 +0" +#140 +1" +b00000000000000000000000001000110 # +#141 +0" +#142 +1" +b00000000000000000000000001000111 # +#143 +0" +#144 +1" +b00000000000000000000000001001000 # +#145 +0" +#146 +1" +b00000000000000000000000001001001 # +#147 +0" +#148 +1" +b00000000000000000000000001001010 # +#149 +0" +#150 +1" +b00000000000000000000000001001011 # +#151 +0" +#152 +1" +b00000000000000000000000001001100 # +#153 +0" +#154 +1" +b00000000000000000000000001001101 # +#155 +0" +#156 +1" +b00000000000000000000000001001110 # +#157 +0" +#158 +1" +b00000000000000000000000001001111 # +#159 +0" +#160 +1" +b00000000000000000000000001010000 # +#161 +0" +#162 +1" +b00000000000000000000000001010001 # +#163 +0" +#164 +1" +b00000000000000000000000001010010 # +#165 +0" +#166 +1" +b00000000000000000000000001010011 # +#167 +0" +#168 +1" +b00000000000000000000000001010100 # +#169 +0" +#170 +1" +b00000000000000000000000001010101 # +#171 +0" +#172 +1" +b00000000000000000000000001010110 # +#173 +0" +#174 +1" +b00000000000000000000000001010111 # +#175 +0" +#176 +1" +b00000000000000000000000001011000 # +#177 +0" +#178 +1" +b00000000000000000000000001011001 # +#179 +0" +#180 +1" +b00000000000000000000000001011010 # +#181 +0" +#182 +1" +b00000000000000000000000001011011 # +#183 +0" +#184 +1" +b00000000000000000000000001011100 # +#185 +0" +#186 +1" +b00000000000000000000000001011101 # +#187 +0" +#188 +1" +b00000000000000000000000001011110 # +#189 +0" diff --git a/test_regress/t/t_trace_complex.py b/test_regress/t/t_trace_complex.py deleted file mode 100755 index 87beec445..000000000 --- a/test_regress/t/t_trace_complex.py +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=['--cc --trace-vcd']) - -test.execute() - -test.file_grep(test.trace_filename, r' v_arrp ') -test.file_grep(test.trace_filename, r' v_arrp_arrp ') -test.file_grep(test.trace_filename, r' v_arrp_strp ') -test.file_grep(test.trace_filename, r' v_arru\[') -test.file_grep(test.trace_filename, r' v_arru_arrp\[') -test.file_grep(test.trace_filename, r' v_arru_arru\[') -test.file_grep(test.trace_filename, r' v_arru_strp\[') -test.file_grep(test.trace_filename, r' v_strp ') -test.file_grep(test.trace_filename, r' v_strp_strp ') - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_fst.out b/test_regress/t/t_trace_complex_default_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_complex_fst.out rename to test_regress/t/t_trace_complex_default_cc_fst.out diff --git a/test_regress/t/t_trace_complex_default_cc_fst.py b/test_regress/t/t_trace_complex_default_cc_fst.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_hier_block_trace_saif_noinl.py b/test_regress/t/t_trace_complex_default_cc_fst_noinl.py similarity index 82% rename from test_regress/t/t_hier_block_trace_saif_noinl.py rename to test_regress/t/t_trace_complex_default_cc_fst_noinl.py index c0f5f7f86..b929c69bc 100755 --- a/test_regress/t/t_hier_block_trace_saif_noinl.py +++ b/test_regress/t/t_trace_complex_default_cc_fst_noinl.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_complex_common -import runpy - -test.priority(30) test.scenarios('vlt_all') -runpy.run_path("t/t_hier_block_trace_saif.py", globals()) +trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_default_cc_fst_threads_1.py b/test_regress/t/t_trace_complex_default_cc_fst_threads_1.py new file mode 100755 index 000000000..8b4cfe063 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_cc_fst_threads_1.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_complex_default_cc_fst_threads_2.py b/test_regress/t/t_trace_complex_default_cc_fst_threads_2.py new file mode 100755 index 000000000..8afc840b9 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_cc_fst_threads_2.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["--trace-threads", "2"]) diff --git a/test_regress/t/t_trace_complex_params_saif.out b/test_regress/t/t_trace_complex_default_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_complex_params_saif.out rename to test_regress/t/t_trace_complex_default_cc_saif.out diff --git a/test_regress/t/t_trace_complex_default_cc_saif.py b/test_regress/t/t_trace_complex_default_cc_saif.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_hier_block_trace_saif_notop.py b/test_regress/t/t_trace_complex_default_cc_saif_noinl.py similarity index 82% rename from test_regress/t/t_hier_block_trace_saif_notop.py rename to test_regress/t/t_trace_complex_default_cc_saif_noinl.py index c0f5f7f86..b929c69bc 100755 --- a/test_regress/t/t_hier_block_trace_saif_notop.py +++ b/test_regress/t/t_trace_complex_default_cc_saif_noinl.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_complex_common -import runpy - -test.priority(30) test.scenarios('vlt_all') -runpy.run_path("t/t_hier_block_trace_saif.py", globals()) +trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_default_cc_saif_threads_1.py b/test_regress/t/t_trace_complex_default_cc_saif_threads_1.py new file mode 100755 index 000000000..8b4cfe063 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_cc_saif_threads_1.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_complex.out b/test_regress/t/t_trace_complex_default_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_complex.out rename to test_regress/t/t_trace_complex_default_cc_vcd.out diff --git a/test_regress/t/t_trace_complex_default_cc_vcd.py b/test_regress/t/t_trace_complex_default_cc_vcd.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_default_cc_vcd_noinl.py b/test_regress/t/t_trace_complex_default_cc_vcd_noinl.py new file mode 100755 index 000000000..b929c69bc --- /dev/null +++ b/test_regress/t/t_trace_complex_default_cc_vcd_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_default_cc_vcd_portable.py b/test_regress/t/t_trace_complex_default_cc_vcd_portable.py new file mode 100755 index 000000000..8df18bc02 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_cc_vcd_portable.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_PORTABLE_ONLY"]) diff --git a/test_regress/t/t_trace_complex_default_cc_vcd_threads_1.py b/test_regress/t/t_trace_complex_default_cc_vcd_threads_1.py new file mode 100755 index 000000000..8b4cfe063 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_cc_vcd_threads_1.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_complex_fst_sc.out b/test_regress/t/t_trace_complex_default_sc_fst.out similarity index 100% rename from test_regress/t/t_trace_complex_fst_sc.out rename to test_regress/t/t_trace_complex_default_sc_fst.out diff --git a/test_regress/t/t_trace_complex_default_sc_fst.py b/test_regress/t/t_trace_complex_default_sc_fst.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_sc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_default_sc_fst_threads_1.py b/test_regress/t/t_trace_complex_default_sc_fst_threads_1.py new file mode 100755 index 000000000..8b4cfe063 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_sc_fst_threads_1.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_complex_default_sc_fst_threads_2.py b/test_regress/t/t_trace_complex_default_sc_fst_threads_2.py new file mode 100755 index 000000000..8afc840b9 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_sc_fst_threads_2.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["--trace-threads", "2"]) diff --git a/test_regress/t/t_trace_complex_default_sc_vcd.out b/test_regress/t/t_trace_complex_default_sc_vcd.out new file mode 100644 index 000000000..c894c8109 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_sc_vcd.out @@ -0,0 +1,224 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $scope module $unit $end + $var wire 1 " global_bit $end + $upscope $end + $scope module t $end + $var wire 1 : clk $end + $var wire 32 # cyc [31:0] $end + $var wire 2 $ v_strp [1:0] $end + $var wire 4 % v_strp_strp [3:0] $end + $var wire 2 & v_unip_strp [1:0] $end + $var wire 2 ' v_arrp [2:1] $end + $var wire 4 ( v_arrp_arrp [3:0] $end + $var wire 4 ) v_arrp_strp [3:0] $end + $var wire 1 ; v_arru[2] $end + $var wire 1 < v_arru[1] $end + $var wire 1 = v_arru_arru[4][2] $end + $var wire 1 > v_arru_arru[4][1] $end + $var wire 1 ? v_arru_arru[3][2] $end + $var wire 1 @ v_arru_arru[3][1] $end + $var wire 2 * v_arru_arrp[4] [2:1] $end + $var wire 2 + v_arru_arrp[3] [2:1] $end + $var wire 2 , v_arru_strp[4] [1:0] $end + $var wire 2 - v_arru_strp[3] [1:0] $end + $var real 64 . v_real $end + $var real 64 0 v_arr_real[0] $end + $var real 64 2 v_arr_real[1] $end + $var wire 64 A v_chandle [63:0] $end + $var wire 64 4 v_str32x2 [63:0] $end + $var wire 32 6 v_enumed [31:0] $end + $var wire 32 7 v_enumed2 [31:0] $end + $var wire 3 8 v_enumb [2:0] $end + $var wire 6 9 v_enumb2_str [5:0] $end + $var wire 8 C unpacked_array[-2] [7:0] $end + $var wire 8 D unpacked_array[-1] [7:0] $end + $var wire 8 E unpacked_array[0] [7:0] $end + $var wire 1 F LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end + $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end + $var wire 32 G PARAM [31:0] $end + $upscope $end + $scope module p2 $end + $var wire 32 H PARAM [31:0] $end + $upscope $end + $scope module p3 $end + $var wire 32 I PARAM [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +1" +b00000000000000000000000000000000 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +r0 . +r0 0 +r0 2 +b0000000000000000000000000000000000000000000000000000000011111111 4 +b00000000000000000000000000000000 6 +b00000000000000000000000000000000 7 +b000 8 +b000000 9 +0: +0; +0< +0= +0> +0? +0@ +b0000000000000000000000000000000000000000000000000000000000000000 A +b00000000 C +b00000000 D +b00000000 E +0F +b00000000000000000000000000000100 G +b00000000000000000000000000000010 H +b00000000000000000000000000000011 I +#10 +b00000000000000000000000000000001 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +r0.1 . +r0.2 0 +r0.3 2 +b0000000000000000000000000000000100000000000000000000000011111110 4 +b00000000000000000000000000000001 6 +b00000000000000000000000000000010 7 +b111 8 +1: +#15 +0: +#20 +b00000000000000000000000000000010 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +r0.2 . +r0.4 0 +r0.6 2 +b0000000000000000000000000000001000000000000000000000000011111101 4 +b00000000000000000000000000000010 6 +b00000000000000000000000000000100 7 +b110 8 +b111111 9 +1: +#25 +0: +#30 +b00000000000000000000000000000011 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +r0.3 . +r0.6000000000000001 0 +r0.8999999999999999 2 +b0000000000000000000000000000001100000000000000000000000011111100 4 +b00000000000000000000000000000011 6 +b00000000000000000000000000000110 7 +b101 8 +b110110 9 +1: +#35 +0: +#40 +b00000000000000000000000000000100 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +r0.4 . +r0.8 0 +r1.2 2 +b0000000000000000000000000000010000000000000000000000000011111011 4 +b00000000000000000000000000000100 6 +b00000000000000000000000000001000 7 +b100 8 +b101101 9 +1: +#45 +0: +#50 +b00000000000000000000000000000101 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +r0.5 . +r1 0 +r1.5 2 +b0000000000000000000000000000010100000000000000000000000011111010 4 +b00000000000000000000000000000101 6 +b00000000000000000000000000001010 7 +b011 8 +b100100 9 +1: +#55 +0: +#60 +b00000000000000000000000000000110 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +r0.6 . +r1.2 0 +r1.8 2 +b0000000000000000000000000000011000000000000000000000000011111001 4 +b00000000000000000000000000000110 6 +b00000000000000000000000000001100 7 +b010 8 +b011011 9 +1: +#64 diff --git a/test_regress/t/t_trace_complex_default_sc_vcd.py b/test_regress/t/t_trace_complex_default_sc_vcd.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_default_sc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_fst.py b/test_regress/t/t_trace_complex_fst.py deleted file mode 100755 index 567b30c42..000000000 --- a/test_regress/t/t_trace_complex_fst.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -test.compile(verilator_flags2=['--cc --trace-fst']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_fst_sc.py b/test_regress/t/t_trace_complex_fst_sc.py deleted file mode 100755 index fbdc3d473..000000000 --- a/test_regress/t/t_trace_complex_fst_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-fst']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_1.py b/test_regress/t/t_trace_complex_fst_threads_1.py deleted file mode 100755 index 2c3d0187b..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_1.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_fst.out" - -test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 1']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_1_sc.py b/test_regress/t/t_trace_complex_fst_threads_1_sc.py deleted file mode 100755 index a5a8d1e23..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_1_sc.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_fst_sc.out" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 1']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_2.py b/test_regress/t/t_trace_complex_fst_threads_2.py deleted file mode 100755 index b42042c4c..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_2.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_fst.out" - -test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 2']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_fst_threads_2_sc.py b/test_regress/t/t_trace_complex_fst_threads_2_sc.py deleted file mode 100755 index 45c71b135..000000000 --- a/test_regress/t/t_trace_complex_fst_threads_2_sc.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_fst_sc.out" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 2']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_noinl.py b/test_regress/t/t_trace_complex_noinl.py deleted file mode 100755 index bad63ffb6..000000000 --- a/test_regress/t/t_trace_complex_noinl.py +++ /dev/null @@ -1,33 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.top_filename = "t/t_trace_complex.v" - -test.compile(verilator_flags2=['--cc --trace-vcd -fno-inline']) - -test.execute() - -test.file_grep(test.trace_filename, r' v_arrp ') -test.file_grep(test.trace_filename, r' v_arrp_arrp ') -test.file_grep(test.trace_filename, r' v_arrp_strp ') -test.file_grep(test.trace_filename, r' v_arru\[') -test.file_grep(test.trace_filename, r' v_arru_arrp\[') -test.file_grep(test.trace_filename, r' v_arru_arru\[') -test.file_grep(test.trace_filename, r' v_arru_strp\[') -test.file_grep(test.trace_filename, r' v_strp ') -test.file_grep(test.trace_filename, r' v_strp_strp ') - -# Should match with module inlining -test.vcd_identical(test.trace_filename, "t/t_trace_complex.out") - -test.passes() diff --git a/test_regress/t/t_trace_complex_params.py b/test_regress/t/t_trace_complex_params.py deleted file mode 100755 index ddec49bd7..000000000 --- a/test_regress/t/t_trace_complex_params.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -test.compile(verilator_flags2=['--cc --trace-vcd --no-trace-structs --trace-params']) - -test.execute() - -test.file_grep(test.trace_filename, r' PARAM ') - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_params_fst.out b/test_regress/t/t_trace_complex_params_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_complex_params_fst.out rename to test_regress/t/t_trace_complex_params_cc_fst.out diff --git a/test_regress/t/t_trace_complex_params_cc_fst.py b/test_regress/t/t_trace_complex_params_cc_fst.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_params_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_params_cc_fst_noinl.py b/test_regress/t/t_trace_complex_params_cc_fst_noinl.py new file mode 100755 index 000000000..b929c69bc --- /dev/null +++ b/test_regress/t/t_trace_complex_params_cc_fst_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_saif.out b/test_regress/t/t_trace_complex_params_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_complex_saif.out rename to test_regress/t/t_trace_complex_params_cc_saif.out diff --git a/test_regress/t/t_trace_complex_params_cc_saif.py b/test_regress/t/t_trace_complex_params_cc_saif.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_params_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_params_cc_saif_noinl.py b/test_regress/t/t_trace_complex_params_cc_saif_noinl.py new file mode 100755 index 000000000..b929c69bc --- /dev/null +++ b/test_regress/t/t_trace_complex_params_cc_saif_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_params.out b/test_regress/t/t_trace_complex_params_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_complex_params.out rename to test_regress/t/t_trace_complex_params_cc_vcd.out diff --git a/test_regress/t/t_trace_complex_params_cc_vcd.py b/test_regress/t/t_trace_complex_params_cc_vcd.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_params_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_params_cc_vcd_noinl.py b/test_regress/t/t_trace_complex_params_cc_vcd_noinl.py new file mode 100755 index 000000000..b929c69bc --- /dev/null +++ b/test_regress/t/t_trace_complex_params_cc_vcd_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_params_fst.py b/test_regress/t/t_trace_complex_params_fst.py deleted file mode 100755 index fe5593c75..000000000 --- a/test_regress/t/t_trace_complex_params_fst.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -test.compile(verilator_flags2=['--cc --trace-fst --no-trace-structs --trace-params']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_params_fst_sc.py b/test_regress/t/t_trace_complex_params_fst_sc.py deleted file mode 100755 index 5acecde14..000000000 --- a/test_regress/t/t_trace_complex_params_fst_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-fst --no-trace-structs --trace-params']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_params_saif.py b/test_regress/t/t_trace_complex_params_saif.py deleted file mode 100755 index 215b0e646..000000000 --- a/test_regress/t/t_trace_complex_params_saif.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_params_saif.out" - -test.compile(verilator_flags2=['--cc --trace-saif --no-trace-structs --trace-params']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_params_fst_sc.out b/test_regress/t/t_trace_complex_params_sc_fst.out similarity index 100% rename from test_regress/t/t_trace_complex_params_fst_sc.out rename to test_regress/t/t_trace_complex_params_sc_fst.out diff --git a/test_regress/t/t_trace_complex_params_sc_fst.py b/test_regress/t/t_trace_complex_params_sc_fst.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_params_sc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_params_sc_vcd.out b/test_regress/t/t_trace_complex_params_sc_vcd.out new file mode 100644 index 000000000..c894c8109 --- /dev/null +++ b/test_regress/t/t_trace_complex_params_sc_vcd.out @@ -0,0 +1,224 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $scope module $unit $end + $var wire 1 " global_bit $end + $upscope $end + $scope module t $end + $var wire 1 : clk $end + $var wire 32 # cyc [31:0] $end + $var wire 2 $ v_strp [1:0] $end + $var wire 4 % v_strp_strp [3:0] $end + $var wire 2 & v_unip_strp [1:0] $end + $var wire 2 ' v_arrp [2:1] $end + $var wire 4 ( v_arrp_arrp [3:0] $end + $var wire 4 ) v_arrp_strp [3:0] $end + $var wire 1 ; v_arru[2] $end + $var wire 1 < v_arru[1] $end + $var wire 1 = v_arru_arru[4][2] $end + $var wire 1 > v_arru_arru[4][1] $end + $var wire 1 ? v_arru_arru[3][2] $end + $var wire 1 @ v_arru_arru[3][1] $end + $var wire 2 * v_arru_arrp[4] [2:1] $end + $var wire 2 + v_arru_arrp[3] [2:1] $end + $var wire 2 , v_arru_strp[4] [1:0] $end + $var wire 2 - v_arru_strp[3] [1:0] $end + $var real 64 . v_real $end + $var real 64 0 v_arr_real[0] $end + $var real 64 2 v_arr_real[1] $end + $var wire 64 A v_chandle [63:0] $end + $var wire 64 4 v_str32x2 [63:0] $end + $var wire 32 6 v_enumed [31:0] $end + $var wire 32 7 v_enumed2 [31:0] $end + $var wire 3 8 v_enumb [2:0] $end + $var wire 6 9 v_enumb2_str [5:0] $end + $var wire 8 C unpacked_array[-2] [7:0] $end + $var wire 8 D unpacked_array[-1] [7:0] $end + $var wire 8 E unpacked_array[0] [7:0] $end + $var wire 1 F LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end + $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end + $var wire 32 G PARAM [31:0] $end + $upscope $end + $scope module p2 $end + $var wire 32 H PARAM [31:0] $end + $upscope $end + $scope module p3 $end + $var wire 32 I PARAM [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +1" +b00000000000000000000000000000000 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +r0 . +r0 0 +r0 2 +b0000000000000000000000000000000000000000000000000000000011111111 4 +b00000000000000000000000000000000 6 +b00000000000000000000000000000000 7 +b000 8 +b000000 9 +0: +0; +0< +0= +0> +0? +0@ +b0000000000000000000000000000000000000000000000000000000000000000 A +b00000000 C +b00000000 D +b00000000 E +0F +b00000000000000000000000000000100 G +b00000000000000000000000000000010 H +b00000000000000000000000000000011 I +#10 +b00000000000000000000000000000001 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +r0.1 . +r0.2 0 +r0.3 2 +b0000000000000000000000000000000100000000000000000000000011111110 4 +b00000000000000000000000000000001 6 +b00000000000000000000000000000010 7 +b111 8 +1: +#15 +0: +#20 +b00000000000000000000000000000010 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +r0.2 . +r0.4 0 +r0.6 2 +b0000000000000000000000000000001000000000000000000000000011111101 4 +b00000000000000000000000000000010 6 +b00000000000000000000000000000100 7 +b110 8 +b111111 9 +1: +#25 +0: +#30 +b00000000000000000000000000000011 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +r0.3 . +r0.6000000000000001 0 +r0.8999999999999999 2 +b0000000000000000000000000000001100000000000000000000000011111100 4 +b00000000000000000000000000000011 6 +b00000000000000000000000000000110 7 +b101 8 +b110110 9 +1: +#35 +0: +#40 +b00000000000000000000000000000100 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +r0.4 . +r0.8 0 +r1.2 2 +b0000000000000000000000000000010000000000000000000000000011111011 4 +b00000000000000000000000000000100 6 +b00000000000000000000000000001000 7 +b100 8 +b101101 9 +1: +#45 +0: +#50 +b00000000000000000000000000000101 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +r0.5 . +r1 0 +r1.5 2 +b0000000000000000000000000000010100000000000000000000000011111010 4 +b00000000000000000000000000000101 6 +b00000000000000000000000000001010 7 +b011 8 +b100100 9 +1: +#55 +0: +#60 +b00000000000000000000000000000110 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +r0.6 . +r1.2 0 +r1.8 2 +b0000000000000000000000000000011000000000000000000000000011111001 4 +b00000000000000000000000000000110 6 +b00000000000000000000000000001100 7 +b010 8 +b011011 9 +1: +#64 diff --git a/test_regress/t/t_trace_complex_params_sc_vcd.py b/test_regress/t/t_trace_complex_params_sc_vcd.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_params_sc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_portable.py b/test_regress/t/t_trace_complex_portable.py deleted file mode 100755 index f6e5795de..000000000 --- a/test_regress/t/t_trace_complex_portable.py +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Same test as t_trace_complex, but exercising the old VCD tracing API - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex.out" - -test.compile(verilator_flags2=['--cc --trace-vcd -CFLAGS -DVL_PORTABLE_ONLY']) - -test.execute() - -test.file_grep(test.trace_filename, r' v_strp ') -test.file_grep(test.trace_filename, r' v_strp_strp ') -test.file_grep(test.trace_filename, r' v_arrp ') -test.file_grep(test.trace_filename, r' v_arrp_arrp ') -test.file_grep(test.trace_filename, r' v_arrp_strp ') -test.file_grep(test.trace_filename, r' v_arru\[') -test.file_grep(test.trace_filename, r' v_arru_arru\[') -test.file_grep(test.trace_filename, r' v_arru_arrp\[') -test.file_grep(test.trace_filename, r' v_arru_strp\[') - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_saif.py b/test_regress/t/t_trace_complex_saif.py deleted file mode 100755 index a86cedd9d..000000000 --- a/test_regress/t/t_trace_complex_saif.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_saif.out" - -test.compile(verilator_flags2=['--cc --trace-saif']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_saif_threads_1.py b/test_regress/t/t_trace_complex_saif_threads_1.py deleted file mode 100755 index 447762c07..000000000 --- a/test_regress/t/t_trace_complex_saif_threads_1.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_saif.out" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_saif_threads_2.py b/test_regress/t/t_trace_complex_saif_threads_2.py deleted file mode 100755 index 2c60ab1b4..000000000 --- a/test_regress/t/t_trace_complex_saif_threads_2.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_saif.out" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_structs.py b/test_regress/t/t_trace_complex_structs.py deleted file mode 100755 index dea6069d6..000000000 --- a/test_regress/t/t_trace_complex_structs.py +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -test.compile(verilator_flags2=['--cc --trace-vcd --trace-structs --no-trace-params']) - -test.execute() - -test.file_grep(test.trace_filename, r' v_strp ') -test.file_grep(test.trace_filename, r' v_strp_strp ') -test.file_grep(test.trace_filename, r' v_arrp ') -test.file_grep_not(test.trace_filename, r' v_arrp_arrp ') -test.file_grep_not(test.trace_filename, r' v_arrp_strp ') -test.file_grep(test.trace_filename, r' v_arru\[') -test.file_grep(test.trace_filename, r' v_arru_arru\[') -test.file_grep(test.trace_filename, r' v_arru_arrp\[') -test.file_grep(test.trace_filename, r' v_arru_strp\[') - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_structs_fst.out b/test_regress/t/t_trace_complex_structs_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_complex_structs_fst.out rename to test_regress/t/t_trace_complex_structs_cc_fst.out diff --git a/test_regress/t/t_trace_complex_structs_cc_fst.py b/test_regress/t/t_trace_complex_structs_cc_fst.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_structs_cc_fst_noinl.py b/test_regress/t/t_trace_complex_structs_cc_fst_noinl.py new file mode 100755 index 000000000..b929c69bc --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_cc_fst_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_structs_saif.out b/test_regress/t/t_trace_complex_structs_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_complex_structs_saif.out rename to test_regress/t/t_trace_complex_structs_cc_saif.out diff --git a/test_regress/t/t_trace_complex_structs_cc_saif.py b/test_regress/t/t_trace_complex_structs_cc_saif.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_structs_cc_saif_noinl.py b/test_regress/t/t_trace_complex_structs_cc_saif_noinl.py new file mode 100755 index 000000000..b929c69bc --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_cc_saif_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_structs.out b/test_regress/t/t_trace_complex_structs_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_complex_structs.out rename to test_regress/t/t_trace_complex_structs_cc_vcd.out diff --git a/test_regress/t/t_trace_complex_structs_cc_vcd.py b/test_regress/t/t_trace_complex_structs_cc_vcd.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_structs_cc_vcd_noinl.py b/test_regress/t/t_trace_complex_structs_cc_vcd_noinl.py new file mode 100755 index 000000000..b929c69bc --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_cc_vcd_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_complex_structs_fst.py b/test_regress/t/t_trace_complex_structs_fst.py deleted file mode 100755 index 52bc52e69..000000000 --- a/test_regress/t/t_trace_complex_structs_fst.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -test.compile(verilator_flags2=['--cc --trace-fst --trace-structs --no-trace-params']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.py b/test_regress/t/t_trace_complex_structs_fst_sc.py deleted file mode 100755 index b0c72da72..000000000 --- a/test_regress/t/t_trace_complex_structs_fst_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=['--sc --trace-fst --trace-structs --no-trace-params']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_structs_saif.py b/test_regress/t/t_trace_complex_structs_saif.py deleted file mode 100755 index ce4cc3b42..000000000 --- a/test_regress/t/t_trace_complex_structs_saif.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex_structs_saif.out" - -test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --no-trace-params']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.out b/test_regress/t/t_trace_complex_structs_sc_fst.out similarity index 100% rename from test_regress/t/t_trace_complex_structs_fst_sc.out rename to test_regress/t/t_trace_complex_structs_sc_fst.out diff --git a/test_regress/t/t_trace_complex_structs_sc_fst.py b/test_regress/t/t_trace_complex_structs_sc_fst.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_sc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_structs_sc_vcd.out b/test_regress/t/t_trace_complex_structs_sc_vcd.out new file mode 100644 index 000000000..de976b476 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_sc_vcd.out @@ -0,0 +1,345 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $scope module $unit $end + $var wire 1 " global_bit $end + $upscope $end + $scope module t $end + $var wire 1 F clk $end + $var wire 32 # cyc [31:0] $end + $scope module v_strp $end + $var wire 1 $ b1 $end + $var wire 1 % b0 $end + $upscope $end + $scope module v_strp_strp $end + $scope module x1 $end + $var wire 1 & b1 $end + $var wire 1 ' b0 $end + $upscope $end + $scope module x0 $end + $var wire 1 ( b1 $end + $var wire 1 ) b0 $end + $upscope $end + $upscope $end + $scope module v_unip_strp $end + $scope module x1 $end + $var wire 1 * b1 $end + $var wire 1 + b0 $end + $upscope $end + $scope module x0 $end + $var wire 1 * b1 $end + $var wire 1 + b0 $end + $upscope $end + $upscope $end + $var wire 2 , v_arrp [2:1] $end + $var wire 2 - v_arrp_arrp[4] [2:1] $end + $var wire 2 . v_arrp_arrp[3] [2:1] $end + $scope module v_arrp_strp[4] $end + $var wire 1 / b1 $end + $var wire 1 0 b0 $end + $upscope $end + $scope module v_arrp_strp[3] $end + $var wire 1 1 b1 $end + $var wire 1 2 b0 $end + $upscope $end + $var wire 1 G v_arru[2] $end + $var wire 1 H v_arru[1] $end + $var wire 1 I v_arru_arru[4][2] $end + $var wire 1 J v_arru_arru[4][1] $end + $var wire 1 K v_arru_arru[3][2] $end + $var wire 1 L v_arru_arru[3][1] $end + $var wire 2 3 v_arru_arrp[4] [2:1] $end + $var wire 2 4 v_arru_arrp[3] [2:1] $end + $scope module v_arru_strp[4] $end + $var wire 1 5 b1 $end + $var wire 1 6 b0 $end + $upscope $end + $scope module v_arru_strp[3] $end + $var wire 1 7 b1 $end + $var wire 1 8 b0 $end + $upscope $end + $var real 64 9 v_real $end + $var real 64 ; v_arr_real[0] $end + $var real 64 = v_arr_real[1] $end + $var wire 64 M v_chandle [63:0] $end + $scope module v_str32x2[1] $end + $var wire 32 ? data [31:0] $end + $upscope $end + $scope module v_str32x2[0] $end + $var wire 32 @ data [31:0] $end + $upscope $end + $var wire 32 A v_enumed [31:0] $end + $var wire 32 B v_enumed2 [31:0] $end + $var wire 3 C v_enumb [2:0] $end + $scope module v_enumb2_str $end + $var wire 3 D a [2:0] $end + $var wire 3 E b [2:0] $end + $upscope $end + $var wire 8 O unpacked_array[-2] [7:0] $end + $var wire 8 P unpacked_array[-1] [7:0] $end + $var wire 8 Q unpacked_array[0] [7:0] $end + $var wire 1 R LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +1" +b00000000000000000000000000000000 # +0$ +0% +0& +0' +0( +0) +0* +0+ +b00 , +b00 - +b00 . +0/ +00 +01 +02 +b00 3 +b00 4 +05 +06 +07 +08 +r0 9 +r0 ; +r0 = +b00000000000000000000000000000000 ? +b00000000000000000000000011111111 @ +b00000000000000000000000000000000 A +b00000000000000000000000000000000 B +b000 C +b000 D +b000 E +0F +0G +0H +0I +0J +0K +0L +b0000000000000000000000000000000000000000000000000000000000000000 M +b00000000 O +b00000000 P +b00000000 Q +0R +#10 +b00000000000000000000000000000001 # +1$ +1% +1& +1' +1( +1) +1* +1+ +b11 , +b11 - +b11 . +1/ +10 +11 +12 +b11 3 +b11 4 +15 +16 +17 +18 +r0.1 9 +r0.2 ; +r0.3 = +b00000000000000000000000000000001 ? +b00000000000000000000000011111110 @ +b00000000000000000000000000000001 A +b00000000000000000000000000000010 B +b111 C +1F +#15 +0F +#20 +b00000000000000000000000000000010 # +0$ +0% +0& +0' +0( +0) +0* +0+ +b00 , +b00 - +b00 . +0/ +00 +01 +02 +b00 3 +b00 4 +05 +06 +07 +08 +r0.2 9 +r0.4 ; +r0.6 = +b00000000000000000000000000000010 ? +b00000000000000000000000011111101 @ +b00000000000000000000000000000010 A +b00000000000000000000000000000100 B +b110 C +b111 D +b111 E +1F +#25 +0F +#30 +b00000000000000000000000000000011 # +1$ +1% +1& +1' +1( +1) +1* +1+ +b11 , +b11 - +b11 . +1/ +10 +11 +12 +b11 3 +b11 4 +15 +16 +17 +18 +r0.3 9 +r0.6000000000000001 ; +r0.8999999999999999 = +b00000000000000000000000000000011 ? +b00000000000000000000000011111100 @ +b00000000000000000000000000000011 A +b00000000000000000000000000000110 B +b101 C +b110 D +b110 E +1F +#35 +0F +#40 +b00000000000000000000000000000100 # +0$ +0% +0& +0' +0( +0) +0* +0+ +b00 , +b00 - +b00 . +0/ +00 +01 +02 +b00 3 +b00 4 +05 +06 +07 +08 +r0.4 9 +r0.8 ; +r1.2 = +b00000000000000000000000000000100 ? +b00000000000000000000000011111011 @ +b00000000000000000000000000000100 A +b00000000000000000000000000001000 B +b100 C +b101 D +b101 E +1F +#45 +0F +#50 +b00000000000000000000000000000101 # +1$ +1% +1& +1' +1( +1) +1* +1+ +b11 , +b11 - +b11 . +1/ +10 +11 +12 +b11 3 +b11 4 +15 +16 +17 +18 +r0.5 9 +r1 ; +r1.5 = +b00000000000000000000000000000101 ? +b00000000000000000000000011111010 @ +b00000000000000000000000000000101 A +b00000000000000000000000000001010 B +b011 C +b100 D +b100 E +1F +#55 +0F +#60 +b00000000000000000000000000000110 # +0$ +0% +0& +0' +0( +0) +0* +0+ +b00 , +b00 - +b00 . +0/ +00 +01 +02 +b00 3 +b00 4 +05 +06 +07 +08 +r0.6 9 +r1.2 ; +r1.8 = +b00000000000000000000000000000110 ? +b00000000000000000000000011111001 @ +b00000000000000000000000000000110 A +b00000000000000000000000000001100 B +b010 C +b011 D +b011 E +1F +#64 diff --git a/test_regress/t/t_trace_complex_structs_sc_vcd.py b/test_regress/t/t_trace_complex_structs_sc_vcd.py new file mode 100755 index 000000000..13a12d3b1 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_sc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_complex_common + +test.scenarios('vlt_all') + +trace_complex_common.run(test) diff --git a/test_regress/t/t_trace_complex_threads_1.py b/test_regress/t/t_trace_complex_threads_1.py deleted file mode 100755 index 54ac16149..000000000 --- a/test_regress/t/t_trace_complex_threads_1.py +++ /dev/null @@ -1,32 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_complex.v" -test.golden_filename = "t/t_trace_complex.out" - -test.compile(verilator_flags2=['--cc --trace-vcd --trace-threads 1']) - -test.execute() - -test.file_grep(test.trace_filename, r' v_strp ') -test.file_grep(test.trace_filename, r' v_strp_strp ') -test.file_grep(test.trace_filename, r' v_arrp ') -test.file_grep(test.trace_filename, r' v_arrp_arrp ') -test.file_grep(test.trace_filename, r' v_arrp_strp ') -test.file_grep(test.trace_filename, r' v_arru\[') -test.file_grep(test.trace_filename, r' v_arru_arru\[') -test.file_grep(test.trace_filename, r' v_arru_arrp\[') -test.file_grep(test.trace_filename, r' v_arru_strp\[') - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn.cpp b/test_regress/t/t_trace_dumpvars_dyn.cpp index 20b894452..0a96f0cb3 100644 --- a/test_regress/t/t_trace_dumpvars_dyn.cpp +++ b/test_regress/t/t_trace_dumpvars_dyn.cpp @@ -7,19 +7,7 @@ // SPDX-License-Identifier: CC0-1.0 #include -#if VM_TRACE_FST -#include -#define TRACE_FILE_NAME "simx.fst" -#define TRACE_CLASS VerilatedFstC -#elif VM_TRACE_VCD -#include -#define TRACE_FILE_NAME "simx.vcd" -#define TRACE_CLASS VerilatedVcdC -#elif VM_TRACE_SAIF -#include -#define TRACE_FILE_NAME "simx.saif" -#define TRACE_CLASS VerilatedSaifC -#endif +#include VL_STRINGIFY(TRACE_HEADER_C) #include @@ -37,13 +25,11 @@ int main(int argc, char** argv) { std::unique_ptr top{new VM_PREFIX{"top"}}; - std::unique_ptr tfp{new TRACE_CLASS}; + std::unique_ptr tfp{new VERILATED_TRACE_C}; -#if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_FST_0) \ - || defined(T_TRACE_DUMPVARS_DYN_SAIF_0) +#if defined(TEST_VARIANT_0) tfp->dumpvars(0, ""); -#elif defined(T_TRACE_DUMPVARS_DYN_VCD_1) || defined(T_TRACE_DUMPVARS_DYN_FST_1) \ - || defined(T_TRACE_DUMPVARS_DYN_SAIF_1) +#elif defined(TEST_VARIANT_1) tfp->dumpvars(99, "t"); // This should not match "top." tfp->dumpvars(1, "top.t.cyc"); // A signal tfp->dumpvars(1, "top.t.sub1a"); // Scope @@ -53,7 +39,7 @@ int main(int argc, char** argv) { #endif top->trace(tfp.get(), 99); - tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/" TRACE_FILE_NAME); + tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx." VL_STRINGIFY(TRACE_FMT)); top->clk = 0; while (main_time <= 20) { diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_0.out b/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_dumpvars_dyn_fst_0.out rename to test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.out diff --git a/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.py b/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.py new file mode 100755 index 000000000..189a9b46d --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_dyn_common + +test.scenarios('vlt_all') + +trace_dumpvars_dyn_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_0.out b/test_regress/t/t_trace_dumpvars_dyn_0_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_dumpvars_dyn_saif_0.out rename to test_regress/t/t_trace_dumpvars_dyn_0_cc_saif.out diff --git a/test_regress/t/t_trace_dumpvars_dyn_0_cc_saif.py b/test_regress/t/t_trace_dumpvars_dyn_0_cc_saif.py new file mode 100755 index 000000000..189a9b46d --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_0_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_dyn_common + +test.scenarios('vlt_all') + +trace_dumpvars_dyn_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.out b/test_regress/t/t_trace_dumpvars_dyn_0_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_dumpvars_dyn_vcd_0.out rename to test_regress/t/t_trace_dumpvars_dyn_0_cc_vcd.out diff --git a/test_regress/t/t_trace_dumpvars_dyn_0_cc_vcd.py b/test_regress/t/t_trace_dumpvars_dyn_0_cc_vcd.py new file mode 100755 index 000000000..189a9b46d --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_0_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_dyn_common + +test.scenarios('vlt_all') + +trace_dumpvars_dyn_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_1.out b/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_dumpvars_dyn_fst_1.out rename to test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.out diff --git a/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.py b/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.py new file mode 100755 index 000000000..189a9b46d --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_dyn_common + +test.scenarios('vlt_all') + +trace_dumpvars_dyn_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_1.out b/test_regress/t/t_trace_dumpvars_dyn_1_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_dumpvars_dyn_saif_1.out rename to test_regress/t/t_trace_dumpvars_dyn_1_cc_saif.out diff --git a/test_regress/t/t_trace_dumpvars_dyn_1_cc_saif.py b/test_regress/t/t_trace_dumpvars_dyn_1_cc_saif.py new file mode 100755 index 000000000..189a9b46d --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_1_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_dyn_common + +test.scenarios('vlt_all') + +trace_dumpvars_dyn_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.out b/test_regress/t/t_trace_dumpvars_dyn_1_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_dumpvars_dyn_vcd_1.out rename to test_regress/t/t_trace_dumpvars_dyn_1_cc_vcd.out diff --git a/test_regress/t/t_trace_dumpvars_dyn_1_cc_vcd.py b/test_regress/t/t_trace_dumpvars_dyn_1_cc_vcd.py new file mode 100755 index 000000000..6d694b64d --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_dyn_1_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_dyn_common + +test.scenarios('vlt_all') + +trace_dumpvars_dyn_common.run(test, verilator_flags2=["-CFLAGS", "-DVL_DEBUG"]) diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_0.py b/test_regress/t/t_trace_dumpvars_dyn_fst_0.py deleted file mode 100755 index 50769b6de..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_fst_0.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" -test.top_filename = "t/t_trace_dumpvars_dyn.v" - -test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_1.py b/test_regress/t/t_trace_dumpvars_dyn_fst_1.py deleted file mode 100755 index 50769b6de..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_fst_1.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" -test.top_filename = "t/t_trace_dumpvars_dyn.v" - -test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_0.py b/test_regress/t/t_trace_dumpvars_dyn_saif_0.py deleted file mode 100755 index b12d179c4..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_saif_0.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" -test.top_filename = "t/t_trace_dumpvars_dyn.v" - -test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_1.py b/test_regress/t/t_trace_dumpvars_dyn_saif_1.py deleted file mode 100755 index b12d179c4..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_saif_1.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" -test.top_filename = "t/t_trace_dumpvars_dyn.v" - -test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py deleted file mode 100755 index 2d601cf13..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" -test.top_filename = "t/t_trace_dumpvars_dyn.v" - -test.compile(make_main=False, verilator_flags2=["--trace-vcd --exe", test.pli_filename]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py deleted file mode 100755 index 4c5419770..000000000 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') -test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" -test.top_filename = "t/t_trace_dumpvars_dyn.v" - -test.compile(make_main=False, - verilator_flags2=["--trace-vcd --exe", test.pli_filename, "-CFLAGS -DVL_DEBUG"]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_enum_fst.py b/test_regress/t/t_trace_enum_fst.py index 676f117bc..aff027207 100755 --- a/test_regress/t/t_trace_enum_fst.py +++ b/test_regress/t/t_trace_enum_fst.py @@ -4,26 +4,12 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_enum_common -test.scenarios('simulator') -test.top_filename = "t/t_trace_enum.v" +test.scenarios('vlt_all') -test.compile(verilator_flags2=['--cc --trace-fst --output-split-ctrace 1']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -# Five $attrbegin expected: -# - state_t declaration -# - t.v_enumed -# - t.sink.state -# - other_state_t declaration -# - t.v_other_enumed -test.file_grep_count(test.golden_filename, r'attrbegin', 5) - -test.passes() +trace_enum_common.run(test) diff --git a/test_regress/t/t_trace_enum_saif.py b/test_regress/t/t_trace_enum_saif.py index 248b39c2a..aff027207 100755 --- a/test_regress/t/t_trace_enum_saif.py +++ b/test_regress/t/t_trace_enum_saif.py @@ -4,18 +4,12 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_enum_common -test.scenarios('simulator') -test.top_filename = "t/t_trace_enum.v" +test.scenarios('vlt_all') -test.compile(verilator_flags2=['--cc --trace-saif --output-split-ctrace 1']) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_enum_common.run(test) diff --git a/test_regress/t/t_trace_enum_vcd.out b/test_regress/t/t_trace_enum_vcd.out new file mode 100644 index 000000000..756f1e35f --- /dev/null +++ b/test_regress/t/t_trace_enum_vcd.out @@ -0,0 +1,25 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 " clk $end + $scope module $unit $end + $upscope $end + $scope module t $end + $var wire 1 " clk $end + $var wire 2 # v_enumed [1:0] $end + $var wire 2 $ v_other_enumed [1:0] $end + $scope module sink $end + $var wire 2 % state [1:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +0" +b00 # +b00 $ +b00 % +#10 +1" diff --git a/test_regress/t/t_trace_enum_vcd.py b/test_regress/t/t_trace_enum_vcd.py new file mode 100755 index 000000000..aff027207 --- /dev/null +++ b/test_regress/t/t_trace_enum_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_enum_common + +test.scenarios('vlt_all') + +trace_enum_common.run(test) diff --git a/test_regress/t/t_trace_event.py b/test_regress/t/t_trace_event.py deleted file mode 100755 index 34813642c..000000000 --- a/test_regress/t/t_trace_event.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=[ - '--trace-vcd --binary', - '--dumpi-V3Trace 9' # Dev coverage of the V3DumpFinder debug code -]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_event_fst.py b/test_regress/t/t_trace_event_fst.py index 55ff9751c..7598a23bd 100755 --- a/test_regress/t/t_trace_event_fst.py +++ b/test_regress/t/t_trace_event_fst.py @@ -4,18 +4,12 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_event_common -test.scenarios('vlt') -test.top_filename = "t/t_trace_event.v" +test.scenarios('vlt_all') -test.compile(verilator_flags2=['--trace-fst --binary']) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_event_common.run(test) diff --git a/test_regress/t/t_trace_event_saif.out b/test_regress/t/t_trace_event_saif.out new file mode 100644 index 000000000..63d6994d1 --- /dev/null +++ b/test_regress/t/t_trace_event_saif.out @@ -0,0 +1,48 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 210) + (INSTANCE t + (NET + (ev_test (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) + (i\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) + (i\[2\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) + (i\[3\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) + (i\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (i\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (toggle (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) + (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) + ) + ) +) diff --git a/test_regress/t/t_trace_event_saif.py b/test_regress/t/t_trace_event_saif.py new file mode 100755 index 000000000..7598a23bd --- /dev/null +++ b/test_regress/t/t_trace_event_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_event_common + +test.scenarios('vlt_all') + +trace_event_common.run(test) diff --git a/test_regress/t/t_trace_event.out b/test_regress/t/t_trace_event_vcd.out similarity index 100% rename from test_regress/t/t_trace_event.out rename to test_regress/t/t_trace_event_vcd.out diff --git a/test_regress/t/t_trace_event_vcd.py b/test_regress/t/t_trace_event_vcd.py new file mode 100755 index 000000000..7598a23bd --- /dev/null +++ b/test_regress/t/t_trace_event_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_event_common + +test.scenarios('vlt_all') + +trace_event_common.run(test) diff --git a/test_regress/t/t_trace_fst.py b/test_regress/t/t_trace_fst.py deleted file mode 100755 index 391b761ee..000000000 --- a/test_regress/t/t_trace_fst.py +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.compile(v_flags2=["--trace-fst"]) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_fst_cmake.out b/test_regress/t/t_trace_fst_cmake.out deleted file mode 100644 index 3e52b4c60..000000000 --- a/test_regress/t/t_trace_fst_cmake.out +++ /dev/null @@ -1,1018 +0,0 @@ -$date - Tue Feb 17 01:32:42 2026 - -$end -$version - fstWriter -$end -$timescale - 1ps -$end -$scope module top $end -$var wire 1 ! clk $end -$var wire 5 " state [4:0] $end -$scope module t $end -$var wire 1 ! clk $end -$var int 32 # cyc [31:0] $end -$var logic 1 $ rstn $end -$var wire 5 " state [4:0] $end -$var real_parameter 64 % fst_gparam_real $end -$var real_parameter 64 & fst_lparam_real $end -$var real 64 % fst_real $end -$var integer 32 ' fst_integer [31:0] $end -$var bit 1 ( fst_bit $end -$var logic 1 ) fst_logic $end -$var int 32 * fst_int [31:0] $end -$var shortint 16 + fst_shortint [15:0] $end -$var longint 64 , fst_longint [63:0] $end -$var byte 8 - fst_byte [7:0] $end -$var parameter 32 . fst_parameter [31:0] $end -$var parameter 32 / fst_lparam [31:0] $end -$var supply0 1 0 fst_supply0 $end -$var supply1 1 1 fst_supply1 $end -$var tri0 1 0 fst_tri0 $end -$var tri1 1 1 fst_tri1 $end -$var tri 1 2 fst_tri $end -$var wire 1 3 fst_wire $end -$scope module test $end -$var wire 1 ! clk $end -$var wire 1 $ rstn $end -$var wire 5 " state [4:0] $end -$var logic 5 4 state_w [4:0] $end -$var logic 5 5 state_array[0] [4:0] $end -$var logic 5 6 state_array[1] [4:0] $end -$var logic 5 7 state_array[2] [4:0] $end -$upscope $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -b00000 7 -b00000 6 -b00000 5 -b00000 4 -03 -02 -11 -00 -b00000000000000000000000111001000 / -b00000000000000000000000001111011 . -b00000000 - -b0000000000000000000000000000000000000000000000000000000000000000 , -b0000000000000000 + -b00000000000000000000000000000000 * -0) -0( -b00000000000000000000000000000000 ' -r4.56 & -r1.23 % -0$ -b00000000000000000000000000000000 # -b00000 " -0! -$end -#10 -1! -b00001 " -b00000000000000000000000000000001 # -b10100 4 -b00001 5 -b00001 6 -b00001 7 -#15 -0! -#20 -1! -b00000000000000000000000000000010 # -#25 -0! -#30 -1! -b00000000000000000000000000000011 # -#35 -0! -#40 -1! -b00000000000000000000000000000100 # -#45 -0! -#50 -1! -b00000000000000000000000000000101 # -#55 -0! -#60 -1! -b00000000000000000000000000000110 # -#65 -0! -#70 -1! -b00000000000000000000000000000111 # -#75 -0! -#80 -1! -b00000000000000000000000000001000 # -#85 -0! -#90 -1! -b00000000000000000000000000001001 # -#95 -0! -#100 -1! -b00000000000000000000000000001010 # -#105 -0! -#110 -1! -b00000000000000000000000000001011 # -1$ -#115 -0! -#120 -1! -b00000000000000000000000000001100 # -b10100 7 -b01010 4 -#125 -0! -#130 -1! -b00101 4 -b01010 7 -b00000000000000000000000000001101 # -b10100 6 -#135 -0! -#140 -1! -b01010 6 -b00000000000000000000000000001110 # -b00101 7 -b10110 4 -b10100 5 -b10100 " -#145 -0! -#150 -1! -b01010 " -b01010 5 -b01011 4 -b10110 7 -b00000000000000000000000000001111 # -b00101 6 -#155 -0! -#160 -1! -b10110 6 -b00000000000000000000000000010000 # -b01011 7 -b10001 4 -b00101 5 -b00101 " -#165 -0! -#170 -1! -b10110 " -b10110 5 -b11100 4 -b10001 7 -b00000000000000000000000000010001 # -b01011 6 -#175 -0! -#180 -1! -b10001 6 -b00000000000000000000000000010010 # -b11100 7 -b01110 4 -b01011 5 -b01011 " -#185 -0! -#190 -1! -b10001 " -b10001 5 -b00111 4 -b01110 7 -b00000000000000000000000000010011 # -b11100 6 -#195 -0! -#200 -1! -b01110 6 -b00000000000000000000000000010100 # -b00111 7 -b10111 4 -b11100 5 -b11100 " -#205 -0! -#210 -1! -b01110 " -b01110 5 -b11111 4 -b10111 7 -b00000000000000000000000000010101 # -b00111 6 -#215 -0! -#220 -1! -b10111 6 -b00000000000000000000000000010110 # -b11111 7 -b11011 4 -b00111 5 -b00111 " -#225 -0! -#230 -1! -b10111 " -b10111 5 -b11001 4 -b11011 7 -b00000000000000000000000000010111 # -b11111 6 -#235 -0! -#240 -1! -b11011 6 -b00000000000000000000000000011000 # -b11001 7 -b11000 4 -b11111 5 -b11111 " -#245 -0! -#250 -1! -b11011 " -b11011 5 -b01100 4 -b11000 7 -b00000000000000000000000000011001 # -b11001 6 -#255 -0! -#260 -1! -b11000 6 -b00000000000000000000000000011010 # -b01100 7 -b00110 4 -b11001 5 -b11001 " -#265 -0! -#270 -1! -b11000 " -b11000 5 -b00011 4 -b00110 7 -b00000000000000000000000000011011 # -b01100 6 -#275 -0! -#280 -1! -b00110 6 -b00000000000000000000000000011100 # -b00011 7 -b10101 4 -b01100 5 -b01100 " -#285 -0! -#290 -1! -b00110 " -b00110 5 -b11110 4 -b10101 7 -b00000000000000000000000000011101 # -b00011 6 -#295 -0! -#300 -1! -b10101 6 -b00000000000000000000000000011110 # -b11110 7 -b01111 4 -b00011 5 -b00011 " -#305 -0! -#310 -1! -b10101 " -b10101 5 -b10011 4 -b01111 7 -b00000000000000000000000000011111 # -b11110 6 -#315 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-b10010 4 -b01101 7 -b00000000000000000000000001100001 # -b11010 6 -#975 -0! -#980 -1! -b01101 6 -b00000000000000000000000001100010 # -b10010 7 -b01001 4 -b11010 5 -b11010 " -#985 -0! -#990 -1! -b01101 " -b01101 5 -b10000 4 -b01001 7 -b00000000000000000000000001100011 # -b10010 6 -#995 -0! -#1000 -1! -b01001 6 -b00000000000000000000000001100100 # -b10000 7 -b01000 4 -b10010 5 -b10010 " diff --git a/test_regress/t/t_trace_fst_cmake.py b/test_regress/t/t_trace_fst_cmake.py deleted file mode 100755 index abec2a742..000000000 --- a/test_regress/t/t_trace_fst_cmake.py +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.compile(v_flags2=["--trace-fst"], verilator_make_gmake=False, verilator_make_cmake=True) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_fst_cmake.v b/test_regress/t/t_trace_fst_cmake.v deleted file mode 100644 index cc095ef19..000000000 --- a/test_regress/t/t_trace_fst_cmake.v +++ /dev/null @@ -1,98 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2018 Yu-Sheng Lin -// SPDX-License-Identifier: CC0-1.0 - -module t ( /*AUTOARG*/ - // Outputs - state, - // Inputs - clk -); - - input clk; - - int cyc; - reg rstn; - output [4:0] state; - - parameter real fst_gparam_real = 1.23; - localparam real fst_lparam_real = 4.56; - real fst_real = 1.23; - integer fst_integer; - bit fst_bit; - logic fst_logic; - int fst_int; - shortint fst_shortint; - longint fst_longint; - byte fst_byte; - - parameter fst_parameter = 123; - localparam fst_lparam = 456; - supply0 fst_supply0; - supply1 fst_supply1; - tri0 fst_tri0; - tri1 fst_tri1; - tri fst_tri; - wire fst_wire; - - Test test ( /*AUTOINST*/ - // Outputs - .state(state[4:0]), - // Inputs - .clk(clk), - .rstn(rstn) - ); - - // Test loop - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - // Setup - rstn <= ~'1; - end - else if (cyc < 10) begin - rstn <= ~'1; - end - else if (cyc < 90) begin - rstn <= ~'0; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - - -module Test ( - input clk, - input rstn, - output logic [4:0] state -); - - logic [4:0] state_w; - logic [4:0] state_array[3]; - assign state = state_array[0]; - - always_comb begin - state_w[4] = state_array[2][0]; - state_w[3] = state_array[2][4]; - state_w[2] = state_array[2][3] ^ state_array[2][0]; - state_w[1] = state_array[2][2]; - state_w[0] = state_array[2][1]; - end - - always_ff @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 3; i++) state_array[i] <= 'b1; - end - else begin - for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; - state_array[2] <= state_w; - end - end - -endmodule diff --git a/test_regress/t/t_trace_fst_sc.out b/test_regress/t/t_trace_fst_sc.out deleted file mode 100644 index b911ff93a..000000000 --- a/test_regress/t/t_trace_fst_sc.out +++ /dev/null @@ -1,1017 +0,0 @@ -$date - Tue Feb 17 01:32:42 2026 - -$end -$version - fstWriter -$end -$timescale - 1ps -$end -$scope module top $end -$scope module t $end -$var wire 1 ! clk $end -$var int 32 " cyc [31:0] $end -$var logic 1 # rstn $end -$var real_parameter 64 $ fst_gparam_real $end -$var real_parameter 64 % fst_lparam_real $end -$var real 64 $ fst_real $end -$var integer 32 & fst_integer [31:0] $end -$var bit 1 ' fst_bit $end -$var logic 1 ( fst_logic $end -$var int 32 ) fst_int [31:0] $end -$var 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-1! -b01101 6 -b00000000000000000000000001100010 " -b10010 7 -b01001 4 -b11010 5 -b11010 3 -#985 -0! -#990 -1! -b01101 3 -b01101 5 -b10000 4 -b01001 7 -b00000000000000000000000001100011 " -b10010 6 -#995 -0! -#1000 -1! -b01001 6 -b00000000000000000000000001100100 " -b10000 7 -b01000 4 -b10010 5 -b10010 3 -#1004 diff --git a/test_regress/t/t_trace_fst_sc.py b/test_regress/t/t_trace_fst_sc.py deleted file mode 100755 index f142e7f0f..000000000 --- a/test_regress/t/t_trace_fst_sc.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=["--trace-fst --sc"]) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_fst_sc.v b/test_regress/t/t_trace_fst_sc.v deleted file mode 100644 index 1eb7e76a3..000000000 --- a/test_regress/t/t_trace_fst_sc.v +++ /dev/null @@ -1,94 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2018 Yu-Sheng Lin -// SPDX-License-Identifier: CC0-1.0 - -module t ( - input clk -); - - int cyc; - reg rstn; - - parameter real fst_gparam_real = 1.23; - localparam real fst_lparam_real = 4.56; - real fst_real = 1.23; - integer fst_integer; - bit fst_bit; - logic fst_logic; - int fst_int; - shortint fst_shortint; - longint fst_longint; - byte fst_byte; - - parameter fst_parameter = 123; - localparam fst_lparam = 456; - supply0 fst_supply0; - supply1 fst_supply1; - tri0 fst_tri0; - tri1 fst_tri1; - tri fst_tri; - wire fst_wire; - - logic [4:0] state; - - Test test ( /*AUTOINST*/ - // Outputs - .state(state[4:0]), - // Inputs - .clk(clk), - .rstn(rstn) - ); - - // Test loop - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - // Setup - rstn <= ~'1; - end - else if (cyc < 10) begin - rstn <= ~'1; - end - else if (cyc < 90) begin - rstn <= ~'0; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - - -module Test ( - input clk, - input rstn, - output logic [4:0] state -); - - logic [4:0] state_w; - logic [4:0] state_array[3]; - assign state = state_array[0]; - - always_comb begin - state_w[4] = state_array[2][0]; - state_w[3] = state_array[2][4]; - state_w[2] = state_array[2][3] ^ state_array[2][0]; - state_w[1] = state_array[2][2]; - state_w[0] = state_array[2][1]; - end - - always_ff @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 3; i++) state_array[i] <= 'b1; - end - else begin - for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; - state_array[2] <= state_w; - end - end - -endmodule diff --git a/test_regress/t/t_trace_fst_sc_cmake.out b/test_regress/t/t_trace_fst_sc_cmake.out deleted file mode 100644 index b911ff93a..000000000 --- a/test_regress/t/t_trace_fst_sc_cmake.out +++ /dev/null @@ -1,1017 +0,0 @@ -$date - Tue Feb 17 01:32:42 2026 - -$end -$version - fstWriter -$end -$timescale - 1ps -$end -$scope module top $end -$scope module t $end -$var wire 1 ! clk $end -$var int 32 " cyc [31:0] $end -$var logic 1 # rstn $end -$var real_parameter 64 $ fst_gparam_real $end -$var real_parameter 64 % fst_lparam_real $end -$var real 64 $ fst_real $end -$var integer 32 & fst_integer [31:0] $end -$var bit 1 ' fst_bit $end -$var logic 1 ( fst_logic $end -$var int 32 ) fst_int [31:0] $end -$var shortint 16 * fst_shortint [15:0] $end -$var longint 64 + fst_longint [63:0] $end -$var byte 8 , fst_byte [7:0] $end -$var parameter 32 - fst_parameter [31:0] $end -$var parameter 32 . fst_lparam [31:0] $end -$var supply0 1 / fst_supply0 $end -$var supply1 1 0 fst_supply1 $end -$var tri0 1 / fst_tri0 $end -$var tri1 1 0 fst_tri1 $end -$var tri 1 1 fst_tri $end -$var wire 1 2 fst_wire $end -$var logic 5 3 state [4:0] $end -$scope module test $end -$var wire 1 ! clk $end -$var wire 1 # rstn $end -$var wire 5 3 state [4:0] $end -$var logic 5 4 state_w [4:0] $end -$var logic 5 5 state_array[0] [4:0] $end -$var logic 5 6 state_array[1] [4:0] $end -$var logic 5 7 state_array[2] [4:0] $end -$upscope $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -b00000 7 -b00000 6 -b00000 5 -b00000 4 -b00000 3 -02 -01 -10 -0/ -b00000000000000000000000111001000 . -b00000000000000000000000001111011 - -b00000000 , -b0000000000000000000000000000000000000000000000000000000000000000 + -b0000000000000000 * -b00000000000000000000000000000000 ) -0( -0' -b00000000000000000000000000000000 & -r4.56 % -r1.23 $ -0# -b00000000000000000000000000000000 " -0! -$end -#10 -1! -b00000000000000000000000000000001 " -b00001 3 -b10100 4 -b00001 5 -b00001 6 -b00001 7 -#15 -0! -#20 -1! -b00000000000000000000000000000010 " -#25 -0! -#30 -1! -b00000000000000000000000000000011 " -#35 -0! -#40 -1! -b00000000000000000000000000000100 " -#45 -0! -#50 -1! -b00000000000000000000000000000101 " -#55 -0! -#60 -1! -b00000000000000000000000000000110 " -#65 -0! -#70 -1! -b00000000000000000000000000000111 " -#75 -0! -#80 -1! -b00000000000000000000000000001000 " -#85 -0! -#90 -1! -b00000000000000000000000000001001 " -#95 -0! -#100 -1! -b00000000000000000000000000001010 " -#105 -0! -#110 -1! -b00000000000000000000000000001011 " -1# -#115 -0! -#120 -1! -b00000000000000000000000000001100 " -b10100 7 -b01010 4 -#125 -0! -#130 -1! -b00101 4 -b01010 7 -b00000000000000000000000000001101 " -b10100 6 -#135 -0! -#140 -1! -b01010 6 -b00000000000000000000000000001110 " -b00101 7 -b10110 4 -b10100 5 -b10100 3 -#145 -0! -#150 -1! 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-b00000000000000000000000001011001 " -b01100 6 -#895 -0! -#900 -1! -b00110 6 -b00000000000000000000000001011010 " -b00011 7 -b10101 4 -b01100 5 -b01100 3 -#905 -0! -#910 -1! -b00110 3 -b00110 5 -b11110 4 -b10101 7 -b00000000000000000000000001011011 " -b00011 6 -#915 -0! -#920 -1! -b10101 6 -b00000000000000000000000001011100 " -b11110 7 -b01111 4 -b00011 5 -b00011 3 -#925 -0! -#930 -1! -b10101 3 -b10101 5 -b10011 4 -b01111 7 -b00000000000000000000000001011101 " -b11110 6 -#935 -0! -#940 -1! -b01111 6 -b00000000000000000000000001011110 " -b10011 7 -b11101 4 -b11110 5 -b11110 3 -#945 -0! -#950 -1! -b01111 3 -b01111 5 -b11010 4 -b11101 7 -b00000000000000000000000001011111 " -b10011 6 -#955 -0! -#960 -1! -b11101 6 -b00000000000000000000000001100000 " -b11010 7 -b01101 4 -b10011 5 -b10011 3 -#965 -0! -#970 -1! -b11101 3 -b11101 5 -b10010 4 -b01101 7 -b00000000000000000000000001100001 " -b11010 6 -#975 -0! -#980 -1! -b01101 6 -b00000000000000000000000001100010 " -b10010 7 -b01001 4 -b11010 5 -b11010 3 -#985 -0! -#990 -1! -b01101 3 -b01101 5 -b10000 4 -b01001 7 -b00000000000000000000000001100011 " -b10010 6 -#995 -0! -#1000 -1! -b01001 6 -b00000000000000000000000001100100 " -b10000 7 -b01000 4 -b10010 5 -b10010 3 -#1004 diff --git a/test_regress/t/t_trace_fst_sc_cmake.py b/test_regress/t/t_trace_fst_sc_cmake.py deleted file mode 100755 index 5473e886d..000000000 --- a/test_regress/t/t_trace_fst_sc_cmake.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=["--trace-fst --sc"], - verilator_make_gmake=False, - verilator_make_cmake=True) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_fst_sc_cmake.v b/test_regress/t/t_trace_fst_sc_cmake.v deleted file mode 100644 index 1eb7e76a3..000000000 --- a/test_regress/t/t_trace_fst_sc_cmake.v +++ /dev/null @@ -1,94 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2018 Yu-Sheng Lin -// SPDX-License-Identifier: CC0-1.0 - -module t ( - input clk -); - - int cyc; - reg rstn; - - parameter real fst_gparam_real = 1.23; - localparam real fst_lparam_real = 4.56; - real fst_real = 1.23; - integer fst_integer; - bit fst_bit; - logic fst_logic; - int fst_int; - shortint fst_shortint; - longint fst_longint; - byte fst_byte; - - parameter fst_parameter = 123; - localparam fst_lparam = 456; - supply0 fst_supply0; - supply1 fst_supply1; - tri0 fst_tri0; - tri1 fst_tri1; - tri fst_tri; - wire fst_wire; - - logic [4:0] state; - - Test test ( /*AUTOINST*/ - // Outputs - .state(state[4:0]), - // Inputs - .clk(clk), - .rstn(rstn) - ); - - // Test loop - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - // Setup - rstn <= ~'1; - end - else if (cyc < 10) begin - rstn <= ~'1; - end - else if (cyc < 90) begin - rstn <= ~'0; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - - -module Test ( - input clk, - input rstn, - output logic [4:0] state -); - - logic [4:0] state_w; - logic [4:0] state_array[3]; - assign state = state_array[0]; - - always_comb begin - state_w[4] = state_array[2][0]; - state_w[3] = state_array[2][4]; - state_w[2] = state_array[2][3] ^ state_array[2][0]; - state_w[1] = state_array[2][2]; - state_w[0] = state_array[2][1]; - end - - always_ff @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 3; i++) state_array[i] <= 'b1; - end - else begin - for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; - state_array[2] <= state_w; - end - end - -endmodule diff --git a/test_regress/t/t_hier_trace.v b/test_regress/t/t_trace_hier.v similarity index 100% rename from test_regress/t/t_hier_trace.v rename to test_regress/t/t_trace_hier.v diff --git a/test_regress/t/t_hier_block_trace_fst.out b/test_regress/t/t_trace_hier_block_default_cc_fst.out similarity index 100% rename from test_regress/t/t_hier_block_trace_fst.out rename to test_regress/t/t_trace_hier_block_default_cc_fst.out diff --git a/test_regress/t/t_hier_block_trace_fst_noinl.py b/test_regress/t/t_trace_hier_block_default_cc_fst.py similarity index 86% rename from test_regress/t/t_hier_block_trace_fst_noinl.py rename to test_regress/t/t_trace_hier_block_default_cc_fst.py index e8283c39d..14165eea8 100755 --- a/test_regress/t/t_hier_block_trace_fst_noinl.py +++ b/test_regress/t/t_trace_hier_block_default_cc_fst.py @@ -8,10 +8,9 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap - -import runpy +import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') -runpy.run_path("t/t_hier_block_trace_fst.py", globals()) +trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_default_cc_fst_noinl.py b/test_regress/t/t_trace_hier_block_default_cc_fst_noinl.py new file mode 100755 index 000000000..b4ae62596 --- /dev/null +++ b/test_regress/t/t_trace_hier_block_default_cc_fst_noinl.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_block_common + +test.priority(30) +test.scenarios('vlt_all') + +trace_hier_block_common.run(test, verilator_flags2=["+define+NO_INLINE"]) diff --git a/test_regress/t/t_hier_block_trace_saif.out b/test_regress/t/t_trace_hier_block_default_cc_saif.out similarity index 100% rename from test_regress/t/t_hier_block_trace_saif.out rename to test_regress/t/t_trace_hier_block_default_cc_saif.out diff --git a/test_regress/t/t_hier_block_trace_fst_notop.py b/test_regress/t/t_trace_hier_block_default_cc_saif.py similarity index 86% rename from test_regress/t/t_hier_block_trace_fst_notop.py rename to test_regress/t/t_trace_hier_block_default_cc_saif.py index e8283c39d..14165eea8 100755 --- a/test_regress/t/t_hier_block_trace_fst_notop.py +++ b/test_regress/t/t_trace_hier_block_default_cc_saif.py @@ -8,10 +8,9 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap - -import runpy +import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') -runpy.run_path("t/t_hier_block_trace_fst.py", globals()) +trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_default_cc_saif_noinl.py b/test_regress/t/t_trace_hier_block_default_cc_saif_noinl.py new file mode 100755 index 000000000..b4ae62596 --- /dev/null +++ b/test_regress/t/t_trace_hier_block_default_cc_saif_noinl.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_block_common + +test.priority(30) +test.scenarios('vlt_all') + +trace_hier_block_common.run(test, verilator_flags2=["+define+NO_INLINE"]) diff --git a/test_regress/t/t_hier_block_trace_vcd.out b/test_regress/t/t_trace_hier_block_default_cc_vcd.out similarity index 100% rename from test_regress/t/t_hier_block_trace_vcd.out rename to test_regress/t/t_trace_hier_block_default_cc_vcd.out diff --git a/test_regress/t/t_hier_block_trace_vcd_noinl.py b/test_regress/t/t_trace_hier_block_default_cc_vcd.py similarity index 86% rename from test_regress/t/t_hier_block_trace_vcd_noinl.py rename to test_regress/t/t_trace_hier_block_default_cc_vcd.py index 8b05cc089..14165eea8 100755 --- a/test_regress/t/t_hier_block_trace_vcd_noinl.py +++ b/test_regress/t/t_trace_hier_block_default_cc_vcd.py @@ -8,10 +8,9 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap - -import runpy +import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') -runpy.run_path("t/t_hier_block_trace_vcd.py", globals()) +trace_hier_block_common.run(test) diff --git a/test_regress/t/t_trace_hier_block_default_cc_vcd_noinl.py b/test_regress/t/t_trace_hier_block_default_cc_vcd_noinl.py new file mode 100755 index 000000000..b4ae62596 --- /dev/null +++ b/test_regress/t/t_trace_hier_block_default_cc_vcd_noinl.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_block_common + +test.priority(30) +test.scenarios('vlt_all') + +trace_hier_block_common.run(test, verilator_flags2=["+define+NO_INLINE"]) diff --git a/test_regress/t/t_hier_block_sc_trace_fst.out b/test_regress/t/t_trace_hier_block_default_sc_fst.out similarity index 99% rename from test_regress/t/t_hier_block_sc_trace_fst.out rename to test_regress/t/t_trace_hier_block_default_sc_fst.out index 1ebd77252..863bebb65 100644 --- a/test_regress/t/t_hier_block_sc_trace_fst.out +++ b/test_regress/t/t_trace_hier_block_default_sc_fst.out @@ -1,5 +1,5 @@ $date - Tue Feb 17 01:31:48 2026 + Wed Mar 11 11:58:28 2026 $end $version diff --git a/test_regress/t/t_hier_block_trace_vcd_notop.py b/test_regress/t/t_trace_hier_block_default_sc_fst.py similarity index 86% rename from test_regress/t/t_hier_block_trace_vcd_notop.py rename to test_regress/t/t_trace_hier_block_default_sc_fst.py index 8b05cc089..14165eea8 100755 --- a/test_regress/t/t_hier_block_trace_vcd_notop.py +++ b/test_regress/t/t_trace_hier_block_default_sc_fst.py @@ -8,10 +8,9 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap - -import runpy +import trace_hier_block_common test.priority(30) test.scenarios('vlt_all') -runpy.run_path("t/t_hier_block_trace_vcd.py", globals()) +trace_hier_block_common.run(test) diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.out b/test_regress/t/t_trace_hier_block_default_sc_vcd.out similarity index 100% rename from test_regress/t/t_hier_block_sc_trace_vcd.out rename to test_regress/t/t_trace_hier_block_default_sc_vcd.out diff --git a/test_regress/t/t_trace_hier_block_default_sc_vcd.py b/test_regress/t/t_trace_hier_block_default_sc_vcd.py new file mode 100755 index 000000000..14165eea8 --- /dev/null +++ b/test_regress/t/t_trace_hier_block_default_sc_vcd.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_block_common + +test.priority(30) +test.scenarios('vlt_all') + +trace_hier_block_common.run(test) diff --git a/test_regress/t/t_hier_block_trace_fst_notop.out b/test_regress/t/t_trace_hier_block_notop_cc_fst.out similarity index 100% rename from test_regress/t/t_hier_block_trace_fst_notop.out rename to test_regress/t/t_trace_hier_block_notop_cc_fst.out diff --git a/test_regress/t/t_trace_hier_block_notop_cc_fst.py b/test_regress/t/t_trace_hier_block_notop_cc_fst.py new file mode 100755 index 000000000..14165eea8 --- /dev/null +++ b/test_regress/t/t_trace_hier_block_notop_cc_fst.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_block_common + +test.priority(30) +test.scenarios('vlt_all') + +trace_hier_block_common.run(test) diff --git a/test_regress/t/t_hier_block_trace_saif_notop.out b/test_regress/t/t_trace_hier_block_notop_cc_saif.out similarity index 100% rename from test_regress/t/t_hier_block_trace_saif_notop.out rename to test_regress/t/t_trace_hier_block_notop_cc_saif.out diff --git a/test_regress/t/t_trace_hier_block_notop_cc_saif.py b/test_regress/t/t_trace_hier_block_notop_cc_saif.py new file mode 100755 index 000000000..14165eea8 --- /dev/null +++ b/test_regress/t/t_trace_hier_block_notop_cc_saif.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_block_common + +test.priority(30) +test.scenarios('vlt_all') + +trace_hier_block_common.run(test) diff --git a/test_regress/t/t_hier_block_trace_vcd_notop.out b/test_regress/t/t_trace_hier_block_notop_cc_vcd.out similarity index 100% rename from test_regress/t/t_hier_block_trace_vcd_notop.out rename to test_regress/t/t_trace_hier_block_notop_cc_vcd.out diff --git a/test_regress/t/t_trace_hier_block_notop_cc_vcd.py b/test_regress/t/t_trace_hier_block_notop_cc_vcd.py new file mode 100755 index 000000000..14165eea8 --- /dev/null +++ b/test_regress/t/t_trace_hier_block_notop_cc_vcd.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_block_common + +test.priority(30) +test.scenarios('vlt_all') + +trace_hier_block_common.run(test) diff --git a/test_regress/t/t_hier_block_trace_vcd_statful_pkg.out b/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.out similarity index 100% rename from test_regress/t/t_hier_block_trace_vcd_statful_pkg.out rename to test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.out diff --git a/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.py b/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.py new file mode 100755 index 000000000..14165eea8 --- /dev/null +++ b/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_block_common + +test.priority(30) +test.scenarios('vlt_all') + +trace_hier_block_common.run(test) diff --git a/test_regress/t/t_hier_trace.out b/test_regress/t/t_trace_hier_fst.out similarity index 100% rename from test_regress/t/t_hier_trace.out rename to test_regress/t/t_trace_hier_fst.out diff --git a/test_regress/t/t_trace_hier_fst.py b/test_regress/t/t_trace_hier_fst.py new file mode 100755 index 000000000..8000fcfd0 --- /dev/null +++ b/test_regress/t/t_trace_hier_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_common + +test.scenarios('vlt_all') + +trace_hier_common.run(test) diff --git a/test_regress/t/t_trace_hier_fst_noinl.py b/test_regress/t/t_trace_hier_fst_noinl.py new file mode 100755 index 000000000..532949897 --- /dev/null +++ b/test_regress/t/t_trace_hier_fst_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_common + +test.scenarios('vlt_all') + +trace_hier_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_trace_hier_saif.out b/test_regress/t/t_trace_hier_saif.out new file mode 100644 index 000000000..d3e229a80 --- /dev/null +++ b/test_regress/t/t_trace_hier_saif.out @@ -0,0 +1,129 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 0) + (INSTANCE top + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + (INSTANCE t + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + (INSTANCE u0_sub_top + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + (INSTANCE u0 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u1 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u2 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u3 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u4 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u5 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u6 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u7 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + ) + (INSTANCE u1_sub_top + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + (INSTANCE u0 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u1 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u2 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u3 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u4 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u5 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u6 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE u7 + (NET + (clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (reset_l (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + ) + ) + ) +) diff --git a/test_regress/t/t_trace_hier_saif.py b/test_regress/t/t_trace_hier_saif.py new file mode 100755 index 000000000..8000fcfd0 --- /dev/null +++ b/test_regress/t/t_trace_hier_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_common + +test.scenarios('vlt_all') + +trace_hier_common.run(test) diff --git a/test_regress/t/t_trace_hier_saif_noinl.py b/test_regress/t/t_trace_hier_saif_noinl.py new file mode 100755 index 000000000..532949897 --- /dev/null +++ b/test_regress/t/t_trace_hier_saif_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_common + +test.scenarios('vlt_all') + +trace_hier_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_hier_trace_sub/sub.vc b/test_regress/t/t_trace_hier_sub/sub.vc similarity index 84% rename from test_regress/t/t_hier_trace_sub/sub.vc rename to test_regress/t/t_trace_hier_sub/sub.vc index 6702fa493..d9c2c3730 100644 --- a/test_regress/t/t_hier_trace_sub/sub.vc +++ b/test_regress/t/t_trace_hier_sub/sub.vc @@ -4,6 +4,6 @@ # SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -+define+T_HIER_TRACE_SUB_VC_DEFINE ++define+T_TRACE_HIER_SUB_VC_DEFINE -t_hier_trace_sub.v +t_trace_hier_sub.v diff --git a/test_regress/t/t_hier_trace_sub/t_hier_trace.vlt b/test_regress/t/t_trace_hier_sub/t_trace_hier.vlt similarity index 100% rename from test_regress/t/t_hier_trace_sub/t_hier_trace.vlt rename to test_regress/t/t_trace_hier_sub/t_trace_hier.vlt diff --git a/test_regress/t/t_hier_trace_sub/t_hier_trace_sub.v b/test_regress/t/t_trace_hier_sub/t_trace_hier_sub.v similarity index 90% rename from test_regress/t/t_hier_trace_sub/t_hier_trace_sub.v rename to test_regress/t/t_trace_hier_sub/t_trace_hier_sub.v index 9ee9037ea..eca9c8066 100644 --- a/test_regress/t/t_hier_trace_sub/t_hier_trace_sub.v +++ b/test_regress/t/t_trace_hier_sub/t_trace_hier_sub.v @@ -4,8 +4,8 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -`ifndef T_HIER_TRACE_SUB_VC_DEFINE -`error "Missed T_HIER_TRACE_INC_V from sub.vc file" +`ifndef T_TRACE_HIER_SUB_VC_DEFINE +`error "Missed T_TRACE_HIER_INC_V from sub.vc file" `endif module detail_code ( diff --git a/test_regress/t/t_hier_trace_sub/top.vc b/test_regress/t/t_trace_hier_sub/top.vc similarity index 100% rename from test_regress/t/t_hier_trace_sub/top.vc rename to test_regress/t/t_trace_hier_sub/top.vc diff --git a/test_regress/t/t_hier_trace_noinl.out b/test_regress/t/t_trace_hier_vcd.out similarity index 100% rename from test_regress/t/t_hier_trace_noinl.out rename to test_regress/t/t_trace_hier_vcd.out diff --git a/test_regress/t/t_trace_hier_vcd.py b/test_regress/t/t_trace_hier_vcd.py new file mode 100755 index 000000000..8000fcfd0 --- /dev/null +++ b/test_regress/t/t_trace_hier_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_common + +test.scenarios('vlt_all') + +trace_hier_common.run(test) diff --git a/test_regress/t/t_trace_hier_vcd_noinl.py b/test_regress/t/t_trace_hier_vcd_noinl.py new file mode 100755 index 000000000..532949897 --- /dev/null +++ b/test_regress/t/t_trace_hier_vcd_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_hier_common + +test.scenarios('vlt_all') + +trace_hier_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_ref_trace.v b/test_regress/t/t_trace_interface_ref.v similarity index 100% rename from test_regress/t/t_interface_ref_trace.v rename to test_regress/t/t_trace_interface_ref.v diff --git a/test_regress/t/t_interface_ref_trace_fst.out b/test_regress/t/t_trace_interface_ref_cc_fst.out similarity index 100% rename from test_regress/t/t_interface_ref_trace_fst.out rename to test_regress/t/t_trace_interface_ref_cc_fst.out diff --git a/test_regress/t/t_trace_interface_ref_cc_fst.py b/test_regress/t/t_trace_interface_ref_cc_fst.py new file mode 100755 index 000000000..0fac34f3a --- /dev/null +++ b/test_regress/t/t_trace_interface_ref_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_interface_ref_common + +test.scenarios('vlt_all') + +trace_interface_ref_common.run(test) diff --git a/test_regress/t/t_interface_ref_trace_saif.out b/test_regress/t/t_trace_interface_ref_cc_saif.out similarity index 100% rename from test_regress/t/t_interface_ref_trace_saif.out rename to test_regress/t/t_trace_interface_ref_cc_saif.out diff --git a/test_regress/t/t_trace_interface_ref_cc_saif.py b/test_regress/t/t_trace_interface_ref_cc_saif.py new file mode 100755 index 000000000..0fac34f3a --- /dev/null +++ b/test_regress/t/t_trace_interface_ref_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_interface_ref_common + +test.scenarios('vlt_all') + +trace_interface_ref_common.run(test) diff --git a/test_regress/t/t_interface_ref_trace.out b/test_regress/t/t_trace_interface_ref_cc_vcd.out similarity index 100% rename from test_regress/t/t_interface_ref_trace.out rename to test_regress/t/t_trace_interface_ref_cc_vcd.out diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd.py b/test_regress/t/t_trace_interface_ref_cc_vcd.py new file mode 100755 index 000000000..0fac34f3a --- /dev/null +++ b/test_regress/t/t_trace_interface_ref_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_interface_ref_common + +test.scenarios('vlt_all') + +trace_interface_ref_common.run(test) diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd_inla.py b/test_regress/t/t_trace_interface_ref_cc_vcd_inla.py new file mode 100755 index 000000000..e311419f3 --- /dev/null +++ b/test_regress/t/t_trace_interface_ref_cc_vcd_inla.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_interface_ref_common + +test.scenarios('vlt_all') + +trace_interface_ref_common.run(test, verilator_flags2=["+define+NO_INLINE_A"]) diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd_inlab.py b/test_regress/t/t_trace_interface_ref_cc_vcd_inlab.py new file mode 100755 index 000000000..38b269e81 --- /dev/null +++ b/test_regress/t/t_trace_interface_ref_cc_vcd_inlab.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_interface_ref_common + +test.scenarios('vlt_all') + +trace_interface_ref_common.run(test, + verilator_flags2=["+define+NO_INLINE_A", "+define+NO_INLINE_B"]) diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd_inlb.py b/test_regress/t/t_trace_interface_ref_cc_vcd_inlb.py new file mode 100755 index 000000000..389614688 --- /dev/null +++ b/test_regress/t/t_trace_interface_ref_cc_vcd_inlb.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_interface_ref_common + +test.scenarios('vlt_all') + +trace_interface_ref_common.run(test, verilator_flags2=["+define+NO_INLINE_B"]) diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd_noinl.py b/test_regress/t/t_trace_interface_ref_cc_vcd_noinl.py new file mode 100755 index 000000000..1a8543f75 --- /dev/null +++ b/test_regress/t/t_trace_interface_ref_cc_vcd_noinl.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_interface_ref_common + +test.scenarios('vlt_all') + +trace_interface_ref_common.run(test, verilator_flags2=["-fno-inline"]) diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.out b/test_regress/t/t_trace_interface_ref_sc_fst.out similarity index 100% rename from test_regress/t/t_interface_ref_trace_fst_sc.out rename to test_regress/t/t_trace_interface_ref_sc_fst.out diff --git a/test_regress/t/t_trace_interface_ref_sc_fst.py b/test_regress/t/t_trace_interface_ref_sc_fst.py new file mode 100755 index 000000000..0fac34f3a --- /dev/null +++ b/test_regress/t/t_trace_interface_ref_sc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_interface_ref_common + +test.scenarios('vlt_all') + +trace_interface_ref_common.run(test) diff --git a/test_regress/t/t_trace_no_top_name.py b/test_regress/t/t_trace_no_top_name.py deleted file mode 100755 index 829683b15..000000000 --- a/test_regress/t/t_trace_no_top_name.py +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary --main-top-name '-' --trace-vcd -Wno-MULTITOP"]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_no_top_name2.cpp b/test_regress/t/t_trace_no_top_name2.cpp index cf2756a91..75b77352b 100644 --- a/test_regress/t/t_trace_no_top_name2.cpp +++ b/test_regress/t/t_trace_no_top_name2.cpp @@ -7,19 +7,7 @@ // SPDX-License-Identifier: CC0-1.0 #include -#if VM_TRACE_FST -#include -#define TRACE_FILE_NAME "simx.fst" -#define TRACE_CLASS VerilatedFstC -#elif VM_TRACE_VCD -#include -#define TRACE_FILE_NAME "simx.vcd" -#define TRACE_CLASS VerilatedVcdC -#elif VM_TRACE_SAIF -#include -#define TRACE_FILE_NAME "simx.saif" -#define TRACE_CLASS VerilatedSaifC -#endif +#include VL_STRINGIFY(TRACE_HEADER_C) #include @@ -36,10 +24,10 @@ int main(int argc, char** argv) { // This test is to specifically check "" as the below upper model name std::unique_ptr top{new VM_PREFIX{""}}; - std::unique_ptr tfp{new TRACE_CLASS}; + std::unique_ptr tfp{new VERILATED_TRACE_C}; top->trace(tfp.get(), 99); - tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/" TRACE_FILE_NAME); + tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx." VL_STRINGIFY(TRACE_FMT)); top->clk = 0; while (main_time <= 20) { diff --git a/test_regress/t/t_trace_no_top_name2_fst.py b/test_regress/t/t_trace_no_top_name2_fst.py index d9ca4cfad..13ac10e86 100755 --- a/test_regress/t/t_trace_no_top_name2_fst.py +++ b/test_regress/t/t_trace_no_top_name2_fst.py @@ -4,19 +4,12 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_no_top_name2_common -test.scenarios('vlt') -test.pli_filename = "t/t_trace_no_top_name2.cpp" -test.top_filename = "t/t_trace_no_top_name2.v" +test.scenarios('vlt_all') -test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_no_top_name2_common.run(test) diff --git a/test_regress/t/t_trace_no_top_name2_saif.py b/test_regress/t/t_trace_no_top_name2_saif.py index 46e190d0a..13ac10e86 100755 --- a/test_regress/t/t_trace_no_top_name2_saif.py +++ b/test_regress/t/t_trace_no_top_name2_saif.py @@ -4,19 +4,12 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_no_top_name2_common -test.scenarios('vlt') -test.pli_filename = "t/t_trace_no_top_name2.cpp" -test.top_filename = "t/t_trace_no_top_name2.v" +test.scenarios('vlt_all') -test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_no_top_name2_common.run(test) diff --git a/test_regress/t/t_trace_no_top_name2_vcd.py b/test_regress/t/t_trace_no_top_name2_vcd.py index 9f472bdd9..13ac10e86 100755 --- a/test_regress/t/t_trace_no_top_name2_vcd.py +++ b/test_regress/t/t_trace_no_top_name2_vcd.py @@ -4,19 +4,12 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_no_top_name2_common -test.scenarios('vlt') -test.pli_filename = "t/t_trace_no_top_name2.cpp" -test.top_filename = "t/t_trace_no_top_name2.v" +test.scenarios('vlt_all') -test.compile(make_main=False, verilator_flags2=["--trace-vcd --exe", test.pli_filename]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_no_top_name2_common.run(test) diff --git a/test_regress/t/t_trace_no_top_name_fst.out b/test_regress/t/t_trace_no_top_name_fst.out new file mode 100644 index 000000000..6349508d1 --- /dev/null +++ b/test_regress/t/t_trace_no_top_name_fst.out @@ -0,0 +1,20 @@ +$date + Thu Mar 12 09:19:45 2026 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module another_top $end +$var wire 1 ! b $end +$upscope $end +$scope module t $end +$var wire 1 ! a $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0! diff --git a/test_regress/t/t_trace_no_top_name_fst.py b/test_regress/t/t_trace_no_top_name_fst.py new file mode 100755 index 000000000..966299507 --- /dev/null +++ b/test_regress/t/t_trace_no_top_name_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_no_top_name_common + +test.scenarios('vlt_all') + +trace_no_top_name_common.run(test) diff --git a/test_regress/t/t_trace_no_top_name_saif.out b/test_regress/t/t_trace_no_top_name_saif.out new file mode 100644 index 000000000..bc110b304 --- /dev/null +++ b/test_regress/t/t_trace_no_top_name_saif.out @@ -0,0 +1,19 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 0) + (INSTANCE another_top + (NET + (b (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + (INSTANCE t + (NET + (a (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) +) diff --git a/test_regress/t/t_trace_no_top_name_saif.py b/test_regress/t/t_trace_no_top_name_saif.py new file mode 100755 index 000000000..966299507 --- /dev/null +++ b/test_regress/t/t_trace_no_top_name_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_no_top_name_common + +test.scenarios('vlt_all') + +trace_no_top_name_common.run(test) diff --git a/test_regress/t/t_trace_no_top_name.out b/test_regress/t/t_trace_no_top_name_vcd.out similarity index 100% rename from test_regress/t/t_trace_no_top_name.out rename to test_regress/t/t_trace_no_top_name_vcd.out diff --git a/test_regress/t/t_trace_no_top_name_vcd.py b/test_regress/t/t_trace_no_top_name_vcd.py new file mode 100755 index 000000000..966299507 --- /dev/null +++ b/test_regress/t/t_trace_no_top_name_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_no_top_name_common + +test.scenarios('vlt_all') + +trace_no_top_name_common.run(test) diff --git a/test_regress/t/t_trace_packed_struct.py b/test_regress/t/t_trace_packed_struct.py deleted file mode 100755 index 956d14f45..000000000 --- a/test_regress/t/t_trace_packed_struct.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(v_flags2=["--trace-vcd"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_trace_packed_struct_fst.out b/test_regress/t/t_trace_packed_struct_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_packed_struct_fst.out rename to test_regress/t/t_trace_packed_struct_cc_fst.out diff --git a/test_regress/t/t_trace_packed_struct_cc_fst.py b/test_regress/t/t_trace_packed_struct_cc_fst.py new file mode 100755 index 000000000..8146fe41d --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_packed_struct_common + +test.scenarios('vlt_all') + +trace_packed_struct_common.run(test) diff --git a/test_regress/t/t_trace_packed_struct_saif.out b/test_regress/t/t_trace_packed_struct_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_packed_struct_saif.out rename to test_regress/t/t_trace_packed_struct_cc_saif.out diff --git a/test_regress/t/t_trace_packed_struct_cc_saif.py b/test_regress/t/t_trace_packed_struct_cc_saif.py new file mode 100755 index 000000000..8146fe41d --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_packed_struct_common + +test.scenarios('vlt_all') + +trace_packed_struct_common.run(test) diff --git a/test_regress/t/t_trace_packed_struct_cc_vcd.out b/test_regress/t/t_trace_packed_struct_cc_vcd.out new file mode 100644 index 000000000..7bab9c9cd --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_cc_vcd.out @@ -0,0 +1,38 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 " clk $end + $scope module t $end + $var wire 1 " clk $end + $var wire 32 # cnt [31:0] $end + $var wire 96 $ v[2] [95:0] $end + $var wire 96 ' v[1] [95:0] $end + $var wire 96 * v[0] [95:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +0" +b00000000000000000000000000000000 # +b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 $ +b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 ' +b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 * +#10 +1" +b00000000000000000000000000000001 # +#15 +0" +#20 +1" +b00000000000000000000000000000010 # +#25 +0" +#30 +1" +b00000000000000000000000000000011 # +#35 +0" +#40 +1" diff --git a/test_regress/t/t_trace_packed_struct_cc_vcd.py b/test_regress/t/t_trace_packed_struct_cc_vcd.py new file mode 100755 index 000000000..8146fe41d --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_packed_struct_common + +test.scenarios('vlt_all') + +trace_packed_struct_common.run(test) diff --git a/test_regress/t/t_trace_packed_struct_fst.py b/test_regress/t/t_trace_packed_struct_fst.py deleted file mode 100755 index 82282acf6..000000000 --- a/test_regress/t/t_trace_packed_struct_fst.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_packed_struct.v" - -test.compile(v_flags2=["--trace-fst"]) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_packed_struct_fst_sc.py b/test_regress/t/t_trace_packed_struct_fst_sc.py deleted file mode 100755 index c946f98d6..000000000 --- a/test_regress/t/t_trace_packed_struct_fst_sc.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_packed_struct.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(v_flags2=["--sc --trace-fst"]) - -test.execute() - -test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_packed_struct_saif.py b/test_regress/t/t_trace_packed_struct_saif.py deleted file mode 100755 index 2368fa1fc..000000000 --- a/test_regress/t/t_trace_packed_struct_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_packed_struct.v" - -test.compile(v_flags2=["--trace-saif"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_packed_struct_fst_sc.out b/test_regress/t/t_trace_packed_struct_sc_fst.out similarity index 100% rename from test_regress/t/t_trace_packed_struct_fst_sc.out rename to test_regress/t/t_trace_packed_struct_sc_fst.out diff --git a/test_regress/t/t_trace_packed_struct_sc_fst.py b/test_regress/t/t_trace_packed_struct_sc_fst.py new file mode 100755 index 000000000..8146fe41d --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_sc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_packed_struct_common + +test.scenarios('vlt_all') + +trace_packed_struct_common.run(test) diff --git a/test_regress/t/t_trace_param.py b/test_regress/t/t_trace_param.py deleted file mode 100755 index 90b85c827..000000000 --- a/test_regress/t/t_trace_param.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.compile(v_flags2=["--trace-vcd"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_trace_param_fst.out b/test_regress/t/t_trace_param_fst.out new file mode 100644 index 000000000..10ff790db --- /dev/null +++ b/test_regress/t/t_trace_param_fst.out @@ -0,0 +1,32 @@ +$date + Thu Mar 12 07:53:08 2026 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$var wire 1 ! i_clk $end +$var wire 3 " i_d [2:0] $end +$var wire 3 # o_q [2:0] $end +$scope module my_module_types $end +$var parameter 32 $ MY_PARAM [31:0] $end +$var parameter 32 % MY_PARAM2 [31:0] $end +$upscope $end +$scope module t $end +$var wire 1 ! i_clk $end +$var wire 3 " i_d [2:0] $end +$var wire 3 # o_q [2:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b00000000000000000000000000001100 % +b00000000000000000000000000000011 $ +b000 # +b000 " +0! diff --git a/test_regress/t/t_trace_param_fst.py b/test_regress/t/t_trace_param_fst.py index fdc7a622b..e5e5b7be2 100755 --- a/test_regress/t/t_trace_param_fst.py +++ b/test_regress/t/t_trace_param_fst.py @@ -4,16 +4,12 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_param_common test.scenarios('vlt_all') -test.top_filename = "t/t_trace_param.v" -test.compile(v_flags2=["--trace-fst"]) - -test.execute() - -test.passes() +trace_param_common.run(test) diff --git a/test_regress/t/t_trace_param_saif.py b/test_regress/t/t_trace_param_saif.py index 1dd577e76..e5e5b7be2 100755 --- a/test_regress/t/t_trace_param_saif.py +++ b/test_regress/t/t_trace_param_saif.py @@ -4,18 +4,12 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_param_common test.scenarios('vlt_all') -test.top_filename = "t/t_trace_param.v" -test.compile(v_flags2=["--trace-saif"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_param_common.run(test) diff --git a/test_regress/t/t_trace_param_vcd.out b/test_regress/t/t_trace_param_vcd.out new file mode 100644 index 000000000..5847f7b9d --- /dev/null +++ b/test_regress/t/t_trace_param_vcd.out @@ -0,0 +1,25 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 " i_clk $end + $var wire 3 # i_d [2:0] $end + $var wire 3 $ o_q [2:0] $end + $scope module my_module_types $end + $var wire 32 % MY_PARAM [31:0] $end + $var wire 32 & MY_PARAM2 [31:0] $end + $upscope $end + $scope module t $end + $var wire 1 " i_clk $end + $var wire 3 # i_d [2:0] $end + $var wire 3 $ o_q [2:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +0" +b000 # +b000 $ +b00000000000000000000000000000011 % +b00000000000000000000000000001100 & diff --git a/test_regress/t/t_trace_param_vcd.py b/test_regress/t/t_trace_param_vcd.py new file mode 100755 index 000000000..e5e5b7be2 --- /dev/null +++ b/test_regress/t/t_trace_param_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_param_common + +test.scenarios('vlt_all') + +trace_param_common.run(test) diff --git a/test_regress/t/t_trace_primitive.py b/test_regress/t/t_trace_primitive.py deleted file mode 100755 index 26c203087..000000000 --- a/test_regress/t/t_trace_primitive.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(v_flags2=["--trace-vcd"]) - -test.execute() - -if test.vlt_all: - test.file_grep(test.trace_filename, "sub_t_i") - -test.passes() diff --git a/test_regress/t/t_trace_primitive_cc_fst.out b/test_regress/t/t_trace_primitive_cc_fst.out new file mode 100644 index 000000000..1a9331056 --- /dev/null +++ b/test_regress/t/t_trace_primitive_cc_fst.out @@ -0,0 +1,113 @@ +$date + Wed Mar 11 13:01:26 2026 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$var wire 1 ! clk $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc [31:0] $end +$var logic 1 # a $end +$var logic 1 $ b $end +$var logic 1 % z $end +$scope module sub_t_i $end +$var wire 1 # x $end +$var wire 1 $ y $end +$var wire 1 % z $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0% +0$ +0# +b00000000000000000000000000000000 " +0! +$end +#10 +1! +b00000000000000000000000000000001 " +#15 +0! +#20 +1! +b00000000000000000000000000000010 " +1# +#25 +0! +#30 +1! +0# +b00000000000000000000000000000011 " +1$ +#35 +0! +#40 +1! +b00000000000000000000000000000100 " +1# +1% +#45 +0! +#50 +1! +0% +0# +b00000000000000000000000000000101 " +0$ +#55 +0! +#60 +1! +b00000000000000000000000000000110 " +1# +#65 +0! +#70 +1! +0# +b00000000000000000000000000000111 " +1$ +#75 +0! +#80 +1! +b00000000000000000000000000001000 " +1# +1% +#85 +0! +#90 +1! +0% +0# +b00000000000000000000000000001001 " +0$ +#95 +0! +#100 +1! +b00000000000000000000000000001010 " +1# +#105 +0! +#110 +1! +0# +b00000000000000000000000000001011 " +1$ +#115 +0! +#120 +1! +b00000000000000000000000000001100 " +1# +1% diff --git a/test_regress/t/t_trace_primitive_cc_fst.py b/test_regress/t/t_trace_primitive_cc_fst.py new file mode 100755 index 000000000..364e68a7b --- /dev/null +++ b/test_regress/t/t_trace_primitive_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_primitive_common + +test.scenarios('vlt_all') + +trace_primitive_common.run(test) diff --git a/test_regress/t/t_trace_primitive_saif.out b/test_regress/t/t_trace_primitive_cc_saif.out similarity index 100% rename from test_regress/t/t_trace_primitive_saif.out rename to test_regress/t/t_trace_primitive_cc_saif.out diff --git a/test_regress/t/t_trace_primitive_cc_saif.py b/test_regress/t/t_trace_primitive_cc_saif.py new file mode 100755 index 000000000..364e68a7b --- /dev/null +++ b/test_regress/t/t_trace_primitive_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_primitive_common + +test.scenarios('vlt_all') + +trace_primitive_common.run(test) diff --git a/test_regress/t/t_trace_primitive_cc_vcd.out b/test_regress/t/t_trace_primitive_cc_vcd.out new file mode 100644 index 000000000..3eaf37271 --- /dev/null +++ b/test_regress/t/t_trace_primitive_cc_vcd.out @@ -0,0 +1,105 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 & clk $end + $scope module t $end + $var wire 1 & clk $end + $var wire 32 " cyc [31:0] $end + $var wire 1 # a $end + $var wire 1 $ b $end + $var wire 1 % z $end + $scope module sub_t_i $end + $var wire 1 # x $end + $var wire 1 $ y $end + $var wire 1 % z $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +0# +0$ +0% +0& +#10 +b00000000000000000000000000000001 " +1& +#15 +0& +#20 +b00000000000000000000000000000010 " +1# +1& +#25 +0& +#30 +b00000000000000000000000000000011 " +0# +1$ +1& +#35 +0& +#40 +b00000000000000000000000000000100 " +1# +1% +1& +#45 +0& +#50 +b00000000000000000000000000000101 " +0# +0$ +0% +1& +#55 +0& +#60 +b00000000000000000000000000000110 " +1# +1& +#65 +0& +#70 +b00000000000000000000000000000111 " +0# +1$ +1& +#75 +0& +#80 +b00000000000000000000000000001000 " +1# +1% +1& +#85 +0& +#90 +b00000000000000000000000000001001 " +0# +0$ +0% +1& +#95 +0& +#100 +b00000000000000000000000000001010 " +1# +1& +#105 +0& +#110 +b00000000000000000000000000001011 " +0# +1$ +1& +#115 +0& +#120 +b00000000000000000000000000001100 " +1# +1% +1& diff --git a/test_regress/t/t_trace_primitive_cc_vcd.py b/test_regress/t/t_trace_primitive_cc_vcd.py new file mode 100755 index 000000000..364e68a7b --- /dev/null +++ b/test_regress/t/t_trace_primitive_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_primitive_common + +test.scenarios('vlt_all') + +trace_primitive_common.run(test) diff --git a/test_regress/t/t_trace_primitive_fst.py b/test_regress/t/t_trace_primitive_fst.py deleted file mode 100755 index e0efa3ca4..000000000 --- a/test_regress/t/t_trace_primitive_fst.py +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_primitive.v" - -test.compile(v_flags2=["--trace-fst"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_trace_primitive_fst_sc.py b/test_regress/t/t_trace_primitive_fst_sc.py deleted file mode 100755 index 01bf153e3..000000000 --- a/test_regress/t/t_trace_primitive_fst_sc.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_primitive.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(v_flags2=["--sc --trace-fst"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_trace_primitive_saif.py b/test_regress/t/t_trace_primitive_saif.py deleted file mode 100755 index 4fa0dc08b..000000000 --- a/test_regress/t/t_trace_primitive_saif.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t/t_trace_primitive.v" - -test.compile(v_flags2=["--trace-saif"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_primitive_sc_fst.out b/test_regress/t/t_trace_primitive_sc_fst.out new file mode 100644 index 000000000..f0b3ea546 --- /dev/null +++ b/test_regress/t/t_trace_primitive_sc_fst.out @@ -0,0 +1,113 @@ +$date + Wed Mar 11 13:01:29 2026 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc [31:0] $end +$var logic 1 # a $end +$var logic 1 $ b $end +$var logic 1 % z $end +$scope module sub_t_i $end +$var wire 1 # x $end +$var wire 1 $ y $end +$var wire 1 % z $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0% +0$ +0# +b00000000000000000000000000000000 " +0! +$end +#10 +1! +b00000000000000000000000000000001 " +#15 +0! +#20 +1! +b00000000000000000000000000000010 " +1# +#25 +0! +#30 +1! +0# +b00000000000000000000000000000011 " +1$ +#35 +0! +#40 +1! +b00000000000000000000000000000100 " +1# +1% +#45 +0! +#50 +1! +0% +0# +b00000000000000000000000000000101 " +0$ +#55 +0! +#60 +1! +b00000000000000000000000000000110 " +1# +#65 +0! +#70 +1! +0# +b00000000000000000000000000000111 " +1$ +#75 +0! +#80 +1! +b00000000000000000000000000001000 " +1# +1% +#85 +0! +#90 +1! +0% +0# +b00000000000000000000000000001001 " +0$ +#95 +0! +#100 +1! +b00000000000000000000000000001010 " +1# +#105 +0! +#110 +1! +0# +b00000000000000000000000000001011 " +1$ +#115 +0! +#120 +1! +b00000000000000000000000000001100 " +1# +1% +#124 diff --git a/test_regress/t/t_trace_primitive_sc_fst.py b/test_regress/t/t_trace_primitive_sc_fst.py new file mode 100755 index 000000000..364e68a7b --- /dev/null +++ b/test_regress/t/t_trace_primitive_sc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_primitive_common + +test.scenarios('vlt_all') + +trace_primitive_common.run(test) diff --git a/test_regress/t/t_trace_rollover.out b/test_regress/t/t_trace_rollover.out index 9f8b917f8..b852a0a9c 100644 --- a/test_regress/t/t_trace_rollover.out +++ b/test_regress/t/t_trace_rollover.out @@ -1,4764 +1,4766 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module top $end - $var wire 1 # clk $end + $var wire 1 " clk $end $scope module t $end - $var wire 1 # clk $end - $var wire 32 $ cyc [31:0] $end + $var wire 1 " clk $end + $var wire 32 # cyc [31:0] $end + $var wire 32 $ unchanged [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 -1# -b00000000000000000000000000000000 $ -#1 -0# -#2 -1# -b00000000000000000000000000000001 $ -#3 -0# -#4 -1# -b00000000000000000000000000000010 $ -#5 -0# -#6 -1# -b00000000000000000000000000000011 $ -#7 -0# -#8 -1# -b00000000000000000000000000000100 $ -#9 -0# -#10 -1# -b00000000000000000000000000000101 $ -#11 -0# -#12 -1# -b00000000000000000000000000000110 $ -#13 -0# -#14 -1# -b00000000000000000000000000000111 $ -#15 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program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.top_filename = "t/t_trace_fst.v" -test.golden_filename = "t/t_trace_saif.out" - -test.compile(v_flags2=["--trace-saif"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_saif_cmake.out b/test_regress/t/t_trace_saif_cmake.out deleted file mode 100644 index c0e3c426f..000000000 --- a/test_regress/t/t_trace_saif_cmake.out +++ /dev/null @@ -1,509 +0,0 @@ -// Generated by verilated_saif -(SAIFILE -(SAIFVERSION "2.0") -(DIRECTION "backward") -(PROGRAM_NAME "Verilator") -(DIVIDER / ) -(TIMESCALE 1ps) -(DURATION 1000) - (INSTANCE top - (NET - (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) - (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) - (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) - (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) - ) - (INSTANCE t - (NET - (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) - (cyc\[0\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) - (cyc\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) - (cyc\[2\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25)) - (cyc\[3\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12)) - (cyc\[4\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6)) - (cyc\[5\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3)) - (cyc\[6\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1)) - (cyc\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (cyc\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) - (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) - (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) - (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) - (fst_gparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_gparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_real\[3\] (T0 1000) (T1 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(TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_longint\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_longint\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_longint\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_longint\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_longint\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_longint\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_longint\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_byte\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_byte\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_byte\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_byte\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_byte\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_byte\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_byte\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_byte\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_parameter\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_parameter\[4\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_parameter\[5\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_parameter\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_parameter\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_parameter\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_lparam\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_lparam\[7\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_lparam\[8\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_lparam\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_lparam\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_supply0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_tri0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) - (fst_tri (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - (INSTANCE test - (NET - (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) - (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) - (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) - (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) - (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) - (state_w\[0\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_w\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_w\[2\] (T0 430) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_w\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) - (state_w\[4\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) - (state_array[0]\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_array[0]\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) - (state_array[0]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_array[0]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) - (state_array[0]\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) - (state_array[1]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 47)) - (state_array[1]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_array[1]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_array[1]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) - (state_array[1]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_array[2]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) - (state_array[2]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_array[2]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_array[2]\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) - (state_array[2]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) - ) - ) - ) - ) -) diff --git a/test_regress/t/t_trace_saif_cmake.py b/test_regress/t/t_trace_saif_cmake.py deleted file mode 100755 index 73b4d1ebd..000000000 --- a/test_regress/t/t_trace_saif_cmake.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.top_filename = "t/t_trace_fst_cmake.v" - -test.compile(v_flags2=["--trace-saif"], verilator_make_gmake=False, verilator_make_cmake=True) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_saif_sc.py b/test_regress/t/t_trace_saif_sc.py deleted file mode 100755 index 648fa0834..000000000 --- a/test_regress/t/t_trace_saif_sc.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt_all') - -test.top_filename = "t/t_trace_fst_sc.v" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(verilator_flags2=["--trace-saif --sc"]) - -test.execute() - -test.saif_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_timing_trace.v b/test_regress/t/t_trace_timing.v similarity index 100% rename from test_regress/t/t_timing_trace.v rename to test_regress/t/t_trace_timing.v diff --git a/test_regress/t/t_timing_trace_fst.out b/test_regress/t/t_trace_timing_fst.out similarity index 100% rename from test_regress/t/t_timing_trace_fst.out rename to test_regress/t/t_trace_timing_fst.out diff --git a/test_regress/t/t_trace_timing_fst.py b/test_regress/t/t_trace_timing_fst.py new file mode 100755 index 000000000..0b80fe230 --- /dev/null +++ b/test_regress/t/t_trace_timing_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_timing_common + +test.scenarios('vlt_all') + +trace_timing_common.run(test) diff --git a/test_regress/t/t_timing_trace_saif.out b/test_regress/t/t_trace_timing_saif.out similarity index 100% rename from test_regress/t/t_timing_trace_saif.out rename to test_regress/t/t_trace_timing_saif.out diff --git a/test_regress/t/t_trace_timing_saif.py b/test_regress/t/t_trace_timing_saif.py new file mode 100755 index 000000000..0b80fe230 --- /dev/null +++ b/test_regress/t/t_trace_timing_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_timing_common + +test.scenarios('vlt_all') + +trace_timing_common.run(test) diff --git a/test_regress/t/t_timing_trace.out b/test_regress/t/t_trace_timing_vcd.out similarity index 100% rename from test_regress/t/t_timing_trace.out rename to test_regress/t/t_trace_timing_vcd.out diff --git a/test_regress/t/t_trace_timing_vcd.py b/test_regress/t/t_trace_timing_vcd.py new file mode 100755 index 000000000..0b80fe230 --- /dev/null +++ b/test_regress/t/t_trace_timing_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_timing_common + +test.scenarios('vlt_all') + +trace_timing_common.run(test) diff --git a/test_regress/t/t_trace_two_a.v b/test_regress/t/t_trace_two_a.v index 2d5829ede..f27143641 100644 --- a/test_regress/t/t_trace_two_a.v +++ b/test_regress/t/t_trace_two_a.v @@ -22,11 +22,7 @@ module t ( // verilator tracing_on initial begin -`ifdef TEST_FST - filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.fst"}; -`else - filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.vcd"}; -`endif + filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.", `STRINGIFY(`TRACE_FMT)}; `ifdef TEST_DUMP $dumpfile(filename); diff --git a/test_regress/t/t_trace_two_cc.cpp b/test_regress/t/t_trace_two_cc.cpp index bc0dfae5d..12e589ea4 100644 --- a/test_regress/t/t_trace_two_cc.cpp +++ b/test_regress/t/t_trace_two_cc.cpp @@ -12,11 +12,7 @@ #include "Vt_trace_two_b.h" #include "verilated.h" #ifdef TEST_HDR_TRACE -# ifdef TEST_FST -# include "verilated_fst_c.h" -# else -# include "verilated_vcd_c.h" -# endif +# include VL_STRINGIFY(TRACE_HEADER_C) #endif // clang-format on @@ -27,46 +23,34 @@ VM_PREFIX* ap; Vt_trace_two_b* bp; int main(int argc, char** argv) { - const std::unique_ptr contextp{new VerilatedContext}; + VerilatedContext context{}; uint64_t sim_time = 1100; - contextp->debug(0); - contextp->commandArgs(argc, argv); - contextp->traceEverOn(true); + context.debug(0); + context.commandArgs(argc, argv); + context.traceEverOn(true); srand48(5); - ap = new VM_PREFIX{contextp.get(), "topa"}; - bp = new Vt_trace_two_b{contextp.get(), "topb"}; - - // clang-format off -#ifdef TEST_HDR_TRACE - contextp->traceEverOn(true); -# ifdef TEST_FST - VerilatedFstC* tfp = new VerilatedFstC; - ap->trace(tfp, 99); - bp->trace(tfp, 99); - tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.fst"); -# else - VerilatedVcdC* tfp = new VerilatedVcdC; - ap->trace(tfp, 99); - bp->trace(tfp, 99); - tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); -# endif -#endif - // clang-format on + ap = new VM_PREFIX{&context, "topa"}; + bp = new Vt_trace_two_b{&context, "topb"}; #ifdef TEST_HDR_TRACE + VERILATED_TRACE_C* tfp = new VERILATED_TRACE_C; + ap->trace(tfp, 99); + bp->trace(tfp, 99); + tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx." VL_STRINGIFY(TRACE_FMT)); + ap->eval_step(); bp->eval_step(); ap->eval_end_step(); bp->eval_end_step(); - if (tfp) tfp->dump(contextp->time()); + if (tfp) tfp->dump(context.time()); #endif { ap->clk = false; - contextp->timeInc(10); + context.timeInc(10); } - while (contextp->time() < sim_time && !contextp->gotFinish()) { + while (context.time() < sim_time && !context.gotFinish()) { ap->clk = !ap->clk; bp->clk = ap->clk; ap->eval_step(); @@ -74,11 +58,11 @@ int main(int argc, char** argv) { ap->eval_end_step(); bp->eval_end_step(); #ifdef TEST_HDR_TRACE - if (tfp) tfp->dump(contextp->time()); + if (tfp) tfp->dump(context.time()); #endif - contextp->timeInc(5); + context.timeInc(5); } - if (!contextp->gotFinish()) { + if (!context.gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } ap->final(); diff --git a/test_regress/t/t_trace_two_dump_cc.py b/test_regress/t/t_trace_two_dump_cc.py deleted file mode 100755 index a100832af..000000000 --- a/test_regress/t/t_trace_two_dump_cc.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t_trace_two_a.v" -test.pli_filename = "t/t_trace_two_cc.cpp" - -test.compile(make_main=False, - verilator_make_gmake=False, - top_filename='t_trace_two_b.v', - vm_prefix='Vt_trace_two_b', - verilator_flags2=['-trace']) - -test.run(logfile=test.obj_dir + "/make_first_ALL.log", - cmd=[ - os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", - "Vt_trace_two_b__ALL.cpp" - ]) - -test.compile(make_main=False, - top_filename='t_trace_two_a.v', - verilator_flags2=['-exe', '-trace', test.pli_filename], - v_flags2=['+define+TEST_DUMP']) - -test.execute() - -if test.vlt_all: - test.file_grep(test.trace_filename, r'\$enddefinitions') - test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_two_dumpfst_cc.out b/test_regress/t/t_trace_two_dump_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_two_dumpfst_cc.out rename to test_regress/t/t_trace_two_dump_cc_fst.out diff --git a/test_regress/t/t_trace_two_dump_cc_fst.py b/test_regress/t/t_trace_two_dump_cc_fst.py new file mode 100755 index 000000000..5c068c551 --- /dev/null +++ b/test_regress/t/t_trace_two_dump_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_two_dump_cc_saif.out b/test_regress/t/t_trace_two_dump_cc_saif.out new file mode 100644 index 000000000..9ead8f3b4 --- /dev/null +++ b/test_regress/t/t_trace_two_dump_cc_saif.out @@ -0,0 +1,293 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 110) + (INSTANCE topa + (NET + (clk (T0 60) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 21)) + ) + (INSTANCE t + (NET + (clk (T0 60) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 21)) + (cyc\[0\] (T0 60) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11)) + (cyc\[1\] (T0 60) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5)) + (cyc\[2\] (T0 70) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) + (cyc\[3\] (T0 80) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) + (cyc\[4\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[5\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[6\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[7\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[8\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[9\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[10\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[11\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[12\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[13\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[14\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[15\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[16\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[17\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[18\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[19\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[20\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[21\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[22\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[23\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[24\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[25\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[26\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[27\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[28\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[29\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[30\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[31\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[0\] (T0 60) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10)) + (c_trace_on\[1\] (T0 60) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6)) + (c_trace_on\[2\] (T0 70) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) + (c_trace_on\[3\] (T0 70) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) + (c_trace_on\[4\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[5\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[6\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[7\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[8\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[9\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[10\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[11\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[12\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[13\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[14\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[15\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[16\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[17\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[18\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[19\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[20\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[21\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[22\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[23\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[24\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[25\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[26\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[27\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[28\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[29\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[30\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[31\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + (INSTANCE sub + (NET + (inside_sub_a\[0\] (T0 10) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) + (inside_sub_a\[1\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[2\] (T0 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0) (TC 0)) + (r\[17\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[18\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[19\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[20\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[21\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[22\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[23\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[24\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[25\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[26\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[27\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[28\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[29\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[30\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[31\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[32\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[33\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[34\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[35\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[36\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[37\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[38\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[39\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[40\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[41\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[42\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[43\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[44\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[45\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[46\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[47\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[48\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[49\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[50\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[51\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[52\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[53\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[54\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[55\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[56\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[57\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[58\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[59\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[60\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[61\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[62\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (r\[63\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + (INSTANCE sub + (NET + (inside_sub_a\[0\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[1\] (T0 10) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) + (inside_sub_a\[2\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[3\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[4\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[5\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[6\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[7\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[8\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[9\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[10\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[11\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[12\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[13\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[14\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[15\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[16\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[17\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[18\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[19\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[20\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[21\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[22\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[23\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[24\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[25\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[26\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[27\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[28\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[29\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[30\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[31\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + ) + ) +) diff --git a/test_regress/t/t_trace_two_dump_cc_saif.py b/test_regress/t/t_trace_two_dump_cc_saif.py new file mode 100755 index 000000000..796e3105c --- /dev/null +++ b/test_regress/t/t_trace_two_dump_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_dump_cc.out b/test_regress/t/t_trace_two_dump_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_two_dump_cc.out rename to test_regress/t/t_trace_two_dump_cc_vcd.out diff --git a/test_regress/t/t_trace_two_dump_cc_vcd.py b/test_regress/t/t_trace_two_dump_cc_vcd.py new file mode 100755 index 000000000..796e3105c --- /dev/null +++ b/test_regress/t/t_trace_two_dump_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_dump_sc.py b/test_regress/t/t_trace_two_dump_sc.py deleted file mode 100755 index db421fb2f..000000000 --- a/test_regress/t/t_trace_two_dump_sc.py +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t_trace_two_a.v" -test.pli_filename = "t/t_trace_two_sc.cpp" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(make_main=False, - verilator_make_gmake=False, - top_filename='t_trace_two_b.v', - vm_prefix='Vt_trace_two_b', - verilator_flags2=['-sc -trace']) - -test.run(logfile=test.obj_dir + "/make_first_ALL.log", - cmd=[ - os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", - "Vt_trace_two_b__ALL.cpp" - ]) - -test.compile(make_main=False, - top_filename='t_trace_two_a.v', - verilator_flags2=['-sc', '-exe', '-trace', test.pli_filename], - v_flags2=['+define+TEST_DUMP']) - -test.execute() - -if test.vlt_all: - test.file_grep(test.trace_filename, r'\$enddefinitions') - test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_two_dump_sc.out b/test_regress/t/t_trace_two_dump_sc_vcd.out similarity index 100% rename from test_regress/t/t_trace_two_dump_sc.out rename to test_regress/t/t_trace_two_dump_sc_vcd.out diff --git a/test_regress/t/t_trace_two_dump_sc_vcd.py b/test_regress/t/t_trace_two_dump_sc_vcd.py new file mode 100755 index 000000000..796e3105c --- /dev/null +++ b/test_regress/t/t_trace_two_dump_sc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_dumpfst_cc.py b/test_regress/t/t_trace_two_dumpfst_cc.py deleted file mode 100755 index b7f599a1b..000000000 --- a/test_regress/t/t_trace_two_dumpfst_cc.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t_trace_two_a.v" -test.pli_filename = "t/t_trace_two_cc.cpp" - -test.compile(make_main=False, - verilator_make_gmake=False, - top_filename='t_trace_two_b.v', - vm_prefix='Vt_trace_two_b', - verilator_flags2=['--trace-fst --trace-threads 1 -DTEST_FST']) - -test.run(logfile=test.obj_dir + "/make_first_ALL.log", - cmd=[ - os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", - "Vt_trace_two_b__ALL.cpp" - ]) - -test.compile( - make_main=False, - top_filename='t_trace_two_a.v', - verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename], - v_flags2=['+define+TEST_DUMP']) - -test.execute() - -if test.vlt_all: - test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_two_hdr_cc.py b/test_regress/t/t_trace_two_hdr_cc.py deleted file mode 100755 index 8f21dfeb7..000000000 --- a/test_regress/t/t_trace_two_hdr_cc.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t_trace_two_a.v" -test.pli_filename = "t/t_trace_two_cc.cpp" - -test.compile(make_main=False, - verilator_make_gmake=False, - top_filename='t_trace_two_b.v', - vm_prefix='Vt_trace_two_b', - verilator_flags2=['-trace']) - -test.run(logfile=test.obj_dir + "/make_first_ALL.log", - cmd=[ - os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", - "Vt_trace_two_b__ALL.cpp" - ]) - -test.compile(make_main=False, - top_filename='t_trace_two_a.v', - make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE=1'], - verilator_flags2=['-exe', '-trace', test.pli_filename]) - -test.execute() - -if test.vlt_all: - test.file_grep(test.trace_filename, r'\$enddefinitions') - test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_two_hdrfst_cc.out b/test_regress/t/t_trace_two_hdr_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_two_hdrfst_cc.out rename to test_regress/t/t_trace_two_hdr_cc_fst.out diff --git a/test_regress/t/t_trace_two_hdr_cc_fst.py b/test_regress/t/t_trace_two_hdr_cc_fst.py new file mode 100755 index 000000000..5c068c551 --- /dev/null +++ b/test_regress/t/t_trace_two_hdr_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_two_hdr_cc_saif.out b/test_regress/t/t_trace_two_hdr_cc_saif.out new file mode 100644 index 000000000..42aeddb3f --- /dev/null +++ b/test_regress/t/t_trace_two_hdr_cc_saif.out @@ -0,0 +1,293 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 100) + (INSTANCE topa + (NET + (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19)) + ) + (INSTANCE t + (NET + (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19)) + (cyc\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11)) + (cyc\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5)) + (cyc\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) + (cyc\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) + (cyc\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[25\] (T0 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0)) + (inside_sub_a\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + ) + ) +) diff --git a/test_regress/t/t_trace_two_hdr_cc_saif.py b/test_regress/t/t_trace_two_hdr_cc_saif.py new file mode 100755 index 000000000..796e3105c --- /dev/null +++ b/test_regress/t/t_trace_two_hdr_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_hdr_cc.out b/test_regress/t/t_trace_two_hdr_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_two_hdr_cc.out rename to test_regress/t/t_trace_two_hdr_cc_vcd.out diff --git a/test_regress/t/t_trace_two_hdr_cc_vcd.py b/test_regress/t/t_trace_two_hdr_cc_vcd.py new file mode 100755 index 000000000..796e3105c --- /dev/null +++ b/test_regress/t/t_trace_two_hdr_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_hdr_sc.py b/test_regress/t/t_trace_two_hdr_sc.py deleted file mode 100755 index c5dce0997..000000000 --- a/test_regress/t/t_trace_two_hdr_sc.py +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') -test.top_filename = "t_trace_two_a.v" -test.pli_filename = "t/t_trace_two_sc.cpp" - -if not test.have_sc: - test.skip("No SystemC installed") - -test.compile(make_main=False, - verilator_make_gmake=False, - top_filename='t_trace_two_b.v', - vm_prefix='Vt_trace_two_b', - verilator_flags2=['-sc -trace']) - -test.run(logfile=test.obj_dir + "/make_first_ALL.log", - cmd=[ - os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", - "Vt_trace_two_b__ALL.cpp" - ]) - -test.compile(make_main=False, - top_filename='t_trace_two_a.v', - make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE'], - verilator_flags2=['-sc', '-exe', '-trace', test.pli_filename]) - -test.execute() - -if test.vlt_all: - test.file_grep(test.trace_filename, r'\$enddefinitions') - test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_two_hdr_sc.out b/test_regress/t/t_trace_two_hdr_sc_vcd.out similarity index 100% rename from test_regress/t/t_trace_two_hdr_sc.out rename to test_regress/t/t_trace_two_hdr_sc_vcd.out diff --git a/test_regress/t/t_trace_two_hdr_sc_vcd.py b/test_regress/t/t_trace_two_hdr_sc_vcd.py new file mode 100755 index 000000000..796e3105c --- /dev/null +++ b/test_regress/t/t_trace_two_hdr_sc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_hdrfst_cc.py b/test_regress/t/t_trace_two_hdrfst_cc.py deleted file mode 100755 index 161d13155..000000000 --- a/test_regress/t/t_trace_two_hdrfst_cc.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t_trace_two_a.v" -test.pli_filename = "t/t_trace_two_cc.cpp" - -test.compile(make_main=False, - verilator_make_gmake=False, - top_filename='t_trace_two_b.v', - vm_prefix='Vt_trace_two_b', - verilator_flags2=['--trace-fst --trace-threads 1']) - -test.run(logfile=test.obj_dir + "/make_first_ALL.log", - cmd=[ - os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", - "Vt_trace_two_b__ALL.cpp" - ]) - -test.compile( - make_main=False, - top_filename='t_trace_two_a.v', - make_flags=['CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"'], - verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename]) - -test.execute() - -if test.vlt_all: - test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_two_port_cc.py b/test_regress/t/t_trace_two_port_cc.py deleted file mode 100755 index e860eb274..000000000 --- a/test_regress/t/t_trace_two_port_cc.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t_trace_two_a.v" -test.pli_filename = "t/t_trace_two_cc.cpp" - -test.compile(make_main=False, - verilator_make_gmake=False, - top_filename='t_trace_two_b.v', - vm_prefix='Vt_trace_two_b', - verilator_flags2=['-trace']) - -test.run(logfile=test.obj_dir + "/make_first_ALL.log", - cmd=[ - os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", - "Vt_trace_two_b__ALL.cpp" - ]) - -test.compile(make_main=False, - top_filename='t_trace_two_a.v', - verilator_flags2=['-exe', '-trace', test.pli_filename], - v_flags2=['+define+TEST_DUMPPORTS']) - -test.execute() - -if test.vlt_all: - test.file_grep(test.trace_filename, r'\$enddefinitions') - test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_two_portfst_cc.out b/test_regress/t/t_trace_two_port_cc_fst.out similarity index 100% rename from test_regress/t/t_trace_two_portfst_cc.out rename to test_regress/t/t_trace_two_port_cc_fst.out diff --git a/test_regress/t/t_trace_two_port_cc_fst.py b/test_regress/t/t_trace_two_port_cc_fst.py new file mode 100755 index 000000000..5c068c551 --- /dev/null +++ b/test_regress/t/t_trace_two_port_cc_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test, verilator_flags2=["--trace-threads", "1"]) diff --git a/test_regress/t/t_trace_two_port_cc_saif.out b/test_regress/t/t_trace_two_port_cc_saif.out new file mode 100644 index 000000000..9ead8f3b4 --- /dev/null +++ b/test_regress/t/t_trace_two_port_cc_saif.out @@ -0,0 +1,293 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 110) + (INSTANCE topa + (NET + (clk (T0 60) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 21)) + ) + (INSTANCE t + (NET + (clk (T0 60) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 21)) + (cyc\[0\] (T0 60) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11)) + (cyc\[1\] (T0 60) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5)) + (cyc\[2\] (T0 70) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) + (cyc\[3\] (T0 80) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) + (cyc\[4\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[5\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[6\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[7\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[8\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[9\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[10\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[11\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[12\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[13\] (T0 110) (T1 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110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[15\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[16\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[17\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[18\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[19\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[20\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[21\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[22\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[23\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[24\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[25\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[26\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[27\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[28\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (c_trace_on\[29\] (T0 110) (T1 0) (TZ 0) (TX 0) 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(inside_sub_a\[15\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[16\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[17\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[18\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[19\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[20\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[21\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[22\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[23\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[24\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[25\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[26\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[27\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[28\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[29\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[30\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (inside_sub_a\[31\] (T0 110) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + ) + ) + ) +) diff --git a/test_regress/t/t_trace_two_port_cc_saif.py b/test_regress/t/t_trace_two_port_cc_saif.py new file mode 100755 index 000000000..796e3105c --- /dev/null +++ b/test_regress/t/t_trace_two_port_cc_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_port_cc.out b/test_regress/t/t_trace_two_port_cc_vcd.out similarity index 100% rename from test_regress/t/t_trace_two_port_cc.out rename to test_regress/t/t_trace_two_port_cc_vcd.out diff --git a/test_regress/t/t_trace_two_port_cc_vcd.py b/test_regress/t/t_trace_two_port_cc_vcd.py new file mode 100755 index 000000000..796e3105c --- /dev/null +++ b/test_regress/t/t_trace_two_port_cc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_port_sc.py b/test_regress/t/t_trace_two_port_sc.py deleted file mode 100755 index 320c1a2d7..000000000 --- a/test_regress/t/t_trace_two_port_sc.py +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -if not test.have_sc: - test.skip("No SystemC installed") - -top_filename = "t_trace_two_a.v" -test.pli_filename = "t/t_trace_two_sc.cpp" - -test.compile(make_main=False, - verilator_make_gmake=False, - top_filename='t_trace_two_b.v', - vm_prefix='Vt_trace_two_b', - verilator_flags2=['-sc -trace']) - -test.run(logfile=test.obj_dir + "/make_first_ALL.log", - cmd=[ - os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", - "Vt_trace_two_b__ALL.cpp" - ]) - -test.compile(make_main=False, - top_filename='t_trace_two_a.v', - verilator_flags2=['-sc', '-exe', '-trace', test.pli_filename], - v_flags2=['+define+TEST_DUMPPORTS']) - -test.execute() - -if test.vlt_all: - test.file_grep(test.trace_filename, r'\$enddefinitions') - test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_two_port_sc.out b/test_regress/t/t_trace_two_port_sc_vcd.out similarity index 100% rename from test_regress/t/t_trace_two_port_sc.out rename to test_regress/t/t_trace_two_port_sc_vcd.out diff --git a/test_regress/t/t_trace_two_port_sc_vcd.py b/test_regress/t/t_trace_two_port_sc_vcd.py new file mode 100755 index 000000000..796e3105c --- /dev/null +++ b/test_regress/t/t_trace_two_port_sc_vcd.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_two_common + +test.scenarios('vlt_all') + +trace_two_common.run(test) diff --git a/test_regress/t/t_trace_two_portfst_cc.py b/test_regress/t/t_trace_two_portfst_cc.py deleted file mode 100755 index 09fe16efd..000000000 --- a/test_regress/t/t_trace_two_portfst_cc.py +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of either the GNU Lesser General Public License Version 3 -# or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2024 Wilson Snyder -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -# Test tracing with two models instanced -import vltest_bootstrap - -test.scenarios('vlt_all') -test.top_filename = "t_trace_two_a.v" -test.pli_filename = "t/t_trace_two_cc.cpp" - -test.compile(make_main=False, - verilator_make_gmake=False, - top_filename='t_trace_two_b.v', - vm_prefix='Vt_trace_two_b', - verilator_flags2=['--trace-fst --trace-threads 1']) - -test.run(logfile=test.obj_dir + "/make_first_ALL.log", - cmd=[ - os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", - "Vt_trace_two_b__ALL.cpp" - ]) - -test.compile( - make_main=False, - top_filename='t_trace_two_a.v', - verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename], - v_flags2=['+define+TEST_DUMPPORTS']) - -test.execute() - -if test.vlt_all: - test.fst_identical(test.trace_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_two_sc.cpp b/test_regress/t/t_trace_two_sc.cpp index 586ed20df..ea098ae7b 100644 --- a/test_regress/t/t_trace_two_sc.cpp +++ b/test_regress/t/t_trace_two_sc.cpp @@ -12,7 +12,7 @@ #include "Vt_trace_two_b.h" #include "verilated.h" #ifdef TEST_HDR_TRACE -# include "verilated_vcd_sc.h" +# include VL_STRINGIFY(TRACE_HEADER_SC) #endif // clang-format on @@ -41,11 +41,11 @@ int sc_main(int argc, char** argv) { bp->clk(clk); #ifdef TEST_HDR_TRACE - VerilatedVcdSc* tfp = new VerilatedVcdSc; + VERILATED_TRACE_SC* tfp = new VERILATED_TRACE_SC; sc_core::sc_start(sc_core::SC_ZERO_TIME); ap->trace(tfp, 99); bp->trace(tfp, 99); - tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); + tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx." VL_STRINGIFY(TRACE_FMT)); #endif { clk = false; diff --git a/test_regress/t/trace_abort_common.py b/test_regress/t/trace_abort_common.py new file mode 100644 index 000000000..fafc25083 --- /dev/null +++ b/test_regress/t/trace_abort_common.py @@ -0,0 +1,34 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + mode, fmt = test.parse_name(r"t_trace_abort_(cc|sc)_([a-z]+)") + + if mode == "sc" and not test.have_sc: + test.skip("No SystemC installed") + + # All test use the same SV file + test.top_filename = "t/t_trace_abort.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + f"--{mode}", + f"--trace-{fmt}", + ] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute(fails=True) + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_array_common.py b/test_regress/t/trace_array_common.py new file mode 100644 index 000000000..dd78543d5 --- /dev/null +++ b/test_regress/t/trace_array_common.py @@ -0,0 +1,31 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + mode, fmt = test.parse_name(r"t_trace_array_(cc|sc)_([a-z]+)") + + if mode == "sc" and not test.have_sc: + test.skip("No SystemC installed") + + # All test use the same SV file + test.top_filename = "t/t_trace_array.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [f"--{mode}", f"--trace-{fmt}", "--trace-structs", "--trace-max-width", "0"] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_ascendingrange_common.py b/test_regress/t/trace_ascendingrange_common.py new file mode 100644 index 000000000..db99bdcaa --- /dev/null +++ b/test_regress/t/trace_ascendingrange_common.py @@ -0,0 +1,31 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + mode, fmt = test.parse_name(r"t_trace_ascendingrange_(cc|sc)_([a-z]+)") + + if mode == "sc" and not test.have_sc: + test.skip("No SystemC installed") + + # All test use the same SV file + test.top_filename = "t/t_trace_ascendingrange.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [f"--{mode}", f"--trace-{fmt}", "--trace-params", "-Wno-ASCRANGE"] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_basic_common.py b/test_regress/t/trace_basic_common.py new file mode 100644 index 000000000..67e581220 --- /dev/null +++ b/test_regress/t/trace_basic_common.py @@ -0,0 +1,38 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, cmake=False, verilator_flags2=()): + mode, fmt = test.parse_name(r"t_trace_basic_(cc|sc)_([a-z]+)") + + if mode == "sc" and not test.have_sc: + test.skip("No SystemC installed") + + # All test use the same SV file + test.top_filename = "t/t_trace_basic.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + f"--{mode}", + f"--trace-{fmt}", + ] + if mode == "sc": + flags.append("+define+SYSTEMC") + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags, + verilator_make_gmake=not cmake, + verilator_make_cmake=cmake) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_cat_common.py b/test_regress/t/trace_cat_common.py new file mode 100644 index 000000000..ebf57c6dd --- /dev/null +++ b/test_regress/t/trace_cat_common.py @@ -0,0 +1,57 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import os + + +def run(test, *, verilator_flags2=()): + variant, fmt = test.parse_name(r"t_trace_cat_(opennext|reopen|renew)_([a-z]+)") + + # All test use the same SV file + test.top_filename = "t/t_trace_cat.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + "--exe", + f"--trace-{fmt}", + "t/t_trace_cat.cpp", + "-CFLAGS", + f"-DTRACE_FMT={fmt}", + "-CFLAGS", + f"-DTRACE_HEADER_C=verilated_{fmt}_c.h", + "-CFLAGS", + f"-DVERILATED_TRACE_C=Verilated{fmt.capitalize()}C", + ] + match variant: + case "opennext": + flags.extend(["-CFLAGS", "-DTRACE_OPENNEXT"]) + case "reopen": + flags.extend(["-CFLAGS", "-DTRACE_REOPEN"]) + case "renew": + flags.extend(["-CFLAGS", "-DTRACE_RENEW"]) + flags.extend(verilator_flags2) + + # Run test + test.compile(make_top_shell=False, make_main=False, verilator_flags2=flags) + + test.execute() + + if variant == "opennext": + os.system("cat" + \ + " " + test.obj_dir + "/simx_part_0000.vcd" + \ + " " + test.obj_dir + "/simx_part_0000_cat*.vcd" + \ + " > " + test.obj_dir + "/simall.vcd") + test.vcd_identical(test.obj_dir + "/simall.vcd", test.golden_filename) + else: + test.trace_identical(test.trace_filename.replace(f".{fmt}", f"_part_0000.{fmt}"), + test.golden_filename.replace(".out", "_part_0000.out")) + test.trace_identical(test.trace_filename.replace(f".{fmt}", f"_part_0100.{fmt}"), + test.golden_filename.replace(".out", "_part_0100.out")) + + test.passes() diff --git a/test_regress/t/trace_complex_common.py b/test_regress/t/trace_complex_common.py new file mode 100644 index 000000000..388ae333e --- /dev/null +++ b/test_regress/t/trace_complex_common.py @@ -0,0 +1,41 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + variant, mode, fmt = test.parse_name(r"t_trace_complex_([a-z]+)_(cc|sc)_([a-z]+)") + + if mode == "sc" and not test.have_sc: + test.skip("No SystemC installed") + + # All test use the same SV file + test.top_filename = "t/t_trace_complex.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + # Flags that influence expected results + flags = [f"--{mode}", f"--trace-{fmt}"] + match variant: + case "default": + pass + case "params": + flags.extend(["--trace-params", "--no-trace-structs"]) + case "structs": + flags.extend(["--no-trace-params", "--trace-structs"]) + case _: + test.error(f"Unhandled test variant '{variant}'") + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_dumpvars_dyn_common.py b/test_regress/t/trace_dumpvars_dyn_common.py new file mode 100644 index 000000000..de53a0390 --- /dev/null +++ b/test_regress/t/trace_dumpvars_dyn_common.py @@ -0,0 +1,47 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + variant, mode, fmt = test.parse_name(r"t_trace_dumpvars_dyn_(0|1)_(cc|sc)_([a-z]+)") + + if mode == "sc" and not test.have_sc: + test.skip("No SystemC installed") + + # All test use the same SV file + test.top_filename = "t/t_trace_dumpvars_dyn.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + f"--{mode}", + "--exe", + f"--trace-{fmt}", + "t/t_trace_dumpvars_dyn.cpp", + "-CFLAGS", + f"-DTRACE_FMT={fmt}", + "-CFLAGS", + f"-DTRACE_HEADER_C=verilated_{fmt}_c.h", + "-CFLAGS", + f"-DVERILATED_TRACE_C=Verilated{fmt.capitalize()}C", + ] + match variant: + case "0": + flags.extend(["-CFLAGS", "-DTEST_VARIANT_0"]) + case "1": + flags.extend(["-CFLAGS", "-DTEST_VARIANT_1"]) + flags.extend(verilator_flags2) + + # Run test + test.compile(make_main=False, verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_enum_common.py b/test_regress/t/trace_enum_common.py new file mode 100644 index 000000000..0e5a383f9 --- /dev/null +++ b/test_regress/t/trace_enum_common.py @@ -0,0 +1,28 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + fmt, = test.parse_name(r"t_trace_enum_([a-z]+)") + + # All test use the same SV file + test.top_filename = "t/t_trace_enum.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [f"--trace-{fmt}", "--output-split-ctrace", "1"] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_event_common.py b/test_regress/t/trace_event_common.py new file mode 100644 index 000000000..8da947aa7 --- /dev/null +++ b/test_regress/t/trace_event_common.py @@ -0,0 +1,32 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + fmt, = test.parse_name(r"t_trace_event_([a-z]+)") + + # All test use the same SV file + test.top_filename = "t/t_trace_event.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + "--binary", + f"--trace-{fmt}", + '--dumpi-V3Trace 9' # Dev coverage of the V3DumpFinder debug code + ] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_hier_block_common.py b/test_regress/t/trace_hier_block_common.py new file mode 100644 index 000000000..c92175c61 --- /dev/null +++ b/test_regress/t/trace_hier_block_common.py @@ -0,0 +1,101 @@ +# pylint: disable=R0914 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import re + + +def run(test, *, verilator_flags2=()): + variant, mode, fmt = test.parse_name( + r"t_trace_hier_block_(default|notop|statefulpkg)_(cc|sc)_([a-z]+)") + + # All test use the same SV file + test.top_filename = "t/t_hier_block.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + verilator_common_flags = [] + match mode: + case "cc": + verilator_common_flags.extend([ # + "--cc", + ]) + case "sc": + verilator_common_flags.extend([ # + "--sc", + "--CFLAGS", + '"-pipe -DCPP_MACRO=cplusplus"', + ]) + case _: + test.error(f"Unknown mode '{mode}'") + + verilator_common_flags.extend([ + f"--trace-{fmt}", + "--trace-underscore", # Should not trace __Vhandle + "--trace-max-width", + "0", + "--trace-max-array", + "0", + "--trace-structs", + "t/t_hier_block.cpp" + ]) + + main_top_name = "top" + match variant: + case "default": + pass + case "notop": + main_top_name = "" + case "statefulpkg": + verilator_common_flags.append("+define+STATEFUL_PKG") + case _: + test.error(f"Unhandled test variant '{variant}'") + + verilator_common_flags.extend(verilator_flags2) + verilator_hier_flags = verilator_common_flags + ['--hierarchical'] + + # Compile hierarchically + test.vm_prefix = "Vhier" + test.main_filename = test.obj_dir + "/Vhier__main.cpp" + test.compile(verilator_flags2=verilator_hier_flags, main_top_name=main_top_name) + + # Compile non-hierarchically + test.vm_prefix = "Vnonh" + test.main_filename = test.obj_dir + "/Vnonh__main.cpp" + test.compile(verilator_flags2=verilator_common_flags, main_top_name=main_top_name) + + trace_hier = test.trace_filename.replace("simx", "hier") + trace_nonh = test.trace_filename.replace("simx", "nonh") + + # Run the hierarchical model + test.execute(executable=test.obj_dir + "/Vhier") + test.run(cmd=["mv", test.trace_filename, trace_hier]) + # Run the non hierarchical model + test.execute(executable=test.obj_dir + "/Vnonh") + test.run(cmd=["mv", test.trace_filename, trace_nonh]) + + if variant != "statefulpkg": + # Scope structure must match exactly, check only in vcd + if fmt == "vcd": + with open(trace_nonh, 'r', encoding='utf8') as fnonh, \ + open(trace_hier, 'r', encoding='utf8') as fhier: + for la, lb in zip(fnonh, fhier): + la = re.sub(r'^(\s*\$var\s+\S+\s+\S+\s+)\S+(.*)$', r'\1CODE\2', la) + lb = re.sub(r'^(\s*\$var\s+\S+\s+\S+\s+)\S+(.*)$', r'\1CODE\2', lb) + if la != lb: + test.error_keep_going("VCD header mismatch: '{}' !~ '{}'".format( + la.strip(), lb.strip())) + if "enddefinitions" in la: + break + + # The two models must match ignoring enum attributes which can differ + test.trace_identical(trace_hier, trace_nonh, ignore_attr=True) + # The hierarchical must match the reference + test.trace_identical(trace_hier, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_hier_common.py b/test_regress/t/trace_hier_common.py new file mode 100644 index 000000000..70afb1275 --- /dev/null +++ b/test_regress/t/trace_hier_common.py @@ -0,0 +1,31 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + fmt, = test.parse_name(r"t_trace_hier_([a-z]+)") + + # All test use the same SV file + test.top_filename = "t/t_trace_hier.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + f"--trace-{fmt}", "-j", "4", "t/t_trace_hier_sub/t_trace_hier.vlt", "--top-module", "t", + "--hierarchical", "-F", "t/t_trace_hier_sub/top.vc" + ] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_interface_ref_common.py b/test_regress/t/trace_interface_ref_common.py new file mode 100644 index 000000000..7bfbd8564 --- /dev/null +++ b/test_regress/t/trace_interface_ref_common.py @@ -0,0 +1,35 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + mode, fmt = test.parse_name(r"t_trace_interface_ref_(cc|sc)_([a-z]+)") + + if mode == "sc" and not test.have_sc: + test.skip("No SystemC installed") + + # All test use the same SV file + test.top_filename = "t/t_trace_interface_ref.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + f"--{mode}", + f"--trace-{fmt}", + "--trace-structs", + ] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_no_top_name2_common.py b/test_regress/t/trace_no_top_name2_common.py new file mode 100644 index 000000000..aed39821a --- /dev/null +++ b/test_regress/t/trace_no_top_name2_common.py @@ -0,0 +1,38 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + fmt, = test.parse_name(r"t_trace_no_top_name2_([a-z]+)") + + # All test use the same SV file + test.top_filename = "t/t_trace_no_top_name2.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + "--exe", + f"--trace-{fmt}", + "t/t_trace_no_top_name2.cpp", + "-CFLAGS", + f"-DTRACE_FMT={fmt}", + "-CFLAGS", + f"-DTRACE_HEADER_C=verilated_{fmt}_c.h", + "-CFLAGS", + f"-DVERILATED_TRACE_C=Verilated{fmt.capitalize()}C", + ] + flags.extend(verilator_flags2) + + # Run test + test.compile(make_main=False, verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_no_top_name_common.py b/test_regress/t/trace_no_top_name_common.py new file mode 100644 index 000000000..1cb4bb3d8 --- /dev/null +++ b/test_regress/t/trace_no_top_name_common.py @@ -0,0 +1,28 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + fmt, = test.parse_name(r"t_trace_no_top_name_([a-z]+)") + + # All test use the same SV file + test.top_filename = "t/t_trace_no_top_name.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = ["--binary", "--main-top-name", "'-'", f"--trace-{fmt}", "-Wno-MULTITOP"] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_packed_struct_common.py b/test_regress/t/trace_packed_struct_common.py new file mode 100644 index 000000000..c994cc732 --- /dev/null +++ b/test_regress/t/trace_packed_struct_common.py @@ -0,0 +1,34 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + mode, fmt = test.parse_name(r"t_trace_packed_struct_(cc|sc)_([a-z]+)") + + if mode == "sc" and not test.have_sc: + test.skip("No SystemC installed") + + # All test use the same SV file + test.top_filename = "t/t_trace_packed_struct.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + f"--{mode}", + f"--trace-{fmt}", + ] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_param_common.py b/test_regress/t/trace_param_common.py new file mode 100644 index 000000000..8ab775b66 --- /dev/null +++ b/test_regress/t/trace_param_common.py @@ -0,0 +1,31 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + fmt, = test.parse_name(r"t_trace_param_([a-z]+)") + + # All test use the same SV file + test.top_filename = "t/t_trace_param.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + "--cc", + f"--trace-{fmt}", + ] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_primitive_common.py b/test_regress/t/trace_primitive_common.py new file mode 100644 index 000000000..fd33ad5c9 --- /dev/null +++ b/test_regress/t/trace_primitive_common.py @@ -0,0 +1,34 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + mode, fmt = test.parse_name(r"t_trace_primitive_(cc|sc)_([a-z]+)") + + if mode == "sc" and not test.have_sc: + test.skip("No SystemC installed") + + # All test use the same SV file + test.top_filename = "t/t_trace_primitive.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = [ + f"--{mode}", + f"--trace-{fmt}", + ] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_timing_common.py b/test_regress/t/trace_timing_common.py new file mode 100644 index 000000000..833cfc4c2 --- /dev/null +++ b/test_regress/t/trace_timing_common.py @@ -0,0 +1,28 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + + +def run(test, *, verilator_flags2=()): + fmt, = test.parse_name(r"t_trace_timing_([a-z]+)") + + # All test use the same SV file + test.top_filename = "t/t_trace_timing.v" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + flags = ["--binary", f"--trace-{fmt}", "-Wno-MINTYPMAXDLY"] + flags.extend(verilator_flags2) + + # Run test + test.compile(verilator_flags2=flags) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes() diff --git a/test_regress/t/trace_two_common.py b/test_regress/t/trace_two_common.py new file mode 100644 index 000000000..ff7487f50 --- /dev/null +++ b/test_regress/t/trace_two_common.py @@ -0,0 +1,83 @@ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import os + + +def run(test, *, verilator_flags2=()): + variant, mode, fmt = test.parse_name(r"t_trace_two_(dump|port|hdr)_(cc|sc)_([a-z]+).*") + + if mode == "sc" and not test.have_sc: + test.skip("No SystemC installed") + + # All test use the same SV file + test.top_filename = "t/t_trace_two_a.v" + # Main driver file depends on mode + main_filename = f"t/t_trace_two_{mode}.cpp" + # Any variations after the format name must yield the exact same trace + test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out" + + common_flags = [ + f"--{mode}", + f"--trace-{fmt}", + f"+define+TRACE_FMT={fmt}", + "-CFLAGS", + f"-DTRACE_FMT={fmt}", + ] + match mode: + case "cc": + common_flags.extend([ + "-CFLAGS", + f"-DTRACE_HEADER_C=verilated_{fmt}_c.h", + "-CFLAGS", + f"-DVERILATED_TRACE_C=Verilated{fmt.capitalize()}C", + ]) + case "sc": + common_flags.extend([ + "-CFLAGS", + f"-DTRACE_HEADER_SC=verilated_{fmt}_sc.h", + "-CFLAGS", + f"-DVERILATED_TRACE_SC=Verilated{fmt.capitalize()}Sc", + ]) + case _: + test.error(f"Unhandled test mode '{mode}'") + match variant: + case "dump": + common_flags.append("+define+TEST_DUMP") + case "port": + common_flags.append("+define+TEST_DUMPPORTS") + case "hdr": + common_flags.extend(["-CFLAGS", "-DTEST_HDR_TRACE=1"]) + case _: + test.error(f"Unhandled test variant '{variant}'") + common_flags.extend(verilator_flags2) + + # Verilate 'b' + test.compile(make_main=False, + verilator_make_gmake=False, + top_filename='t_trace_two_b.v', + vm_prefix='Vt_trace_two_b', + verilator_flags2=common_flags) + + # Create the ALL.cpp for 'b' + test.run(logfile=test.obj_dir + "/make_first_ALL.log", + cmd=[ + os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", + "Vt_trace_two_b__ALL.cpp" + ]) + + # Build 'a', this includes ALL.cpp for 'b' + test.compile(make_main=False, + top_filename='t_trace_two_a.v', + verilator_flags2=common_flags + ['--exe', main_filename]) + + test.execute() + + test.trace_identical(test.trace_filename, test.golden_filename) + + test.passes()