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Fix parse error on output reg signed 

git-svn-id: file://localhost/svn/verilator/trunk/verilator@986 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2008-02-08 18:38:47 +00:00
parent e4297486ef
commit 4977a5e1d9
2 changed files with 18 additions and 13 deletions
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12
src/verilog.y
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@ -526,15 +526,15 @@ regsigList: regsig { $$ = $1; }
| regsigList ',' regsig { $$ = $1;$1->addNext($3); } | regsigList ',' regsig { $$ = $1;$1->addNext($3); }
; ;
portV2kDecl: varRESET varInput signingE v2kNetDeclE regrangeE portV2kSig { $$ = $6; } portV2kDecl: varRESET varInput v2kNetDeclE signingE regrangeE portV2kSig { $$ = $6; }
| varRESET varInout signingE v2kNetDeclE regrangeE portV2kSig { $$ = $6; } | varRESET varInout v2kNetDeclE signingE regrangeE portV2kSig { $$ = $6; }
| varRESET varOutput signingE v2kVarDeclE regrangeE portV2kSig { $$ = $6; } | varRESET varOutput v2kVarDeclE signingE regrangeE portV2kSig { $$ = $6; }
; ;
// IEEE: port_declaration - plus ';' // IEEE: port_declaration - plus ';'
portDecl: varRESET varInput signingE v2kVarDeclE regrangeE sigList ';' { $$ = $6; } portDecl: varRESET varInput v2kVarDeclE signingE regrangeE sigList ';' { $$ = $6; }
| varRESET varInout signingE v2kVarDeclE regrangeE sigList ';' { $$ = $6; } | varRESET varInout v2kVarDeclE signingE regrangeE sigList ';' { $$ = $6; }
| varRESET varOutput signingE v2kVarDeclE regrangeE sigList ';' { $$ = $6; } | varRESET varOutput v2kVarDeclE signingE regrangeE sigList ';' { $$ = $6; }
; ;
varDecl: varRESET varReg signingE regrangeE regsigList ';' { $$ = $5; } varDecl: varRESET varReg signingE regrangeE regsigList ';' { $$ = $5; }

19
test_regress/t/t_math_mul.v
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@ -15,21 +15,24 @@ module t (/*AUTOARG*/
reg [63:0] crc; reg [63:0] crc;
reg [63:0] sum; reg [63:0] sum;
reg [31:0] out1; wire [31:0] out1;
sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1)); wire [31:0] out2;
sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2);
always @ (posedge clk) begin always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1); `ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
`endif
cyc <= cyc + 1; cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {32'h0,out1}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
if (cyc==1) begin if (cyc==1) begin
// Setup // Setup
crc <= 64'h00000000_00000097; crc <= 64'h00000000_00000097;
sum <= 64'h0; sum <= 64'h0;
end end
else if (cyc==90) begin else if (cyc==90) begin
if (sum !== 64'hc1f743ad62c2c04d) $stop; if (sum !== 64'he396068aba3898a2) $stop;
end end
else if (cyc==91) begin else if (cyc==91) begin
end end
@ -49,18 +52,20 @@ endmodule
module sub (/*AUTOARG*/ module sub (/*AUTOARG*/
// Outputs // Outputs
out1, out1, out2,
// Inputs // Inputs
in1, in2 in1, in2
); );
input [15:0] in1; input [15:0] in1;
input [15:0] in2; input [15:0] in2;
output reg [31:0] out1; output reg signed [31:0] out1;
output reg unsigned [31:0] out2;
always @* begin always @* begin
// verilator lint_off WIDTH // verilator lint_off WIDTH
out1 = $signed(in1) * $signed(in2); out1 = $signed(in1) * $signed(in2);
out2 = $unsigned(in1) * $unsigned(in2);
// verilator lint_on WIDTH // verilator lint_on WIDTH
end end