From 4977a5e1d9c9353a5619de7dd6da2bad93bce412 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 8 Feb 2008 18:38:47 +0000
Subject: [PATCH] Fix parse error on output reg signed

git-svn-id: file://localhost/svn/verilator/trunk/verilator@986 77ca24e4-aefa-0310-84f0-b9a241c72d87
---
 src/verilog.y               | 12 ++++++------
 test_regress/t/t_math_mul.v | 19 ++++++++++++-------
 2 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/src/verilog.y b/src/verilog.y
index 0cd6a9085..519a8249f 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -526,15 +526,15 @@ regsigList:	regsig  				{ $$ = $1; }
 	|	regsigList ',' regsig		       	{ $$ = $1;$1->addNext($3); }
 	;
 
-portV2kDecl:	varRESET varInput  signingE v2kNetDeclE regrangeE portV2kSig	{ $$ = $6; }
-	|	varRESET varInout  signingE v2kNetDeclE regrangeE portV2kSig	{ $$ = $6; }
-	|	varRESET varOutput signingE v2kVarDeclE regrangeE portV2kSig	{ $$ = $6; }
+portV2kDecl:	varRESET varInput  v2kNetDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
+	|	varRESET varInout  v2kNetDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
+	|	varRESET varOutput v2kVarDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
 	;
 
 // IEEE: port_declaration - plus ';'
-portDecl:	varRESET varInput  signingE v2kVarDeclE regrangeE  sigList ';'	{ $$ = $6; }
-     	|	varRESET varInout  signingE v2kVarDeclE regrangeE  sigList ';'	{ $$ = $6; }
-     	|	varRESET varOutput signingE v2kVarDeclE regrangeE  sigList ';'	{ $$ = $6; }
+portDecl:	varRESET varInput  v2kVarDeclE signingE regrangeE  sigList ';'	{ $$ = $6; }
+     	|	varRESET varInout  v2kVarDeclE signingE regrangeE  sigList ';'	{ $$ = $6; }
+     	|	varRESET varOutput v2kVarDeclE signingE regrangeE  sigList ';'	{ $$ = $6; }
 	;
 
 varDecl:	varRESET varReg     signingE regrangeE  regsigList ';'	{ $$ = $5; }
diff --git a/test_regress/t/t_math_mul.v b/test_regress/t/t_math_mul.v
index cc35ad092..3b6d408b1 100644
--- a/test_regress/t/t_math_mul.v
+++ b/test_regress/t/t_math_mul.v
@@ -15,21 +15,24 @@ module t (/*AUTOARG*/
    reg [63:0] crc;
    reg [63:0] sum;
 
-   reg [31:0] out1;
-   sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1));
+   wire [31:0] out1;
+   wire [31:0] out2;
+   sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2);
 
    always @ (posedge clk) begin
-      //$write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1);
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
+`endif
       cyc <= cyc + 1;
       crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
-      sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {32'h0,out1};
+      sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
       if (cyc==1) begin
 	 // Setup
 	 crc <= 64'h00000000_00000097;
 	 sum <= 64'h0;
       end
       else if (cyc==90) begin
-	 if (sum !== 64'hc1f743ad62c2c04d) $stop;
+	 if (sum !== 64'he396068aba3898a2) $stop;
       end
       else if (cyc==91) begin
       end
@@ -49,18 +52,20 @@ endmodule
 
 module sub (/*AUTOARG*/
    // Outputs
-   out1,
+   out1, out2,
    // Inputs
    in1, in2
    );
 
    input      [15:0] in1;
    input      [15:0] in2;
-   output reg [31:0] out1;
+   output reg signed [31:0] out1;
+   output reg unsigned [31:0] out2;
    
    always @* begin
       // verilator lint_off WIDTH
       out1 = $signed(in1) * $signed(in2);
+      out2 = $unsigned(in1) * $unsigned(in2);
       // verilator lint_on WIDTH
    end