Replaced test_c/test_sc with new examples/ directory.

examples/tracing_c/sim_main.cpp

@@ -0,0 +1,114 @@
+// DESCRIPTION: Verilator: Verilog example module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+//======================================================================
+
+// Include common routines
+#include <verilated.h>
+
+#include <sys/stat.h>  // mkdir
+
+// Include model header, generated from Verilating "top.v"
+#include "Vtop.h"
+
+// If "verilator --trace" is used, include the tracing class
+#if VM_TRACE
+# include <verilated_vcd_c.h>
+#endif
+
+// Current simulation time (64-bit unsigned)
+vluint64_t main_time = 0;
+// Called by $time in Verilog
+double sc_time_stamp () {
+    return main_time; // Note does conversion to real, to match SystemC
+}
+
+int main(int argc, char** argv, char** env) {
+    // This is a more complicated example, please also see the simpler examples/hello_world_c.
+
+    // Prevent unused variable warnings
+    if (0 && argc && argv && env) {}
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    Verilated::commandArgs(argc, argv);
+
+    // Set debug level, 0 is off, 9 is highest presently used
+    Verilated::debug(0);
+
+    // Randomization reset policy
+    Verilated::randReset(2);
+
+    // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
+    Vtop* top = new Vtop; // Or use a const unique_ptr, or the VL_UNIQUE_PTR wrapper
+
+    // If verilator was invoked with --trace, open trace
+#if VM_TRACE
+    Verilated::traceEverOn(true);  // Verilator must compute traced signals
+    VL_PRINTF("Enabling waves into logs/vlt_dump.vcd...\n");
+    VerilatedVcdC* tfp = new VerilatedVcdC;
+    top->trace(tfp, 99);  // Trace 99 levels of hierarchy
+    mkdir("logs", 0777);
+    tfp->open("logs/vlt_dump.vcd");  // Open the dump file
+#endif
+
+    // Set some inputs
+    top->reset_l = !0;
+    top->fastclk = 0;
+    top->clk = 0;
+    top->in_small = 1;
+    top->in_quad = 0x1234;
+    top->in_wide[0] = 0x1;
+    top->in_wide[1] = 0x22222222;
+    top->in_wide[2] = 0x33333333;
+
+    // Simulate until $finish
+    while (!Verilated::gotFinish()) {
+	main_time++;  // Time passes...
+
+	// Toggle clocks and such
+	top->fastclk = !top->fastclk;
+	if ((main_time % 10) == 3) {
+	    top->clk = 1;
+	}
+	if ((main_time % 10) == 8) {
+	    top->clk = 0;
+	}
+	if (main_time > 1 && main_time < 10) {
+	    top->reset_l = !1;  // Assert reset
+	} else {
+	    top->reset_l = !0;  // Deassert reset
+	}
+
+	// Assign some other inputs
+	top->in_quad += 0x12;
+
+	// Evaluate model
+	top->eval();
+
+    	// Read outputs
+	VL_PRINTF ("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x"
+		   " -> oquad=%" VL_PRI64"x owide=%x_%08x_%08x\n",
+		   main_time, top->clk, top->reset_l, top->in_quad,
+		   top->out_quad, top->out_wide[2], top->out_wide[1], top->out_wide[0]);
+    }
+
+    // Final model cleanup
+    top->final();
+
+    // Close trace if opened
+#if VM_TRACE
+    if (tfp) { tfp->close(); }
+#endif
+
+    //  Coverage analysis (since test passed)
+#if VM_COVERAGE
+    mkdir("logs", 0777);
+    VerilatedCov::write("logs/coverage.dat");
+#endif
+
+    // Destroy model
+    delete top; top = NULL;
+
+    // Fin
+    exit(0);
+}