diff --git a/Changes b/Changes index 417d83f58..2c0f22857 100644 --- a/Changes +++ b/Changes @@ -4,6 +4,9 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 3.913 devel +** Added new examples/ directory with appropriate examples. This replaces the + old test_c and test_sc directories. + *** Add --getenv option. **** The internal test_verilated test directory is moved to be part of test_regress. diff --git a/Makefile.in b/Makefile.in index 2381ebf7f..ed9a8a217 100644 --- a/Makefile.in +++ b/Makefile.in @@ -101,7 +101,9 @@ PACKAGE_VERSION = @PACKAGE_VERSION@ SHELL = /bin/sh -SUBDIRS = src test_c test_sc test_regress +SUBDIRS = src test_regress \ + examples/hello_world_c examples/hello_world_sc \ + examples/tracing_c examples/tracing_sc \ INFOS = README README.html README.pdf internals.txt internals.html \ internals.pdf verilator.txt verilator.html verilator.pdf \ @@ -127,6 +129,8 @@ DISTFILES_INC = $(INFOS) .gitignore Artistic COPYING COPYING.LESSER \ src/vlcovgen \ src/.gdbinit \ src/*.pl src/*.pod \ + examples/*/.*ignore examples/*/Makefile* \ + examples/*/*.[chv]* examples/*/*.pl \ test_*/.*ignore test_*/Makefile* test_*/*.cpp \ test_*/*.pl test_*/*.v test_*/*.vc test_*/*.vh \ test_regress/t/t*/*.sv* \ @@ -181,31 +185,33 @@ verilator_exe verilator_bin verilator_bin_dbg verilator_coverage_bin_dbg: msg_test: all_nomsg @echo "Build complete!" @echo - @echo "Type 'make test' to test." + @echo "Now type 'make test' to test." @echo -.PHONY:test +.PHONY: test ifeq ($(CFG_WITH_LONGTESTS),yes) # Local... Else don't burden users -test: test_c test_sc test_regress +test: smoke-test examples test_regress else -test: test_c test_sc +test: smoke-test examples endif @echo "Tests passed!" @echo - @echo "Type 'make install' to install documentation." + @echo "Now type 'make install' to install." + @echo "Or type 'make' inside an examples subdirectory." @echo -test_c: all_nomsg - @(cd test_c && $(MAKE)) -test_c_debug: all_nomsg - @(cd test_c && $(MAKE) test_debug) -test_sc: all_nomsg - @(cd test_sc && $(MAKE)) -test_sc_debug: all_nomsg - @(cd test_sc && $(MAKE) test_debug) +smoke-test: all_nomsg + test_regress/t/t_a_first_cc.pl + test_regress/t/t_a_first_sc.pl + test_regress: all_nomsg @(cd test_regress && $(MAKE)) +examples: all_nomsg + for p in examples/* ; do \ + $(MAKE) -C $$p ; \ + done + info: $(INFOS) # Use --no-split to avoid creating filenames > 14 chars. @@ -278,9 +284,7 @@ VL_INST_INC_SRCDIR_FILES = \ include/vltstd/*.[chv]* \ VL_INST_DATA_SRCDIR_FILES = \ - test_v/*.[chv]* \ - test_c/*.[chv]* test_c/Makefile test_c/Makefile_obj \ - test_sc/*.[chv]* test_sc/Makefile test_sc/Makefile_obj \ + examples/*/*.[chv]* examples/*/Makefile* \ installbin: $(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(bindir) @@ -311,12 +315,13 @@ installdata: ; for p in $(VL_INST_INC_SRCDIR_FILES) ; do \ $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/$$p; \ done - $(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples/test_c - $(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples/test_sc - $(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples/test_v + $(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples/hello_world_c + $(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples/hello_world_sc + $(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples/tracing_c + $(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples/tracing_sc cd $(srcdir) \ ; for p in $(VL_INST_DATA_SRCDIR_FILES) ; do \ - $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/examples/$$p; \ + $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/$$p; \ done $(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgconfigdir) $(INSTALL_DATA) verilator.pc $(DESTDIR)$(pkgconfigdir) @@ -328,15 +333,15 @@ uninstall: -cd $(DESTDIR)$(mandir)/man1 && rm -f $(VL_INST_MAN_FILES) -cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_INC_BLDDIR_FILES) -cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_INC_SRCDIR_FILES) - -cd $(DESTDIR)$(pkgdatadir)/examples && rm -f $(VL_INST_DATA_SRCDIR_FILES) + -cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_DATA_SRCDIR_FILES) -rm $(DESTDIR)$(pkgconfigdir)/verilator.pc -rmdir $(DESTDIR)$(pkgdatadir)/bin -rmdir $(DESTDIR)$(pkgdatadir)/include/vltstd -rmdir $(DESTDIR)$(pkgdatadir)/include - -rmdir $(DESTDIR)$(pkgdatadir)/examples/test_c - -rmdir $(DESTDIR)$(pkgdatadir)/examples/test_sc - -rmdir $(DESTDIR)$(pkgdatadir)/examples/test_sp - -rmdir $(DESTDIR)$(pkgdatadir)/examples/test_v + -rmdir $(DESTDIR)$(pkgdatadir)/examples/hello_world_c + -rmdir $(DESTDIR)$(pkgdatadir)/examples/hello_world_sc + -rmdir $(DESTDIR)$(pkgdatadir)/examples/tracing_c + -rmdir $(DESTDIR)$(pkgdatadir)/examples/tracing_sc -rmdir $(DESTDIR)$(pkgdatadir)/examples -rmdir $(DESTDIR)$(pkgdatadir) -rmdir $(DESTDIR)$(pkgconfigdir) @@ -451,7 +456,7 @@ endif maintainer-clean:: @echo "This command is intended for maintainers to use;" @echo "rebuilding the deleted files requires makeinfo." - rm -f *.info* $(INFOS) configure + rm -f *.info* *.1 $(INFOS) configure clean mostlyclean distclean maintainer-clean maintainer-copy:: for dir in $(SUBDIRS); do \ @@ -465,7 +470,8 @@ clean mostlyclean distclean maintainer-clean:: rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas rm -f *.tex - rm -rf test_verilated/obj_dir + rm -rf test_*/obj_dir + rm -rf examples/*/obj_dir examples/*/logs distclean maintainer-clean:: rm -f Makefile config.status config.cache config.log TAGS diff --git a/README.pod b/README.pod index 519d45750..2f2f15636 100644 --- a/README.pod +++ b/README.pod @@ -169,6 +169,9 @@ have the verilator binary directory in your PATH (this should already be true if using the default configure), and make sure VERILATOR_ROOT is not set. +You may now wish to consult the examples directory. Type C inside any +example directory to run the example. + =back =head1 USAGE DOCUMENTATION @@ -190,9 +193,10 @@ The directories in the kit after de-taring are as follows: include/verilated.v => Stub defines for linting include/verilated.mk => Common makefile src/ => Translator source code - test_v => Example Verilog code for other test dirs - test_c => Example Verilog->C++ conversion - test_sc => Example Verilog->SystemC conversion + examples/hello_world_c => Example simple Verilog->C++ conversion + examples/hello_world_sc => Example simple Verilog->SystemC conversion + examples/tracing_c => Example Verilog->C++ with tracing + examples/tracing_sc => Example Verilog->SystemC with tracing test_regress => Internal tests =head1 LIMITATIONS diff --git a/bin/verilator b/bin/verilator index 7b929bd99..7552a7b53 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1369,7 +1369,7 @@ We'll compile this example into C++. cat <sim_main.cpp #include "Vour.h" #include "verilated.h" - int main(int argc, char **argv, char **env) { + int main(int argc, char** argv, char** env) { Verilated::commandArgs(argc, argv); Vour* top = new Vour; while (!Verilated::gotFinish()) { top->eval(); } @@ -1982,7 +1982,7 @@ accesses the above signal "readme" would be: printf("Value of v: %d\n", v.value.integer); // Prints "readme" } - int main(int argc, char **argv, char **env) { + int main(int argc, char** argv, char** env) { Verilated::commandArgs(argc, argv); Vour* top = new Vour; Verilated::internalsDump(); // See scopes to help debug @@ -3680,7 +3680,7 @@ trace file if you want all data to land in the same output file. #include "verilated_vcd_c.h" ... - int main(int argc, char **argv, char **env) { + int main(int argc, char** argv, char** env) { ... Verilated::traceEverOn(true); VerilatedVcdC* tfp = new VerilatedVcdC; @@ -3694,6 +3694,8 @@ trace file if you want all data to land in the same output file. tfp->close(); } +Also see the examples/tracing_cc directory in the distribution. + =item How do I generate waveforms (traces) in SystemC? Add the --trace switch to Verilator, and in your top level C sc_main code, @@ -3716,7 +3718,7 @@ trace file if you want all data to land in the same output file. #include "verilated_vcd_sc.h" ... - int main(int argc, char **argv, char **env) { + int main(int argc, char** argv, char** env) { ... Verilated::traceEverOn(true); VerilatedVcdSc* tfp = new VerilatedVcdSc; @@ -3728,11 +3730,13 @@ trace file if you want all data to land in the same output file. tfp->close(); } +Also see the examples/tracing_cc directory in the distribution. + =item How do I view waveforms (traces)? Verilator makes standard VCD (Value Change Dump) files. They are viewable -with the public domain Dinotrace or GtkWave programs, or any of the many -commercial offerings. +with the public domain GtkWave (recommended) or Dinotrace (legacy) +programs, or any of the many commercial offerings. =item How do I reduce the size of large waveform (trace) files? diff --git a/test_c/.gitignore b/examples/hello_world_c/.gitignore similarity index 79% rename from test_c/.gitignore rename to examples/hello_world_c/.gitignore index 2f695bf80..f68b202e1 100644 --- a/test_c/.gitignore +++ b/examples/hello_world_c/.gitignore @@ -3,4 +3,4 @@ *.csrc *.vcd obj_* -project +logs diff --git a/examples/hello_world_c/Makefile b/examples/hello_world_c/Makefile new file mode 100644 index 000000000..10c79f4f3 --- /dev/null +++ b/examples/hello_world_c/Makefile @@ -0,0 +1,51 @@ +###################################################################### +# +# DESCRIPTION: Verilator Example: Small Makefile +# +# This calls the object directory makefile. That allows the objects to +# be placed in the "current directory" which simplifies the Makefile. +# +# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# +###################################################################### +# Check for sanity to avoid later confusion + +ifneq ($(words $(CURDIR)),1) + $(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)') +endif + +###################################################################### + +# This is intended to be a minimal example. Before copying this to start a +# real project, it is better to start with a more complete example, +# e.g. examples/tracing_c. + +# If $VERILATOR_ROOT isn't in the enviornment, we assume it is part of a +# package inatall, and verilator is in your path. Otherwise find the +# binary relative to $VERILATOR_ROOT (such as when inside the git sources). +ifeq ($(VERILATOR_ROOT),) +VERILATOR = verilator +else +VERILATOR = $(VERILATOR_ROOT)/bin/verilator +endif + +default: + @echo "-- Verilator hello-world simple example" + @echo "-- VERILATE ----------------" + $(VERILATOR) -cc --exe top.v sim_main.cpp + @echo "-- COMPILE -----------------" + $(MAKE) -j 4 -C obj_dir -f Vtop.mk + @echo "-- RUN ---------------------" + obj_dir/Vtop + @echo "-- DONE --------------------" + @echo "Note: Once this example is understood, see examples/tracing_c." + @echo "Note: Also see the EXAMPLE section in the verilator manpage/document." + +###################################################################### + +maintainer-copy:: +clean mostlyclean distclean maintainer-clean:: + -rm -rf obj_dir *.log *.dmp *.vpd core diff --git a/examples/hello_world_c/sim_main.cpp b/examples/hello_world_c/sim_main.cpp new file mode 100644 index 000000000..821553c33 --- /dev/null +++ b/examples/hello_world_c/sim_main.cpp @@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog example module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. +//====================================================================== + +// Include common routines +#include + +// Include model header, generated from Verilating "top.v" +#include "Vtop.h" + +int main(int argc, char** argv, char** env) { + // See a similar example walkthrough in the verilator manpage. + + // This is intended to be a minimal example. Before copying this to start a + // real project, it is better to start with a more complete example, + // e.g. examples/c_tracing. + + // Prevent unused variable warnings + if (0 && argc && argv && env) {} + + // Construct the Verilated model, from Vtop.h generated from Verilating "top.v" + Vtop* top = new Vtop; + + // Simulate until $finish + while (!Verilated::gotFinish()) { + + // Evaluate model + top->eval(); + } + + // Final model cleanup + top->final(); + + // Destroy model + delete top; + + // Fin + exit(0); +} diff --git a/examples/hello_world_c/top.v b/examples/hello_world_c/top.v new file mode 100644 index 000000000..b1116025d --- /dev/null +++ b/examples/hello_world_c/top.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog example module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +// See also the EXAMPLE section in the verilator manpage/document. +module top; + initial begin + $display("Hello World!"); + $finish; + end +endmodule diff --git a/test_sc/.gitignore b/examples/hello_world_sc/.gitignore similarity index 72% rename from test_sc/.gitignore rename to examples/hello_world_sc/.gitignore index b491e81b1..f68b202e1 100644 --- a/test_sc/.gitignore +++ b/examples/hello_world_sc/.gitignore @@ -1,8 +1,6 @@ -*.old *.dmp *.log *.csrc *.vcd obj_* logs -project diff --git a/examples/hello_world_sc/Makefile b/examples/hello_world_sc/Makefile new file mode 100644 index 000000000..6b725bec1 --- /dev/null +++ b/examples/hello_world_sc/Makefile @@ -0,0 +1,66 @@ +###################################################################### +# +# DESCRIPTION: Verilator Example: Small Makefile +# +# This calls the object directory makefile. That allows the objects to +# be placed in the "current directory" which simplifies the Makefile. +# +# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# +###################################################################### +# Check for sanity to avoid later confusion + +ifneq ($(words $(CURDIR)),1) + $(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)') +endif + +###################################################################### + +# This is intended to be a minimal example. Before copying this to start a +# real project, it is better to start with a more complete example, +# e.g. examples/tracing_sc. + +# If $VERILATOR_ROOT isn't in the enviornment, we assume it is part of a +# package inatall, and verilator is in your path. Otherwise find the +# binary relative to $VERILATOR_ROOT (such as when inside the git sources). +ifeq ($(VERILATOR_ROOT),) +VERILATOR = verilator +else +VERILATOR = $(VERILATOR_ROOT)/bin/verilator +endif + +# Check if SC exists via a verilator call (empty if not) +SYSTEMC_EXISTS := $(shell $(VERILATOR) --getenv SYSTEMC_INCLUDE) + +ifneq ($(SYSTEMC_EXISTS),) +default: run +else +default: nosc +endif + +run: + @echo "-- Verilator hello-world simple example" + @echo "-- VERILATE ----------------" + $(VERILATOR) -sc --exe top.v sc_main.cpp + @echo "-- COMPILE -----------------" + $(MAKE) -j 4 -C obj_dir -f Vtop.mk + @echo "-- RUN ---------------------" + obj_dir/Vtop + @echo "-- DONE --------------------" + @echo "Note: Once this example is understood, see examples/tracing_sc." + @echo "Note: Also see the EXAMPLE section in the verilator manpage/document." + +###################################################################### + +nosc: + @echo + @echo "%Skip: SYSTEMC_INCLUDE not in environment" + @echo "(If you have SystemC see the README, and rebuild Verilator)" + @echo + +maintainer-copy:: +clean mostlyclean distclean maintainer-clean:: + -rm -rf obj_dir *.log *.dmp *.vpd core diff --git a/examples/hello_world_sc/sc_main.cpp b/examples/hello_world_sc/sc_main.cpp new file mode 100644 index 000000000..f31f54610 --- /dev/null +++ b/examples/hello_world_sc/sc_main.cpp @@ -0,0 +1,51 @@ +// -*- SystemC -*- +// DESCRIPTION: Verilator Example: Top level main for invoking SystemC model +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. +//====================================================================== + +// SystemC global header +#include + +// Include common routines +#include + +// Include model header, generated from Verilating "top.v" +#include "Vtop.h" + +int sc_main(int argc, char* argv[]) { + // See a similar example walkthrough in the verilator manpage. + + // This is intended to be a minimal example. Before copying this to start a + // real project, it is better to start with a more complete example, + // e.g. examples/c_tracing. + + // Prevent unused variable warnings + if (0 && argc && argv) {} + + // Construct the Verilated model, from Vtop.h generated from Verilating "top.v" + Vtop* top = new Vtop("top"); + + // Initialize SC model +#if (SYSTEMC_VERSION>=20070314) + sc_start(1,SC_NS); +#else + sc_start(1); +#endif + + // Simulate until $finish + while (!Verilated::gotFinish()) { +#if (SYSTEMC_VERSION>=20070314) + sc_start(1,SC_NS); +#else + sc_start(1); +#endif + } + + // Final model cleanup + top->final(); + + // Fin + return 0; +} diff --git a/examples/hello_world_sc/top.v b/examples/hello_world_sc/top.v new file mode 100644 index 000000000..b1116025d --- /dev/null +++ b/examples/hello_world_sc/top.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog example module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +// See also the EXAMPLE section in the verilator manpage/document. +module top; + initial begin + $display("Hello World!"); + $finish; + end +endmodule diff --git a/examples/tracing_c/.gitignore b/examples/tracing_c/.gitignore new file mode 100644 index 000000000..f68b202e1 --- /dev/null +++ b/examples/tracing_c/.gitignore @@ -0,0 +1,6 @@ +*.dmp +*.log +*.csrc +*.vcd +obj_* +logs diff --git a/examples/tracing_c/Makefile b/examples/tracing_c/Makefile new file mode 100644 index 000000000..9fada20f3 --- /dev/null +++ b/examples/tracing_c/Makefile @@ -0,0 +1,95 @@ +###################################################################### +# +# DESCRIPTION: Verilator Example: Small Makefile +# +# This calls the object directory makefile. That allows the objects to +# be placed in the "current directory" which simplifies the Makefile. +# +# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# +###################################################################### +# Check for sanity to avoid later confusion + +ifneq ($(words $(CURDIR)),1) + $(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)') +endif + +###################################################################### +# Set up variables + +# If $VERILATOR_ROOT isn't in the enviornment, we assume it is part of a +# package inatall, and verilator is in your path. Otherwise find the +# binary relative to $VERILATOR_ROOT (such as when inside the git sources). +ifeq ($(VERILATOR_ROOT),) +VERILATOR = verilator +VERILATOR_COVERAGE = verilator_coverage +else +VERILATOR = $(VERILATOR_ROOT)/bin/verilator +VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage +endif + +VERILATOR_FLAGS = +# Generate C++ in executable form +VERILATOR_FLAGS += -cc --exe +# Generate makefile dependencies (not shown as complicates the Makefile) +#VERILATOR_FLAGS += -MMD +# Optimize +VERILATOR_FLAGS += -O2 -x-assign 0 +# Warn abount lint issues; may not want this on less solid designs +VERILATOR_FLAGS += -Wall +# Make waveforms +VERILATOR_FLAGS += --trace +# Check SystemVerilog assertions +VERILATOR_FLAGS += --assert +# Generate coverage analysis +VERILATOR_FLAGS += --coverage +# Run Verilator in debug mode +#VERILATOR_FLAGS += --debug +# Add this trace to get a backtrace in gdb +#VERILATOR_FLAGS += --gdbbt + +###################################################################### +default: run + +run: + @echo + @echo "-- Verilator tracing example" + + @echo + @echo "-- VERILATE ----------------" + $(VERILATOR) $(VERILATOR_FLAGS) -f input.vc top.v sim_main.cpp + + @echo + @echo "-- COMPILE -----------------" +# To compile, we can either just do what Verilator asks, +# or call a submakefile where we can override the rules ourselves +# $(MAKE) -j 4 -C obj_dir -f Vtop.mk + $(MAKE) -j 4 -C obj_dir -f ../Makefile_obj + + @echo + @echo "-- RUN ---------------------" + @mkdir -p logs + obj_dir/Vtop | tee logs/sim.log + + @echo + @echo "-- COVERAGE ----------------" + $(VERILATOR_COVERAGE) --annotate logs/annotated logs/coverage.dat + + @echo + @echo "-- DONE --------------------" + @echo "To see waveforms, open vlt_dump.vcd in a waveform viewer" + @echo + + +###################################################################### +# Other targets + +show-config: + $(VERILATOR) -V + +maintainer-copy:: +clean mostlyclean distclean maintainer-clean:: + -rm -rf obj_dir logs *.log *.dmp *.vpd coverage.dat core diff --git a/examples/tracing_c/Makefile_obj b/examples/tracing_c/Makefile_obj new file mode 100644 index 000000000..7fa08631e --- /dev/null +++ b/examples/tracing_c/Makefile_obj @@ -0,0 +1,54 @@ +# -*- Makefile -*- +####################################################################### +# +# DESCRIPTION: Verilator Example: Makefile for inside object directory +# +# This is executed in the object directory, and called by ../Makefile +# +# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# +####################################################################### + +default: Vtop + +# Include the rules made by Verilator +include Vtop.mk + +####################################################################### +# Compile flags + +# Override some default compile flags +CPPFLAGS += -MMD -MP +CPPFLAGS += -DVL_DEBUG=1 +# Turn on some more flags (when configured appropriately) +ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users +CPPFLAGS += -DVL_THREADED=1 +CPPFLAGS += -W -Werror -Wall +endif + +# See the benchmarking section of bin/verilator. +# Support class optimizations. This includes the tracing and symbol table. +# SystemC takes minutes to optimize, thus it is off by default. +OPT_SLOW = +# Fast path optimizations. Most time is spent in these classes. +OPT_FAST = -O2 -fstrict-aliasing +#OPT_FAST = -O +#OPT_FAST = + +####################################################################### +# Linking final exe -- presumes have a sim_main.cpp + +# Special compile rule +sim_main.o: sim_main.cpp $(VM_PREFIX).h + +###################################################################### +###################################################################### +# Automatically understand dependencies + +DEPS := $(wildcard *.d) +ifneq ($(DEPS),) +include $(DEPS) +endif diff --git a/examples/tracing_c/input.vc b/examples/tracing_c/input.vc new file mode 100644 index 000000000..4f2ba1e7c --- /dev/null +++ b/examples/tracing_c/input.vc @@ -0,0 +1,2 @@ +// This file typically lists flags required by a large project, e.g. include directories ++librescan +libext+.v+.sv+.vh+.svh -y . diff --git a/examples/tracing_c/sim_main.cpp b/examples/tracing_c/sim_main.cpp new file mode 100644 index 000000000..004d7ade1 --- /dev/null +++ b/examples/tracing_c/sim_main.cpp @@ -0,0 +1,114 @@ +// DESCRIPTION: Verilator: Verilog example module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. +//====================================================================== + +// Include common routines +#include + +#include // mkdir + +// Include model header, generated from Verilating "top.v" +#include "Vtop.h" + +// If "verilator --trace" is used, include the tracing class +#if VM_TRACE +# include +#endif + +// Current simulation time (64-bit unsigned) +vluint64_t main_time = 0; +// Called by $time in Verilog +double sc_time_stamp () { + return main_time; // Note does conversion to real, to match SystemC +} + +int main(int argc, char** argv, char** env) { + // This is a more complicated example, please also see the simpler examples/hello_world_c. + + // Prevent unused variable warnings + if (0 && argc && argv && env) {} + // Pass arguments so Verilated code can see them, e.g. $value$plusargs + Verilated::commandArgs(argc, argv); + + // Set debug level, 0 is off, 9 is highest presently used + Verilated::debug(0); + + // Randomization reset policy + Verilated::randReset(2); + + // Construct the Verilated model, from Vtop.h generated from Verilating "top.v" + Vtop* top = new Vtop; // Or use a const unique_ptr, or the VL_UNIQUE_PTR wrapper + + // If verilator was invoked with --trace, open trace +#if VM_TRACE + Verilated::traceEverOn(true); // Verilator must compute traced signals + VL_PRINTF("Enabling waves into logs/vlt_dump.vcd...\n"); + VerilatedVcdC* tfp = new VerilatedVcdC; + top->trace(tfp, 99); // Trace 99 levels of hierarchy + mkdir("logs", 0777); + tfp->open("logs/vlt_dump.vcd"); // Open the dump file +#endif + + // Set some inputs + top->reset_l = !0; + top->fastclk = 0; + top->clk = 0; + top->in_small = 1; + top->in_quad = 0x1234; + top->in_wide[0] = 0x1; + top->in_wide[1] = 0x22222222; + top->in_wide[2] = 0x33333333; + + // Simulate until $finish + while (!Verilated::gotFinish()) { + main_time++; // Time passes... + + // Toggle clocks and such + top->fastclk = !top->fastclk; + if ((main_time % 10) == 3) { + top->clk = 1; + } + if ((main_time % 10) == 8) { + top->clk = 0; + } + if (main_time > 1 && main_time < 10) { + top->reset_l = !1; // Assert reset + } else { + top->reset_l = !0; // Deassert reset + } + + // Assign some other inputs + top->in_quad += 0x12; + + // Evaluate model + top->eval(); + + // Read outputs + VL_PRINTF ("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x" + " -> oquad=%" VL_PRI64"x owide=%x_%08x_%08x\n", + main_time, top->clk, top->reset_l, top->in_quad, + top->out_quad, top->out_wide[2], top->out_wide[1], top->out_wide[0]); + } + + // Final model cleanup + top->final(); + + // Close trace if opened +#if VM_TRACE + if (tfp) { tfp->close(); } +#endif + + // Coverage analysis (since test passed) +#if VM_COVERAGE + mkdir("logs", 0777); + VerilatedCov::write("logs/coverage.dat"); +#endif + + // Destroy model + delete top; top = NULL; + + // Fin + exit(0); +} diff --git a/examples/tracing_c/sub.v b/examples/tracing_c/sub.v new file mode 100644 index 000000000..6f6fde7b6 --- /dev/null +++ b/examples/tracing_c/sub.v @@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. +// ====================================================================== + +module sub + ( + input clk, + input fastclk, + input reset_l + ); + + // Example counter/flop + reg [31:0] count_f; + always_ff @ (posedge fastclk) begin + if (!reset_l) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + count_f <= 32'h0; + // End of automatics + end + else begin + count_f <= count_f + 1; + end + end + + // Another example flop + reg [31:0] count_c; + always_ff @ (posedge clk) begin + if (!reset_l) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + count_c <= 32'h0; + // End of automatics + end + else begin + count_c <= count_c + 1; + if (count_c >= 3) begin + $display("[%0t] fastclk is %0d times faster than clk\n", + $time, count_f/count_c); + // This write is a magic value the Makefile uses to make sure the + // test completes successfully. + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + // An example assertion + always_ff @ (posedge clk) begin + AssertionExample: assert (!reset_l || count_c<100); + end + + // And example coverage analysis + cover property (@(posedge clk) count_c==3); + +endmodule diff --git a/examples/tracing_c/top.v b/examples/tracing_c/top.v new file mode 100644 index 000000000..e605270e2 --- /dev/null +++ b/examples/tracing_c/top.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog example module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. +// ====================================================================== + +// This is intended to be a complex example of several features, please also +// see the simpler examples/hello_world_c. + +module top + ( + // Declare some signals so we can see how I/O works + input clk, + input fastclk, + input reset_l, + + output [1:0] out_small, + output [39:0] out_quad, + output [69:0] out_wide, + input [1:0] in_small, + input [39:0] in_quad, + input [69:0] in_wide + ); + + // Connect up the outputs, using some trivial logic + wire [1:0] out_small = ~reset_l ? '0 : (in_small + 2'b1); + wire [39:0] out_quad = ~reset_l ? '0 : (in_quad + 40'b1); + wire [69:0] out_wide = ~reset_l ? '0 : (in_wide + 70'b1); + + // And an example sub module. The submodule will print stuff. + sub sub (/*AUTOINST*/ + // Inputs + .clk (clk), + .fastclk (fastclk), + .reset_l (reset_l)); + + // Print some stuff as an example + initial begin + $display("[%0t] Model running...\n", $time); + end + +endmodule diff --git a/examples/tracing_sc/.gitignore b/examples/tracing_sc/.gitignore new file mode 100644 index 000000000..f68b202e1 --- /dev/null +++ b/examples/tracing_sc/.gitignore @@ -0,0 +1,6 @@ +*.dmp +*.log +*.csrc +*.vcd +obj_* +logs diff --git a/examples/tracing_sc/Makefile b/examples/tracing_sc/Makefile new file mode 100644 index 000000000..3c9c68f97 --- /dev/null +++ b/examples/tracing_sc/Makefile @@ -0,0 +1,108 @@ +###################################################################### +# +# DESCRIPTION: Verilator Example: Small Makefile +# +# This calls the object directory makefile. That allows the objects to +# be placed in the "current directory" which simplifies the Makefile. +# +# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# +###################################################################### +# Check for sanity to avoid later confusion + +ifneq ($(words $(CURDIR)),1) + $(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)') +endif + +###################################################################### +# Set up variables + +# If $VERILATOR_ROOT isn't in the enviornment, we assume it is part of a +# package inatall, and verilator is in your path. Otherwise find the +# binary relative to $VERILATOR_ROOT (such as when inside the git sources). +ifeq ($(VERILATOR_ROOT),) +VERILATOR = verilator +VERILATOR_COVERAGE = verilator_coverage +else +VERILATOR = $(VERILATOR_ROOT)/bin/verilator +VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage +endif + +VERILATOR_FLAGS = +# Generate SystemC in executable form +VERILATOR_FLAGS += -sc --exe +# Generate makefile dependencies (not shown as complicates the Makefile) +#VERILATOR_FLAGS += -MMD +# Optimize +VERILATOR_FLAGS += -O2 -x-assign 0 +# Warn abount lint issues; may not want this on less solid designs +VERILATOR_FLAGS += -Wall +# Make waveforms +VERILATOR_FLAGS += --trace +# Check SystemVerilog assertions +VERILATOR_FLAGS += --assert +# Generate coverage analysis +VERILATOR_FLAGS += --coverage +# Run Verilator in debug mode +#VERILATOR_FLAGS += --debug +# Add this trace to get a backtrace in gdb +#VERILATOR_FLAGS += --gdbbt + +# Check if SC exists via a verilator call (empty if not) +SYSTEMC_EXISTS := $(shell $(VERILATOR) --getenv SYSTEMC_INCLUDE) + +###################################################################### + +ifneq ($(SYSTEMC_EXISTS),) +default: run +else +default: nosc +endif + +run: + @echo + @echo "-- Verilator tracing example" + + @echo + @echo "-- VERILATE ----------------" + $(VERILATOR) $(VERILATOR_FLAGS) -f input.vc top.v sc_main.cpp + + @echo + @echo "-- COMPILE ----------------=" +# To compile, we can either just do what Verilator asks, +# or call a submakefile where we can override the rules ourselves +# $(MAKE) -j 4 -C obj_dir -f Vtop.mk + $(MAKE) -j 4 -C obj_dir -f ../Makefile_obj + + @echo + @echo "-- RUN ---------------------" + @mkdir -p logs + obj_dir/Vtop | tee logs/sim.log + + @echo + @echo "-- COVERAGE ----------------" + $(VERILATOR_COVERAGE) --annotate logs/annotated logs/coverage.dat + + @echo + @echo "-- DONE --------------------" + @echo "To see waveforms, open vlt_dump.vcd in a waveform viewer" + @echo + +###################################################################### +# Other targets + +nosc: + @echo + @echo "%Skip: SYSTEMC_INCLUDE not in environment" + @echo "(If you have SystemC see the README, and rebuild Verilator)" + @echo + +show-config: + $(VERILATOR) -V + +maintainer-copy:: +clean mostlyclean distclean maintainer-clean:: + -rm -rf obj_dir logs *.log *.dmp *.vpd coverage.dat core diff --git a/examples/tracing_sc/Makefile_obj b/examples/tracing_sc/Makefile_obj new file mode 100644 index 000000000..cd984f7b9 --- /dev/null +++ b/examples/tracing_sc/Makefile_obj @@ -0,0 +1,62 @@ +# -*- Makefile -*- +####################################################################### +# +# DESCRIPTION: Verilator Example: Makefile for inside object directory +# +# This is executed in the object directory, and called by ../Makefile +# +# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# +####################################################################### + +default: Vtop + +# Include the rules made by Verilator +include Vtop.mk + +####################################################################### +# Compile flags + +# Override some default compile flags +CPPFLAGS += -MMD -MP +CPPFLAGS += -DVL_DEBUG=1 +# SystemC isn't too clean +CPPFLAGS += -Wno-deprecated +# Turn on some more flags (when configured appropriately) +ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users +CPPFLAGS += -DVL_THREADED=1 +CPPFLAGS += -W -Werror -Wall +endif + +# If you build your own rules from scratch, note you need to include +# SystemC as follows (Vtop.mk file includes verilated.mk with these +# already). +# CPPFLAGS += $(SYSTEMC_CXX_FLAGS) -I$(SYSTEMC_INCLUDE) +# LDFLAGS += $(SYSTEMC_CXX_FLAGS) -L$(SYSTEMC_LIBDIR) + +# See the benchmarking section of bin/verilator. +# Support class optimizations. This includes the tracing and symbol table. +# SystemC takes minutes to optimize, thus it is off by default. +OPT_SLOW = +# Fast path optimizations. Most time is spent in these classes. +OPT_FAST = -O2 -fstrict-aliasing +#OPT_FAST = -O +#OPT_FAST = + +####################################################################### +# Linking final exe -- presumes have a sim_main.cpp + +# Special compile rule +sim_main.o: sim_main.cpp $(VM_PREFIX).h + +###################################################################### +###################################################################### +# Automatically understand dependencies + +DEPS := $(wildcard *.d) +ifneq ($(DEPS),) +include $(DEPS) +endif diff --git a/examples/tracing_sc/input.vc b/examples/tracing_sc/input.vc new file mode 100644 index 000000000..4f2ba1e7c --- /dev/null +++ b/examples/tracing_sc/input.vc @@ -0,0 +1,2 @@ +// This file typically lists flags required by a large project, e.g. include directories ++librescan +libext+.v+.sv+.vh+.svh -y . diff --git a/test_sc/sc_main.cpp b/examples/tracing_sc/sc_main.cpp similarity index 53% rename from test_sc/sc_main.cpp rename to examples/tracing_sc/sc_main.cpp index 41b9475b7..c78cc79d2 100644 --- a/test_sc/sc_main.cpp +++ b/examples/tracing_sc/sc_main.cpp @@ -1,41 +1,49 @@ // -*- SystemC -*- // DESCRIPTION: Verilator Example: Top level main for invoking SystemC model // -// Copyright 2003-2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -//==================================================================== +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. +//====================================================================== -#include -#include -#include -#include +// SystemC global header +#include -#include "systemc.h" // SystemC global header -#include "verilated_vcd_sc.h" // Tracing +// Include common routines +#include +#if VM_TRACE +#include +#endif -#include "Vtop.h" // Top level header, generated from verilog +#include // mkdir + +// Include model header, generated from Verilating "top.v" +#include "Vtop.h" int sc_main(int argc, char* argv[]) { + // This is a more complicated example, please also see the simpler examples/hello_world_c. + + // Prevent unused variable warnings + if (0 && argc && argv) {} + // Pass arguments so Verilated code can see them, e.g. $value$plusargs Verilated::commandArgs(argc, argv); + + // Set debug level, 0 is off, 9 is highest presently used + Verilated::debug(0); + + // Randomization reset policy Verilated::randReset(2); - Verilated::debug(0); // We compiled with it on for testing, turn it back off // General logfile ios::sync_with_stdio(); - // Defaults + // Defaults time #if (SYSTEMC_VERSION>20011000) #else sc_time dut(1.0, sc_ns); sc_set_default_time_unit(dut); #endif - //========== - // Define the Clocks - - cout << "Defining Clocks\n"; + // Define clocks #if (SYSTEMC_VERSION>=20070314) sc_clock clk ("clk", 10,SC_NS, 0.5, 3,SC_NS, true); sc_clock fastclk ("fastclk", 2,SC_NS, 0.5, 2,SC_NS, true); @@ -44,9 +52,8 @@ int sc_main(int argc, char* argv[]) { sc_clock fastclk ("fastclk", 2, 0.5, 2, true); #endif - cout << "Defining Interconnect\n"; + // Define interconnect sc_signal reset_l; - sc_signal passed; sc_signal in_small; sc_signal in_quad; sc_signal > in_wide; @@ -54,23 +61,18 @@ int sc_main(int argc, char* argv[]) { sc_signal out_quad; sc_signal > out_wide; - //========== - // Part under test - + // Construct the Verilated model, from inside Vtop.h Vtop* top = new Vtop("top"); - top->clk (clk); - top->fastclk (fastclk); - top->reset_l (reset_l); - top->passed (passed); - top->in_small (in_small); - top->in_quad (in_quad); - top->in_wide (in_wide); - top->out_small (out_small); - top->out_quad (out_quad); - top->out_wide (out_wide); - - //========== - // Waves + // Attach signals to the model + top->clk (clk); + top->fastclk (fastclk); + top->reset_l (reset_l); + top->in_small (in_small); + top->in_quad (in_quad); + top->in_wide (in_wide); + top->out_small (out_small); + top->out_quad (out_quad); + top->out_wide (out_wide); #if VM_TRACE // Before any evaluation, need to know to calculate those signals only used for tracing @@ -79,41 +81,35 @@ int sc_main(int argc, char* argv[]) { // You must do one evaluation before enabling waves, in order to allow // SystemC to interconnect everything for testing. - cout <<("Test initialization...\n"); - reset_l = 1; #if (SYSTEMC_VERSION>=20070314) sc_start(1,SC_NS); #else sc_start(1); #endif - //========== - // Waves - + // Turn on waves #if VM_TRACE - cout << "Enabling waves...\n"; + cout << "Enabling waves into logs/vlt_dump.vcd...\n"; VerilatedVcdSc* tfp = new VerilatedVcdSc; top->trace (tfp, 99); - tfp->open ("vlt_dump.vcd"); + mkdir("logs", 0777); + tfp->open ("logs/vlt_dump.vcd"); #endif - //========== - // Start of Test - - cout <<("Test beginning...\n"); - - reset_l = 1; - while (VL_TIME_Q() < 60 && !Verilated::gotFinish()) { + // Simulate until $finish + while (!Verilated::gotFinish()) { #if VM_TRACE // Flush the wave files each cycle so we can immediately see the output // Don't do this in "real" programs, do it in an abort() handler instead if (tfp) tfp->flush(); -#endif - if (VL_TIME_Q() > 10) { - reset_l = 1; // Deassert reset + // Apply inputs + if (VL_TIME_Q() > 1 && VL_TIME_Q() < 10) { + reset_l = !1; // Assert reset } else if (VL_TIME_Q() > 1) { - reset_l = 0; // Assert reset + reset_l = !0; // Deassert reset } +#endif + // Simulate 1ns #if (SYSTEMC_VERSION>=20070314) sc_start(1,SC_NS); #else @@ -121,30 +117,20 @@ int sc_main(int argc, char* argv[]) { #endif } - top->final(); - - //========== // Close Waves #if VM_TRACE if (tfp) tfp->close(); #endif - if (!passed) { - VL_PRINTF ("A Test failed!!\n"); - abort(); - } + // Final model cleanup + top->final(); - //========== // Coverage analysis (since test passed) - mkdir("logs", 0777); #if VM_COVERAGE + mkdir("logs", 0777); VerilatedCov::write("logs/coverage.dat"); -#endif // VM_COVERAGE +#endif - //========== - // Close LogFiles - - cout << "*-* All Finished *-*\n"; // Magic if using perl's Log::Detect - - return(0); + // Fin + return 0; } diff --git a/examples/tracing_sc/sub.v b/examples/tracing_sc/sub.v new file mode 100644 index 000000000..6f6fde7b6 --- /dev/null +++ b/examples/tracing_sc/sub.v @@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. +// ====================================================================== + +module sub + ( + input clk, + input fastclk, + input reset_l + ); + + // Example counter/flop + reg [31:0] count_f; + always_ff @ (posedge fastclk) begin + if (!reset_l) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + count_f <= 32'h0; + // End of automatics + end + else begin + count_f <= count_f + 1; + end + end + + // Another example flop + reg [31:0] count_c; + always_ff @ (posedge clk) begin + if (!reset_l) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + count_c <= 32'h0; + // End of automatics + end + else begin + count_c <= count_c + 1; + if (count_c >= 3) begin + $display("[%0t] fastclk is %0d times faster than clk\n", + $time, count_f/count_c); + // This write is a magic value the Makefile uses to make sure the + // test completes successfully. + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + // An example assertion + always_ff @ (posedge clk) begin + AssertionExample: assert (!reset_l || count_c<100); + end + + // And example coverage analysis + cover property (@(posedge clk) count_c==3); + +endmodule diff --git a/examples/tracing_sc/top.v b/examples/tracing_sc/top.v new file mode 100644 index 000000000..e605270e2 --- /dev/null +++ b/examples/tracing_sc/top.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog example module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. +// ====================================================================== + +// This is intended to be a complex example of several features, please also +// see the simpler examples/hello_world_c. + +module top + ( + // Declare some signals so we can see how I/O works + input clk, + input fastclk, + input reset_l, + + output [1:0] out_small, + output [39:0] out_quad, + output [69:0] out_wide, + input [1:0] in_small, + input [39:0] in_quad, + input [69:0] in_wide + ); + + // Connect up the outputs, using some trivial logic + wire [1:0] out_small = ~reset_l ? '0 : (in_small + 2'b1); + wire [39:0] out_quad = ~reset_l ? '0 : (in_quad + 40'b1); + wire [69:0] out_wide = ~reset_l ? '0 : (in_wide + 70'b1); + + // And an example sub module. The submodule will print stuff. + sub sub (/*AUTOINST*/ + // Inputs + .clk (clk), + .fastclk (fastclk), + .reset_l (reset_l)); + + // Print some stuff as an example + initial begin + $display("[%0t] Model running...\n", $time); + end + +endmodule diff --git a/test_c/Makefile b/test_c/Makefile deleted file mode 100644 index 282b01a1d..000000000 --- a/test_c/Makefile +++ /dev/null @@ -1,66 +0,0 @@ -#***************************************************************************** -# -# DESCRIPTION: Verilator Example: Makefile for inside source directory -# -# This calls the object directory makefile. That allows the objects to -# be placed in the "current directory" which simplifies the Makefile. -# -# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# -#****************************************************************************/ - -default: show_config test_default - -# This must point to the root of the VERILATOR kit -VERILATOR_ROOT := $(shell pwd)/.. -export VERILATOR_ROOT - -# Pick up PERL and other variable settings -include $(VERILATOR_ROOT)/include/verilated.mk - -DEBUG_QUIET = --debug --debugi 0 --gdbbt --no-dump-tree -DEBUG_ON = --debug --trace-dups --gdbbt -#DEBUG = $(DEBUG_ON) -VALGRIND_ON = $(DEBUG_ON) --gdb "valgrind -v --leak-check=yes" - -###################################################################### -test_default: prep compile run -test_debug: prep_dbg compile run -test_valgrind: prep_vg compile run - -VERILATOR_FLAGS = --cc -f $(VERILATOR_ROOT)/test_v/input.vc top.v -VERILATOR_FLAGS += --trace - -#show_config: Is the very first time we've executed Verilator after building -#so we make sure to run with --gdbbt, so if it dumps we'll get a trace. -show_config: - $(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_QUIET) -V - -#prep: Is the very first time we're running a Verilation -#so we make sure to run with --gdbbt, so if it dumps we'll get a trace. -prep: - $(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_QUIET) $(VERILATOR_FLAGS) -prep_dbg: - $(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS) -prep_vg: - $(PERL) $(VERILATOR_ROOT)/bin/verilator $(VALGRIND_ON) $(VERILATOR_FLAGS) - -compile: - cd obj_dir ; $(MAKE) -j 3 -f ../Makefile_obj - -run: - obj_dir/simx - -###################################################################### - -obj_dir: - mkdir $@ - -###################################################################### - -maintainer-copy:: -clean mostlyclean distclean maintainer-clean:: - -rm -rf obj_dir *.log *.dmp *.vpd core diff --git a/test_c/Makefile_obj b/test_c/Makefile_obj deleted file mode 100644 index 555a5fd14..000000000 --- a/test_c/Makefile_obj +++ /dev/null @@ -1,33 +0,0 @@ -# -*- Makefile -*- -#***************************************************************************** -# -# DESCRIPTION: Verilator Example: Makefile for inside object directory -# -# This is executed in the object directory, and called by ../Makefile -# -# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# -#***************************************************************************** - -default: simx -include Vtop.mk - -####################################################################### -# Compile flags - -CPPFLAGS += -DVL_DEBUG=1 -ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users -CPPFLAGS += -DVL_THREADED=1 -CPPFLAGS += -W -Werror -Wall -endif - -####################################################################### -# Linking final exe -- presumes have a sim_main.cpp - -simx: sim_main.o $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a - $(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt - -sim_main.o: sim_main.cpp $(VM_PREFIX).h diff --git a/test_c/sim_main.cpp b/test_c/sim_main.cpp deleted file mode 100644 index b6fd952b2..000000000 --- a/test_c/sim_main.cpp +++ /dev/null @@ -1,84 +0,0 @@ -// DESCRIPTION: Verilator Example: Top level main for invoking model -// -// Copyright 2003-2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. - -#include // Defines common routines -#include "Vtop.h" // From Verilating "top.v" -#if VM_TRACE -# include // Trace file format header -#endif - -Vtop *top; // Instantiation of module - -vluint64_t main_time = 0; // Current simulation time (64-bit unsigned) - -double sc_time_stamp () { // Called by $time in Verilog - return main_time; // Note does conversion to real, to match SystemC -} - -int main(int argc, char **argv, char **env) { - if (0 && argc && argv && env) {} // Prevent unused variable warnings - top = new Vtop; // Create instance of module - - Verilated::commandArgs(argc, argv); - Verilated::debug(0); - -#if VM_TRACE // If verilator was invoked with --trace - Verilated::traceEverOn(true); // Verilator must compute traced signals - VL_PRINTF("Enabling waves...\n"); - VerilatedVcdC* tfp = new VerilatedVcdC; - top->trace (tfp, 99); // Trace 99 levels of hierarchy - tfp->open ("vlt_dump.vcd"); // Open the dump file -#endif - - top->reset_l = 1; // Set some inputs - top->fastclk = 0; - top->clk = 0; - top->passed = 0; - - while (main_time < 60 && !top->passed && !Verilated::gotFinish()) { - - if ((main_time % 10) == 3) { // Toggle clock - top->clk = 1; - } - if ((main_time % 10) == 8) { - top->clk = 0; - } - if (main_time > 10) { - top->reset_l = 1; // Deassert reset - } else if (main_time > 1) { - top->reset_l = 0; // Assert reset - } - - top->eval(); // Evaluate model -#if VM_TRACE - if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp -#endif - - // Read outputs - VL_PRINTF ("[%" VL_PRI64 "d] %x %x %x %x %x_%08x_%08x\n", - main_time, top->clk, top->reset_l, top->passed, - top->out_small, top->out_wide[2], top->out_wide[1], top->out_wide[0]); - - top->fastclk = !top->fastclk; - main_time++; // Time passes... - } - - top->final(); - -#if VM_TRACE - if (tfp) tfp->close(); -#endif - - if (!top->passed) { - VL_PRINTF ("A Test failed\n"); - abort(); - } else { - VL_PRINTF ("All Tests passed\n"); - } - - exit(0L); -} diff --git a/test_regress/t/t_a_first_cc.pl b/test_regress/t/t_a_first_cc.pl new file mode 100755 index 000000000..db757b56d --- /dev/null +++ b/test_regress/t/t_a_first_cc.pl @@ -0,0 +1,27 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +# show-config: This test runs the very first time we've executed Verilator +# after building so we make sure to run with --gdbbt, so if it dumps we'll +# get a trace. + +$DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"; + +$Self->run(cmd=>["perl", "../bin/verilator", $DEBUG_QUIET, "-V"]); + +compile ( + verilator_flags2 => [$DEBUG_QUIET, "--trace"], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_a_first_cc.v b/test_regress/t/t_a_first_cc.v new file mode 100644 index 000000000..d90fb7797 --- /dev/null +++ b/test_regress/t/t_a_first_cc.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Test loop + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_a_first_sc.pl b/test_regress/t/t_a_first_sc.pl new file mode 100755 index 000000000..164c9122e --- /dev/null +++ b/test_regress/t/t_a_first_sc.pl @@ -0,0 +1,27 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +# This test runs the very first time we've executed Verilator --sc +# after building so we make sure to run with --gdbbt, so if it dumps we'll +# get a trace. + +top_filename("t/t_a_first_cc.v"); + +$DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"; + +compile ( + verilator_flags2 => [$DEBUG_QUIET, "-sc --trace"], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_sc/Makefile b/test_sc/Makefile deleted file mode 100644 index 6a62965bc..000000000 --- a/test_sc/Makefile +++ /dev/null @@ -1,68 +0,0 @@ -#***************************************************************************** -# -# DESCRIPTION: Verilator Example: Makefile for inside source directory -# -# This calls the object directory makefile. That allows the objects to -# be placed in the "current directory" which simplifies the Makefile. -# -# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# -#****************************************************************************/ - -default: test_default - -# This must point to the root of the VERILATOR kit -VERILATOR_ROOT := $(shell pwd)/.. -export VERILATOR_ROOT - -# Pick up PERL and other variable settings -include $(VERILATOR_ROOT)/include/verilated.mk - -DEBUG_ON = --debug -SYSTEMC_TESTING ?= $(SYSTEMC)$(SYSTEMC_INCLUDE) - -###################################################################### -ifneq ($(SYSTEMC_TESTING),) -test_default: precopy prep compile run -test_debug: precopy prep_dbg compile run -else -test_default: nosc -test_debug: nosc -endif - -V_FLAGS = -f $(VERILATOR_ROOT)/test_v/input.vc -VERILATOR_FLAGS = --sc $(V_FLAGS) top.v -VERILATOR_FLAGS += --trace - -precopy: - -prep: - $(PERL) $(VERILATOR_ROOT)/bin/verilator $(VERILATOR_FLAGS) -prep_dbg: - $(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS) - -compile: - cd obj_dir ; $(MAKE) -j 3 -f ../Makefile_obj - -run: - obj_dir/simx - -###################################################################### - -obj_dir: - mkdir $@ - -nosc: - @echo - @echo %Skip: SYSTEMC_INCLUDE not in environment - @echo - -###################################################################### - -maintainer-copy:: -clean mostlyclean distclean maintainer-clean:: - -rm -rf obj_dir *.log *.dmp *.vpd *.vcd core - diff --git a/test_sc/Makefile_obj b/test_sc/Makefile_obj deleted file mode 100644 index 7310f0f62..000000000 --- a/test_sc/Makefile_obj +++ /dev/null @@ -1,34 +0,0 @@ -# -*- Makefile -*- -#***************************************************************************** -# -# DESCRIPTION: Verilator Example: Makefile for inside object directory -# -# This is executed in the object directory, and called by ../Makefile -# -# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# -#***************************************************************************** - -default: simx -include Vtop.mk - -####################################################################### - -CPPFLAGS += -Wno-deprecated -CPPFLAGS += $(SYSTEMC_CXX_FLAGS) - -LDFLAGS += $(SYSTEMC_CXX_FLAGS) - -####################################################################### -# Linking final exe -- presumes have a sim_main.cpp - -SC_LIB = $(SYSTEMC_LIBDIR)/libsystemc.a - -simx: sc_main.o $(VK_GLOBAL_OBJS) \ - $(VM_PREFIX)__ALL.a $(SC_LIB) - $(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(SC_LIBS) $(LIBS) 2>&1 | c++filt - -sc_main.o: sc_main.cpp $(VM_PREFIX).h diff --git a/test_v/input.vc b/test_v/input.vc deleted file mode 100644 index 87fea5f1b..000000000 --- a/test_v/input.vc +++ /dev/null @@ -1,5 +0,0 @@ - -+librescan +libext+.v - -y ../test_v - +incdir+../test_v - +incdir+../include diff --git a/test_v/t.v b/test_v/t.v deleted file mode 100644 index 9fb245983..000000000 --- a/test_v/t.v +++ /dev/null @@ -1,45 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. - -module t (/*AUTOARG*/ - // Outputs - passed, - // Inputs - clk, fastclk, reset_l - ); - - input clk /*verilator sc_clock*/; - input fastclk /*verilator sc_clock*/; - input reset_l; - output passed; - - reg [31:0] count_c; - reg [31:0] count_f; - - always @ (posedge clk) begin - if (!reset_l) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - count_c <= 32'h0; - // End of automatics - end else begin - count_c <= count_c + 1; - end - end - - always @ (posedge fastclk) begin - if (!reset_l) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - count_f <= 32'h0; - passed <= 1'h0; - // End of automatics - end else begin - count_f <= count_f + 1; - if (count_f == 5) passed <= 1'b1; - end - end - -endmodule diff --git a/test_v/top.v b/test_v/top.v deleted file mode 100644 index 373c90c14..000000000 --- a/test_v/top.v +++ /dev/null @@ -1,44 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. - -`timescale 1 ns/ 1ns - -module top (/*AUTOARG*/ - // Outputs - passed, out_small, out_quad, out_wide, - // Inputs - clk, fastclk, reset_l, in_small, in_quad, in_wide - ); - - output passed; - input clk; - input fastclk; - input reset_l; - - output [1:0] out_small; - output [39:0] out_quad; - output [69:0] out_wide; - input [1:0] in_small; - input [39:0] in_quad; - input [69:0] in_wide; - - wire [1:0] out_small = in_small | {2{reset_l}}; - wire [39:0] out_quad = in_quad | {40{reset_l}}; - wire [69:0] out_wide = in_wide | {70{reset_l}}; - - initial begin - $write("Hello World!\n"); - end - - // Example sub module - t t (/*AUTOINST*/ - // Outputs - .passed (passed), - // Inputs - .clk (clk), - .fastclk (fastclk), - .reset_l (reset_l)); - -endmodule