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Test clean-ups, resolve an internal error masked by the checking strategy, and add 'automatic' to remove warnings 

Signed-off-by: Matthew Ballance <matt.ballance@gmail.com>
This commit is contained in:
Matthew Ballance 2026-03-07 00:53:20 +00:00
parent affe776463
commit 464be2c85b
32 changed files with 78 additions and 94 deletions
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20
src/verilog.y
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@ -6947,9 +6947,9 @@ covergroup_declaration<nodep>: // ==IEEE: covergroup_declaration
| yCOVERGROUP yEXTENDS idAny ';'
/*cont*/ coverage_spec_or_optionListE
/*cont*/ yENDGROUP endLabelE
{ BBCOVERIGN($1, "Ignoring unsupported: covergroup inheritance (extends)");
$$ = new AstCovergroup{$<fl>3, *$3, nullptr, nullptr, $5, nullptr};
GRAMMARP->endLabel($<fl>7, $$, $7); }
{ $$ = nullptr;
BBUNSUP($1, "Unsupported: covergroup inheritance (extends) is not implemented");
DEL($5); }
;
cgPortListE<nodep>:
@ -7921,11 +7921,15 @@ class_item<nodep>: // ==IEEE: class_item
| timeunits_declaration { $$ = $1; }
| covergroup_declaration
{
const string cgName = $1->name();
$1->name("__vlAnonCG_" + cgName);
AstVar* const newp = new AstVar{$1->fileline(), VVarType::VAR, cgName,
VFlagChildDType{}, new AstRefDType($1->fileline(), $1->name())};
$$ = addNextNull($1, newp);
if ($1) {
const string cgName = $1->name();
$1->name("__vlAnonCG_" + cgName);
AstVar* const newp = new AstVar{$1->fileline(), VVarType::VAR, cgName,
VFlagChildDType{}, new AstRefDType($1->fileline(), $1->name())};
$$ = addNextNull($1, newp);
} else {
$$ = nullptr;
}
}
// // local_parameter_declaration under parameter_declaration
| parameter_declaration ';' { $$ = $1; }

2
test_regress/t/t_covergroup_auto_bins.py
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@ -1,8 +1,6 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Test automatic bins: bins auto[N]
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.

2
test_regress/t/t_covergroup_auto_bins.v
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@ -1,5 +1,7 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// Test automatic bins: bins auto[N]
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

1
test_regress/t/t_covergroup_auto_sample.py
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@ -9,7 +9,6 @@
import vltest_bootstrap
# Test automatic sampling with --no-timing (default)
test.scenarios('vlt')
test.compile()

1
test_regress/t/t_covergroup_auto_sample.v
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@ -1,4 +1,5 @@
// DESCRIPTION: Verilator: Test automatic sampling with clocking events
// Tests --no-timing (default) mode; see t_covergroup_auto_sample_timing for --timing variant.
// This file ONLY is placed into the Public Domain, for any use, without warranty.
// SPDX-License-Identifier: CC0-1.0

1
test_regress/t/t_covergroup_auto_sample_timing.py
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@ -9,7 +9,6 @@
import vltest_bootstrap
# Test automatic sampling with --timing
test.scenarios('vlt')
# Use the same .v file as the non-timing test

9
test_regress/t/t_covergroup_clocking_internal.py
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@ -11,15 +11,6 @@ import vltest_bootstrap
test.scenarios('vlt')
# This test documents a known Verilator timing limitation:
# Internal clocks (generated via `always #5 clk = ~clk`) don't properly
# trigger procedural blocks in --timing mode. Even explicit .sample() calls
# in always @(posedge clk) blocks don't execute.
#
# Root cause: Timing scheduler doesn't trigger NBA/active regions for
# internally generated clock edges.
#
# Workaround: Use module input clocks (see t_covergroup_auto_sample.v)
test.compile(verilator_flags2=["--timing"])
test.execute(fails=True, expect=r'%Error: .*Timeout')

6
test_regress/t/t_covergroup_clocking_internal.v
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@ -11,6 +11,12 @@
// for internal clocks due to Verilator timing scheduler limitations.
// The sample() call is generated but the NBA region isn't triggered.
//
// Root cause: Timing scheduler doesn't trigger NBA/active regions for
// internally generated clock edges. Even explicit .sample() calls in
// always @(posedge clk) blocks don't execute in --timing mode.
//
// Workaround: Use module input clocks (see t_covergroup_auto_sample.v)
//
// Solution: Call .sample() explicitly in an always block.
module t;

4
test_regress/t/t_covergroup_clocking_module_input.v
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@ -37,9 +37,7 @@ module t(/*AUTOARG*/
data <= cyc[1:0];
if (cyc == 5) begin
/* verilator lint_off IMPLICITSTATIC */
real cov = cg_inst.get_inst_coverage();
/* verilator lint_on IMPLICITSTATIC */
automatic real cov = cg_inst.get_inst_coverage();
$display("Coverage: %0.1f%%", cov);
// Should have hit all 4 bins (cycles 0-3) = 100%

4
test_regress/t/t_covergroup_cross_large.v
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@ -64,9 +64,7 @@ module t(/*AUTOARG*/
d <= cyc[7:4];
if (cyc == 20) begin
/* verilator lint_off IMPLICITSTATIC */
real inst_cov = cg_inst.get_inst_coverage();
/* verilator lint_on IMPLICITSTATIC */
automatic real inst_cov = cg_inst.get_inst_coverage();
$display("Coverage: %0.1f%%", inst_cov);
if (inst_cov < 1.0 || inst_cov > 100.0) begin

4
test_regress/t/t_covergroup_cross_small.v
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@ -47,9 +47,7 @@ module t(/*AUTOARG*/
b <= cyc[7:4];
if (cyc == 20) begin
/* verilator lint_off IMPLICITSTATIC */
real inst_cov = cg_inst.get_inst_coverage();
/* verilator lint_on IMPLICITSTATIC */
automatic real inst_cov = cg_inst.get_inst_coverage();
$display("Coverage: %0.1f%%", inst_cov);
$write("*-* All Finished *-*\n");

3
test_regress/t/t_covergroup_database.py
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@ -15,15 +15,12 @@ test.compile(verilator_flags2=['--coverage'])
test.execute()
# Check that coverage database contains functional coverage entries
# Format uses control characters as delimiters: C '^At^Bcovergroup^Apage...bin^Blow...h^Bcg.cp.low' count
test.file_grep(test.coverage_filename, r'covergroup')
test.file_grep(test.coverage_filename, r'bin.{0,2}low') # binlow with possible delimiter
test.file_grep(test.coverage_filename, r'bin.{0,2}high') # binhigh with possible delimiter
test.file_grep(test.coverage_filename, r'cg\.cp\.low')
test.file_grep(test.coverage_filename, r'cg\.cp\.high')
# Verify both bins have non-zero counts (they were both sampled)
test.file_grep(test.coverage_filename, r'.*bin.{0,2}low.*\' [1-9]')
test.file_grep(test.coverage_filename, r'.*bin.{0,2}high.*\' [1-9]')

5
test_regress/t/t_covergroup_extends.out Normal file
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@ -0,0 +1,5 @@
%Error-UNSUPPORTED: t/t_covergroup_extends.v:26:9: Unsupported: covergroup inheritance (extends) is not implemented
26 | covergroup extends g1;
| ^~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

7
test_regress/t/t_covergroup_extends.py
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@ -11,11 +11,6 @@ import vltest_bootstrap
test.scenarios('vlt')
# Covergroup inheritance with 'extends' is not yet supported
test.compile(
fails=test.vlt_all,
expect=
r'%Error: t/t_covergroup_extends.v:\d+:\d+: Unsupported: covergroup inheritance \(extends\) is not implemented'
)
test.lint(expect_filename=test.golden_filename, fails=True)
test.passes()

3
test_regress/t/t_covergroup_extends.v
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@ -1,10 +1,11 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// Covergroup inheritance with 'extends' is not yet supported
//
// This file ONLY is placed under the Creative Commons Public Domain
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
/* verilator lint_off COVERIGN */
module t;
class base;
enum {red, green, blue} color;

5
test_regress/t/t_covergroup_extends_newfirst.out Normal file
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@ -0,0 +1,5 @@
%Error-UNSUPPORTED: t/t_covergroup_extends_newfirst.v:29:9: Unsupported: covergroup inheritance (extends) is not implemented
29 | covergroup extends g1;
| ^~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

7
test_regress/t/t_covergroup_extends_newfirst.py
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@ -11,11 +11,6 @@ import vltest_bootstrap
test.scenarios('vlt')
# Covergroup inheritance with 'extends' is not yet supported
test.compile(
fails=test.vlt_all,
expect=
r'%Error: t/t_covergroup_extends_newfirst.v:\d+:\d+: Unsupported: covergroup inheritance \(extends\) is not implemented'
)
test.lint(expect_filename=test.golden_filename, fails=True)
test.passes()

3
test_regress/t/t_covergroup_extends_newfirst.v
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@ -1,10 +1,11 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// Covergroup inheritance with 'extends' is not yet supported
//
// This file ONLY is placed under the Creative Commons Public Domain
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
/* verilator lint_off COVERIGN */
module t;
class base;
function new();

2
test_regress/t/t_covergroup_illegal_bins.py
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@ -1,8 +1,6 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Test that illegal_bins are excluded from coverage (like ignore_bins)
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.

2
test_regress/t/t_covergroup_illegal_bins.v
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@ -1,5 +1,7 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// Test that illegal_bins are excluded from coverage (like ignore_bins)
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

2
test_regress/t/t_covergroup_static_coverage.py
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@ -11,8 +11,6 @@ import vltest_bootstrap
test.scenarios('vlt')
# Type-level (static) coverage using cg::get_coverage() compiles but returns placeholder value
# Test compiles successfully but runtime behavior is incorrect (returns 0.0)
test.compile()
test.passes()

6
test_regress/t/t_covergroup_static_coverage.v
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@ -1,11 +1,13 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// Test static get_coverage() with multiple instances.
// Type-level (static) coverage using cg::get_coverage() compiles but returns
// a placeholder value (0.0); runtime behavior is not fully correct.
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Test static get_coverage() with multiple instances
module t;
covergroup cg;

11
test_regress/t/t_covergroup_trans_3value.out Normal file
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@ -0,0 +1,11 @@
%Warning-CASEINCOMPLETE: t/t_covergroup_trans_3value.v:13:12: Case values incompletely covered (example pattern 0x3)
: ... note: In instance 't.cg'
13 | bins trans_3val = (0 => 1 => 2);
| ^~~~~~~~~~
... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest
... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
%Warning-CASEINCOMPLETE: t/t_covergroup_trans_3value.v:14:12: Case values incompletely covered (example pattern 0x3)
: ... note: In instance 't.cg'
14 | bins trans_3val_2 = (2 => 3 => 4);
| ^~~~~~~~~~~~
%Error: Exiting due to

5
test_regress/t/t_covergroup_trans_3value.py
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@ -11,9 +11,6 @@ import vltest_bootstrap
test.scenarios('vlt')
# Multi-value (3+) transition bins generate incomplete case statements
# This is a known limitation - complex transitions not fully supported
test.compile(fails=test.vlt_all,
expect=r'%Warning-CASEINCOMPLETE:.*Case values incompletely covered')
test.lint(expect_filename=test.golden_filename, fails=True)
test.passes()

2
test_regress/t/t_covergroup_trans_3value.v
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@ -1,4 +1,6 @@
// DESCRIPTION: Verilator: Test transition bins - 3-value sequences
// Known limitation: multi-value (3+) transition bins generate incomplete case
// statements; complex transitions are not fully supported.
// This file ONLY is placed into the Public Domain, for any use, without warranty.
// SPDX-License-Identifier: CC0-1.0

3
test_regress/t/t_covergroup_trans_ranges.py
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@ -11,7 +11,6 @@ import vltest_bootstrap
test.scenarios('vlt')
# Transition array bins are now supported
test.compile(verilator_flags2=["-Wno-IMPLICITSTATIC"])
test.compile()
test.passes()

3
test_regress/t/t_covergroup_trans_ranges.v
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@ -1,4 +1,5 @@
// DESCRIPTION: Verilator: Test transition bins - array bins
// Transition array bins are supported.
// This file ONLY is placed into the Public Domain, for any use, without warranty.
// SPDX-License-Identifier: CC0-1.0
@ -30,7 +31,7 @@ module t (/*AUTOARG*/
2: state <= 2; // 1 => 2 (hits trans_array[1=>2])
3: state <= 3; // 2 => 3 (hits trans_array[2=>3])
4: begin
real cov = cg_inst.get_inst_coverage();
automatic real cov = cg_inst.get_inst_coverage();
$display("Coverage: %f%%", cov);
// We should have hit all 3 array bins = 100%
if (cov >= 99.0) begin

7
test_regress/t/t_covergroup_trans_restart.out Normal file
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@ -0,0 +1,7 @@
%Warning-CASEINCOMPLETE: t/t_covergroup_trans_restart.v:13:12: Case values incompletely covered (example pattern 0x3)
: ... note: In instance 't.cg'
13 | bins trans_restart = (1 => 2 => 3);
| ^~~~~~~~~~~~~
... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest
... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
%Error: Exiting due to

5
test_regress/t/t_covergroup_trans_restart.py
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@ -11,9 +11,6 @@ import vltest_bootstrap
test.scenarios('vlt')
# Multi-value transition bins with restart semantics generate incomplete case statements
# This is a known limitation - complex transitions not fully supported
test.compile(fails=test.vlt_all,
expect=r'%Warning-CASEINCOMPLETE:.*Case values incompletely covered')
test.lint(expect_filename=test.golden_filename, fails=True)
test.passes()

2
test_regress/t/t_covergroup_trans_restart.v
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@ -1,4 +1,6 @@
// DESCRIPTION: Verilator: Test transition bins - restart behavior
// Known limitation: multi-value transition bins with restart semantics generate
// incomplete case statements; complex transitions are not fully supported.
// This file ONLY is placed into the Public Domain, for any use, without warranty.
// SPDX-License-Identifier: CC0-1.0

33
test_regress/t/t_covergroup_unsup.out
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@ -186,35 +186,8 @@
%Warning-COVERIGN: t/t_covergroup_unsup.v:174:10: Ignoring unsupported: explicit coverage cross bins
174 | bins bin_multiple_fields = binsof(p.inner_packet.field);
| ^~~~
%Warning-COVERIGN: t/t_covergroup_unsup.v:195:7: Ignoring unsupported: covergroup inheritance (extends)
195 | covergroup extends cg_empty;
| ^~~~~~~~~~
%Warning-COVERIGN: t/t_covergroup_unsup.v:99:13: Ignoring unsupported: cross references unknown coverpoint: a
: ... note: In instance 't'
99 | cross a, b iff (!rst);
| ^
%Warning-COVERIGN: t/t_covergroup_unsup.v:102:13: Ignoring unsupported: cross references unknown coverpoint: a
: ... note: In instance 't'
102 | cross a, b iff (!rst) {}
| ^
%Warning-COVERIGN: t/t_covergroup_unsup.v:105:13: Ignoring unsupported: cross references unknown coverpoint: a
: ... note: In instance 't'
105 | cross a, b { option.comment = "cross"; option.weight = 12; }
| ^
%Warning-COVERIGN: t/t_covergroup_unsup.v:108:13: Ignoring unsupported: cross references unknown coverpoint: a
: ... note: In instance 't'
108 | cross a, b {
| ^
%Warning-COVERIGN: t/t_covergroup_unsup.v:114:23: Ignoring unsupported: cross references unknown coverpoint: a
: ... note: In instance 't'
114 | my_cg_id: cross a, b iff (!rst);
| ^
%Warning-COVERIGN: t/t_covergroup_unsup.v:156:13: Ignoring unsupported: cross references unknown coverpoint: a
: ... note: In instance 't'
156 | cross a, b {
| ^
%Warning-COVERIGN: t/t_covergroup_unsup.v:185:7: Ignoring unsupported: covergroup clocking event on member variable
: ... note: In instance 't'
185 | covergroup cov1 @m_z;
%Error-UNSUPPORTED: t/t_covergroup_unsup.v:196:7: Unsupported: covergroup inheritance (extends) is not implemented
196 | covergroup extends cg_empty;
| ^~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

2
test_regress/t/t_covergroup_unsup.v
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@ -190,10 +190,12 @@ module t (
`endif
endclass
`ifndef T_COVERGROUP_UNSUP_IGN
class CgEmb;
covergroup extends cg_empty;
endgroup
endclass
`endif
initial begin
automatic cg_empty cov1 = new;