diff --git a/src/verilog.y b/src/verilog.y index c9a6c2ecb..64f6d80f1 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -6947,9 +6947,9 @@ covergroup_declaration: // ==IEEE: covergroup_declaration | yCOVERGROUP yEXTENDS idAny ';' /*cont*/ coverage_spec_or_optionListE /*cont*/ yENDGROUP endLabelE - { BBCOVERIGN($1, "Ignoring unsupported: covergroup inheritance (extends)"); - $$ = new AstCovergroup{$3, *$3, nullptr, nullptr, $5, nullptr}; - GRAMMARP->endLabel($7, $$, $7); } + { $$ = nullptr; + BBUNSUP($1, "Unsupported: covergroup inheritance (extends) is not implemented"); + DEL($5); } ; cgPortListE: @@ -7921,11 +7921,15 @@ class_item: // ==IEEE: class_item | timeunits_declaration { $$ = $1; } | covergroup_declaration { - const string cgName = $1->name(); - $1->name("__vlAnonCG_" + cgName); - AstVar* const newp = new AstVar{$1->fileline(), VVarType::VAR, cgName, - VFlagChildDType{}, new AstRefDType($1->fileline(), $1->name())}; - $$ = addNextNull($1, newp); + if ($1) { + const string cgName = $1->name(); + $1->name("__vlAnonCG_" + cgName); + AstVar* const newp = new AstVar{$1->fileline(), VVarType::VAR, cgName, + VFlagChildDType{}, new AstRefDType($1->fileline(), $1->name())}; + $$ = addNextNull($1, newp); + } else { + $$ = nullptr; + } } // // local_parameter_declaration under parameter_declaration | parameter_declaration ';' { $$ = $1; } diff --git a/test_regress/t/t_covergroup_auto_bins.py b/test_regress/t/t_covergroup_auto_bins.py index e66ef82df..2351d6963 100755 --- a/test_regress/t/t_covergroup_auto_bins.py +++ b/test_regress/t/t_covergroup_auto_bins.py @@ -1,8 +1,6 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Test automatic bins: bins auto[N] -# # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. diff --git a/test_regress/t/t_covergroup_auto_bins.v b/test_regress/t/t_covergroup_auto_bins.v index ef9c66948..9b8726006 100644 --- a/test_regress/t/t_covergroup_auto_bins.v +++ b/test_regress/t/t_covergroup_auto_bins.v @@ -1,5 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // +// Test automatic bins: bins auto[N] +// // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_covergroup_auto_sample.py b/test_regress/t/t_covergroup_auto_sample.py index c1943295f..2351d6963 100755 --- a/test_regress/t/t_covergroup_auto_sample.py +++ b/test_regress/t/t_covergroup_auto_sample.py @@ -9,7 +9,6 @@ import vltest_bootstrap -# Test automatic sampling with --no-timing (default) test.scenarios('vlt') test.compile() diff --git a/test_regress/t/t_covergroup_auto_sample.v b/test_regress/t/t_covergroup_auto_sample.v index 4c7d772ef..25739de7d 100644 --- a/test_regress/t/t_covergroup_auto_sample.v +++ b/test_regress/t/t_covergroup_auto_sample.v @@ -1,4 +1,5 @@ // DESCRIPTION: Verilator: Test automatic sampling with clocking events +// Tests --no-timing (default) mode; see t_covergroup_auto_sample_timing for --timing variant. // This file ONLY is placed into the Public Domain, for any use, without warranty. // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_covergroup_auto_sample_timing.py b/test_regress/t/t_covergroup_auto_sample_timing.py index 071d14c14..f9dff9c4b 100755 --- a/test_regress/t/t_covergroup_auto_sample_timing.py +++ b/test_regress/t/t_covergroup_auto_sample_timing.py @@ -9,7 +9,6 @@ import vltest_bootstrap -# Test automatic sampling with --timing test.scenarios('vlt') # Use the same .v file as the non-timing test diff --git a/test_regress/t/t_covergroup_clocking_internal.py b/test_regress/t/t_covergroup_clocking_internal.py index 108fb561a..9e877cb53 100755 --- a/test_regress/t/t_covergroup_clocking_internal.py +++ b/test_regress/t/t_covergroup_clocking_internal.py @@ -11,15 +11,6 @@ import vltest_bootstrap test.scenarios('vlt') -# This test documents a known Verilator timing limitation: -# Internal clocks (generated via `always #5 clk = ~clk`) don't properly -# trigger procedural blocks in --timing mode. Even explicit .sample() calls -# in always @(posedge clk) blocks don't execute. -# -# Root cause: Timing scheduler doesn't trigger NBA/active regions for -# internally generated clock edges. -# -# Workaround: Use module input clocks (see t_covergroup_auto_sample.v) test.compile(verilator_flags2=["--timing"]) test.execute(fails=True, expect=r'%Error: .*Timeout') diff --git a/test_regress/t/t_covergroup_clocking_internal.v b/test_regress/t/t_covergroup_clocking_internal.v index 98ef639f6..39a245780 100644 --- a/test_regress/t/t_covergroup_clocking_internal.v +++ b/test_regress/t/t_covergroup_clocking_internal.v @@ -11,6 +11,12 @@ // for internal clocks due to Verilator timing scheduler limitations. // The sample() call is generated but the NBA region isn't triggered. // +// Root cause: Timing scheduler doesn't trigger NBA/active regions for +// internally generated clock edges. Even explicit .sample() calls in +// always @(posedge clk) blocks don't execute in --timing mode. +// +// Workaround: Use module input clocks (see t_covergroup_auto_sample.v) +// // Solution: Call .sample() explicitly in an always block. module t; diff --git a/test_regress/t/t_covergroup_clocking_module_input.v b/test_regress/t/t_covergroup_clocking_module_input.v index 22e40583c..c38d5ff94 100644 --- a/test_regress/t/t_covergroup_clocking_module_input.v +++ b/test_regress/t/t_covergroup_clocking_module_input.v @@ -37,9 +37,7 @@ module t(/*AUTOARG*/ data <= cyc[1:0]; if (cyc == 5) begin - /* verilator lint_off IMPLICITSTATIC */ - real cov = cg_inst.get_inst_coverage(); - /* verilator lint_on IMPLICITSTATIC */ + automatic real cov = cg_inst.get_inst_coverage(); $display("Coverage: %0.1f%%", cov); // Should have hit all 4 bins (cycles 0-3) = 100% diff --git a/test_regress/t/t_covergroup_cross_large.v b/test_regress/t/t_covergroup_cross_large.v index ca4c200b6..38fa8f4ce 100644 --- a/test_regress/t/t_covergroup_cross_large.v +++ b/test_regress/t/t_covergroup_cross_large.v @@ -64,9 +64,7 @@ module t(/*AUTOARG*/ d <= cyc[7:4]; if (cyc == 20) begin - /* verilator lint_off IMPLICITSTATIC */ - real inst_cov = cg_inst.get_inst_coverage(); - /* verilator lint_on IMPLICITSTATIC */ + automatic real inst_cov = cg_inst.get_inst_coverage(); $display("Coverage: %0.1f%%", inst_cov); if (inst_cov < 1.0 || inst_cov > 100.0) begin diff --git a/test_regress/t/t_covergroup_cross_small.v b/test_regress/t/t_covergroup_cross_small.v index e8c51dd82..415c4e1de 100644 --- a/test_regress/t/t_covergroup_cross_small.v +++ b/test_regress/t/t_covergroup_cross_small.v @@ -47,9 +47,7 @@ module t(/*AUTOARG*/ b <= cyc[7:4]; if (cyc == 20) begin - /* verilator lint_off IMPLICITSTATIC */ - real inst_cov = cg_inst.get_inst_coverage(); - /* verilator lint_on IMPLICITSTATIC */ + automatic real inst_cov = cg_inst.get_inst_coverage(); $display("Coverage: %0.1f%%", inst_cov); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_covergroup_database.py b/test_regress/t/t_covergroup_database.py index b1a3cf689..2748786a8 100755 --- a/test_regress/t/t_covergroup_database.py +++ b/test_regress/t/t_covergroup_database.py @@ -15,15 +15,12 @@ test.compile(verilator_flags2=['--coverage']) test.execute() -# Check that coverage database contains functional coverage entries -# Format uses control characters as delimiters: C '^At^Bcovergroup^Apage...bin^Blow...h^Bcg.cp.low' count test.file_grep(test.coverage_filename, r'covergroup') test.file_grep(test.coverage_filename, r'bin.{0,2}low') # binlow with possible delimiter test.file_grep(test.coverage_filename, r'bin.{0,2}high') # binhigh with possible delimiter test.file_grep(test.coverage_filename, r'cg\.cp\.low') test.file_grep(test.coverage_filename, r'cg\.cp\.high') -# Verify both bins have non-zero counts (they were both sampled) test.file_grep(test.coverage_filename, r'.*bin.{0,2}low.*\' [1-9]') test.file_grep(test.coverage_filename, r'.*bin.{0,2}high.*\' [1-9]') diff --git a/test_regress/t/t_covergroup_extends.out b/test_regress/t/t_covergroup_extends.out new file mode 100644 index 000000000..3f425743f --- /dev/null +++ b/test_regress/t/t_covergroup_extends.out @@ -0,0 +1,5 @@ +%Error-UNSUPPORTED: t/t_covergroup_extends.v:26:9: Unsupported: covergroup inheritance (extends) is not implemented + 26 | covergroup extends g1; + | ^~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_covergroup_extends.py b/test_regress/t/t_covergroup_extends.py index 25e90b5da..ef7407f24 100755 --- a/test_regress/t/t_covergroup_extends.py +++ b/test_regress/t/t_covergroup_extends.py @@ -11,11 +11,6 @@ import vltest_bootstrap test.scenarios('vlt') -# Covergroup inheritance with 'extends' is not yet supported -test.compile( - fails=test.vlt_all, - expect= - r'%Error: t/t_covergroup_extends.v:\d+:\d+: Unsupported: covergroup inheritance \(extends\) is not implemented' -) +test.lint(expect_filename=test.golden_filename, fails=True) test.passes() diff --git a/test_regress/t/t_covergroup_extends.v b/test_regress/t/t_covergroup_extends.v index 880857d4b..f1240cd4b 100644 --- a/test_regress/t/t_covergroup_extends.v +++ b/test_regress/t/t_covergroup_extends.v @@ -1,10 +1,11 @@ // DESCRIPTION: Verilator: Verilog Test module // +// Covergroup inheritance with 'extends' is not yet supported +// // This file ONLY is placed under the Creative Commons Public Domain // SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 -/* verilator lint_off COVERIGN */ module t; class base; enum {red, green, blue} color; diff --git a/test_regress/t/t_covergroup_extends_newfirst.out b/test_regress/t/t_covergroup_extends_newfirst.out new file mode 100644 index 000000000..b08fe2656 --- /dev/null +++ b/test_regress/t/t_covergroup_extends_newfirst.out @@ -0,0 +1,5 @@ +%Error-UNSUPPORTED: t/t_covergroup_extends_newfirst.v:29:9: Unsupported: covergroup inheritance (extends) is not implemented + 29 | covergroup extends g1; + | ^~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_covergroup_extends_newfirst.py b/test_regress/t/t_covergroup_extends_newfirst.py index 71a498320..ef7407f24 100755 --- a/test_regress/t/t_covergroup_extends_newfirst.py +++ b/test_regress/t/t_covergroup_extends_newfirst.py @@ -11,11 +11,6 @@ import vltest_bootstrap test.scenarios('vlt') -# Covergroup inheritance with 'extends' is not yet supported -test.compile( - fails=test.vlt_all, - expect= - r'%Error: t/t_covergroup_extends_newfirst.v:\d+:\d+: Unsupported: covergroup inheritance \(extends\) is not implemented' -) +test.lint(expect_filename=test.golden_filename, fails=True) test.passes() diff --git a/test_regress/t/t_covergroup_extends_newfirst.v b/test_regress/t/t_covergroup_extends_newfirst.v index aee7a2f7b..2daba60f5 100644 --- a/test_regress/t/t_covergroup_extends_newfirst.v +++ b/test_regress/t/t_covergroup_extends_newfirst.v @@ -1,10 +1,11 @@ // DESCRIPTION: Verilator: Verilog Test module // +// Covergroup inheritance with 'extends' is not yet supported +// // This file ONLY is placed under the Creative Commons Public Domain // SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 -/* verilator lint_off COVERIGN */ module t; class base; function new(); diff --git a/test_regress/t/t_covergroup_illegal_bins.py b/test_regress/t/t_covergroup_illegal_bins.py index d11b6a975..2351d6963 100755 --- a/test_regress/t/t_covergroup_illegal_bins.py +++ b/test_regress/t/t_covergroup_illegal_bins.py @@ -1,8 +1,6 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Test that illegal_bins are excluded from coverage (like ignore_bins) -# # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. diff --git a/test_regress/t/t_covergroup_illegal_bins.v b/test_regress/t/t_covergroup_illegal_bins.v index 19721c995..cacfd7558 100644 --- a/test_regress/t/t_covergroup_illegal_bins.v +++ b/test_regress/t/t_covergroup_illegal_bins.v @@ -1,5 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // +// Test that illegal_bins are excluded from coverage (like ignore_bins) +// // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_covergroup_static_coverage.py b/test_regress/t/t_covergroup_static_coverage.py index be0e01535..46f459325 100755 --- a/test_regress/t/t_covergroup_static_coverage.py +++ b/test_regress/t/t_covergroup_static_coverage.py @@ -11,8 +11,6 @@ import vltest_bootstrap test.scenarios('vlt') -# Type-level (static) coverage using cg::get_coverage() compiles but returns placeholder value -# Test compiles successfully but runtime behavior is incorrect (returns 0.0) test.compile() test.passes() diff --git a/test_regress/t/t_covergroup_static_coverage.v b/test_regress/t/t_covergroup_static_coverage.v index 4faf3b95c..5d60de872 100644 --- a/test_regress/t/t_covergroup_static_coverage.v +++ b/test_regress/t/t_covergroup_static_coverage.v @@ -1,11 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // +// Test static get_coverage() with multiple instances. +// Type-level (static) coverage using cg::get_coverage() compiles but returns +// a placeholder value (0.0); runtime behavior is not fully correct. +// // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -// Test static get_coverage() with multiple instances - module t; covergroup cg; diff --git a/test_regress/t/t_covergroup_trans_3value.out b/test_regress/t/t_covergroup_trans_3value.out new file mode 100644 index 000000000..034bd05a5 --- /dev/null +++ b/test_regress/t/t_covergroup_trans_3value.out @@ -0,0 +1,11 @@ +%Warning-CASEINCOMPLETE: t/t_covergroup_trans_3value.v:13:12: Case values incompletely covered (example pattern 0x3) + : ... note: In instance 't.cg' + 13 | bins trans_3val = (0 => 1 => 2); + | ^~~~~~~~~~ + ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest + ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. +%Warning-CASEINCOMPLETE: t/t_covergroup_trans_3value.v:14:12: Case values incompletely covered (example pattern 0x3) + : ... note: In instance 't.cg' + 14 | bins trans_3val_2 = (2 => 3 => 4); + | ^~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_covergroup_trans_3value.py b/test_regress/t/t_covergroup_trans_3value.py index 226a5a1f3..77a0ac64b 100755 --- a/test_regress/t/t_covergroup_trans_3value.py +++ b/test_regress/t/t_covergroup_trans_3value.py @@ -11,9 +11,6 @@ import vltest_bootstrap test.scenarios('vlt') -# Multi-value (3+) transition bins generate incomplete case statements -# This is a known limitation - complex transitions not fully supported -test.compile(fails=test.vlt_all, - expect=r'%Warning-CASEINCOMPLETE:.*Case values incompletely covered') +test.lint(expect_filename=test.golden_filename, fails=True) test.passes() diff --git a/test_regress/t/t_covergroup_trans_3value.v b/test_regress/t/t_covergroup_trans_3value.v index f30170858..dc8d4407a 100644 --- a/test_regress/t/t_covergroup_trans_3value.v +++ b/test_regress/t/t_covergroup_trans_3value.v @@ -1,4 +1,6 @@ // DESCRIPTION: Verilator: Test transition bins - 3-value sequences +// Known limitation: multi-value (3+) transition bins generate incomplete case +// statements; complex transitions are not fully supported. // This file ONLY is placed into the Public Domain, for any use, without warranty. // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_covergroup_trans_ranges.py b/test_regress/t/t_covergroup_trans_ranges.py index 01b5938a5..4348f3df1 100755 --- a/test_regress/t/t_covergroup_trans_ranges.py +++ b/test_regress/t/t_covergroup_trans_ranges.py @@ -11,7 +11,6 @@ import vltest_bootstrap test.scenarios('vlt') -# Transition array bins are now supported -test.compile(verilator_flags2=["-Wno-IMPLICITSTATIC"]) +test.compile() test.passes() diff --git a/test_regress/t/t_covergroup_trans_ranges.v b/test_regress/t/t_covergroup_trans_ranges.v index 115b1b073..2321c21fe 100644 --- a/test_regress/t/t_covergroup_trans_ranges.v +++ b/test_regress/t/t_covergroup_trans_ranges.v @@ -1,4 +1,5 @@ // DESCRIPTION: Verilator: Test transition bins - array bins +// Transition array bins are supported. // This file ONLY is placed into the Public Domain, for any use, without warranty. // SPDX-License-Identifier: CC0-1.0 @@ -30,7 +31,7 @@ module t (/*AUTOARG*/ 2: state <= 2; // 1 => 2 (hits trans_array[1=>2]) 3: state <= 3; // 2 => 3 (hits trans_array[2=>3]) 4: begin - real cov = cg_inst.get_inst_coverage(); + automatic real cov = cg_inst.get_inst_coverage(); $display("Coverage: %f%%", cov); // We should have hit all 3 array bins = 100% if (cov >= 99.0) begin diff --git a/test_regress/t/t_covergroup_trans_restart.out b/test_regress/t/t_covergroup_trans_restart.out new file mode 100644 index 000000000..e21357c52 --- /dev/null +++ b/test_regress/t/t_covergroup_trans_restart.out @@ -0,0 +1,7 @@ +%Warning-CASEINCOMPLETE: t/t_covergroup_trans_restart.v:13:12: Case values incompletely covered (example pattern 0x3) + : ... note: In instance 't.cg' + 13 | bins trans_restart = (1 => 2 => 3); + | ^~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest + ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_covergroup_trans_restart.py b/test_regress/t/t_covergroup_trans_restart.py index 10bbe4350..77a0ac64b 100755 --- a/test_regress/t/t_covergroup_trans_restart.py +++ b/test_regress/t/t_covergroup_trans_restart.py @@ -11,9 +11,6 @@ import vltest_bootstrap test.scenarios('vlt') -# Multi-value transition bins with restart semantics generate incomplete case statements -# This is a known limitation - complex transitions not fully supported -test.compile(fails=test.vlt_all, - expect=r'%Warning-CASEINCOMPLETE:.*Case values incompletely covered') +test.lint(expect_filename=test.golden_filename, fails=True) test.passes() diff --git a/test_regress/t/t_covergroup_trans_restart.v b/test_regress/t/t_covergroup_trans_restart.v index 0d4895f08..ec7b3357c 100644 --- a/test_regress/t/t_covergroup_trans_restart.v +++ b/test_regress/t/t_covergroup_trans_restart.v @@ -1,4 +1,6 @@ // DESCRIPTION: Verilator: Test transition bins - restart behavior +// Known limitation: multi-value transition bins with restart semantics generate +// incomplete case statements; complex transitions are not fully supported. // This file ONLY is placed into the Public Domain, for any use, without warranty. // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_covergroup_unsup.out b/test_regress/t/t_covergroup_unsup.out index 614c42239..6ab3c74b8 100644 --- a/test_regress/t/t_covergroup_unsup.out +++ b/test_regress/t/t_covergroup_unsup.out @@ -186,35 +186,8 @@ %Warning-COVERIGN: t/t_covergroup_unsup.v:174:10: Ignoring unsupported: explicit coverage cross bins 174 | bins bin_multiple_fields = binsof(p.inner_packet.field); | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:195:7: Ignoring unsupported: covergroup inheritance (extends) - 195 | covergroup extends cg_empty; - | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:99:13: Ignoring unsupported: cross references unknown coverpoint: a - : ... note: In instance 't' - 99 | cross a, b iff (!rst); - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:102:13: Ignoring unsupported: cross references unknown coverpoint: a - : ... note: In instance 't' - 102 | cross a, b iff (!rst) {} - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:105:13: Ignoring unsupported: cross references unknown coverpoint: a - : ... note: In instance 't' - 105 | cross a, b { option.comment = "cross"; option.weight = 12; } - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:108:13: Ignoring unsupported: cross references unknown coverpoint: a - : ... note: In instance 't' - 108 | cross a, b { - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:114:23: Ignoring unsupported: cross references unknown coverpoint: a - : ... note: In instance 't' - 114 | my_cg_id: cross a, b iff (!rst); - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:156:13: Ignoring unsupported: cross references unknown coverpoint: a - : ... note: In instance 't' - 156 | cross a, b { - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:185:7: Ignoring unsupported: covergroup clocking event on member variable - : ... note: In instance 't' - 185 | covergroup cov1 @m_z; +%Error-UNSUPPORTED: t/t_covergroup_unsup.v:196:7: Unsupported: covergroup inheritance (extends) is not implemented + 196 | covergroup extends cg_empty; | ^~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_covergroup_unsup.v b/test_regress/t/t_covergroup_unsup.v index 36e6d7aa7..eaeb7aa21 100644 --- a/test_regress/t/t_covergroup_unsup.v +++ b/test_regress/t/t_covergroup_unsup.v @@ -190,10 +190,12 @@ module t ( `endif endclass +`ifndef T_COVERGROUP_UNSUP_IGN class CgEmb; covergroup extends cg_empty; endgroup endclass +`endif initial begin automatic cg_empty cov1 = new;