Fix module resolution with __, bug631.

Changes

@@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.847 devel
 
+**** Fix module resolution with __, bug631. [Jason McMullan]
+
 
 * Verilator 3.846 2013-03-09
 

src/V3EmitCSyms.cpp

@@ -102,7 +102,7 @@ class EmitCSyms : EmitCBaseVisitor {
 	    if (rsvd != "") {
 		// Generally V3Name should find all of these and throw SYMRSVDWORD.
 		// We'll still check here because the compiler errors resulting if we miss this warning are SO nasty
-		nodep->v3error("Symbol matching "+rsvd+" reserved word reached emitter, should have hit SYMRSVDWORD: '"<<nodep->name()<<"'");
+		nodep->v3error("Symbol matching "+rsvd+" reserved word reached emitter, should have hit SYMRSVDWORD: '"<<nodep->prettyName()<<"'");
 	    }
 	}
     }

src/V3LinkCells.cpp

@@ -75,7 +75,7 @@ public:
 void LinkCellsGraph::loopsMessageCb(V3GraphVertex* vertexp) {
     if (LinkCellsVertex* vvertexp = dynamic_cast<LinkCellsVertex*>(vertexp)) {
 	vvertexp->modp()->v3error("Recursive module (module instantiates itself): "
-				  <<vvertexp->modp()->name());
+				  <<vvertexp->modp()->prettyName());
 	V3Error::abortIfErrors();
     } else {  // Everything should match above, but...
 	v3fatalSrc("Recursive instantiations");
@@ -128,8 +128,9 @@ private:
 	    // Read-subfile
 	    // If file not found, make AstNotFoundModule, rather than error out.
 	    // We'll throw the error when we know the module will really be needed.
+	    string prettyName = AstNode::prettyName(modName);
 	    V3Parse parser (v3Global.rootp(), m_filterp, m_parseSymp);
-	    parser.parseFile(nodep->fileline(), modName, false, "");
+	    parser.parseFile(nodep->fileline(), prettyName, false, "");
 	    V3Error::abortIfErrors();
 	    // We've read new modules, grab new pointers to their names
 	    readModNames();
@@ -137,7 +138,7 @@ private:
 	    modp = m_mods.rootp()->findIdFallback(modName)->nodep()->castNodeModule();
 	    if (!modp) {
 		// This shouldn't throw a message as parseFile will create a AstNotFoundModule for us
-		nodep->v3error("Can't resolve module reference: "<<modName);
+		nodep->v3error("Can't resolve module reference: "<<prettyName);
 	    }
 	}
 	return modp;
@@ -189,7 +190,7 @@ private:
 			      <<"' does not match "<<nodep->typeName()<<" name: "<<nodep->prettyName());
 	    }
 	}
-	bool topMatch = (v3Global.opt.topModule()==nodep->name());
+	bool topMatch = (v3Global.opt.topModule()==nodep->prettyName());
 	if (topMatch) {
 	    m_topVertexp = vertex(nodep);
 	    UINFO(2,"Link --top-module: "<<nodep<<endl);

src/V3LinkDot.cpp

@@ -698,7 +698,7 @@ private:
 			&& (!m_ftaskp || m_ftaskp != foundp->nodep())  // Not the function's variable hiding function
 			&& !nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)
 			&& !foundp->nodep()->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)) {
-			nodep->v3warn(VARHIDDEN,"Declaration of signal hides declaration in upper scope: "<<nodep->name()<<endl
+			nodep->v3warn(VARHIDDEN,"Declaration of signal hides declaration in upper scope: "<<nodep->prettyName()<<endl
 				      <<foundp->nodep()->warnMore()<<"... Location of original declaration");
 		    }
 		    ins = true;
@@ -744,7 +744,7 @@ private:
 		// User can disable the message at either point
 		if (!nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)
 		    && !foundp->nodep()->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)) {
-		    nodep->v3warn(VARHIDDEN,"Declaration of enum value hides declaration in upper scope: "<<nodep->name()<<endl
+		    nodep->v3warn(VARHIDDEN,"Declaration of enum value hides declaration in upper scope: "<<nodep->prettyName()<<endl
 				  <<foundp->nodep()->warnMore()<<"... Location of original declaration");
 		}
 		ins = true;
@@ -858,7 +858,7 @@ private:
     }
     virtual void visit(AstDefParam* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
-	nodep->v3warn(DEFPARAM,"Suggest replace defparam with Verilog 2001 #(."<<nodep->name()<<"(...etc...))");
+	nodep->v3warn(DEFPARAM,"Suggest replace defparam with Verilog 2001 #(."<<nodep->prettyName()<<"(...etc...))");
 	VSymEnt* foundp = m_statep->getNodeSym(nodep)->findIdFallback(nodep->path());
 	AstCell* cellp = foundp->nodep()->castCell();
 	if (!cellp) {

src/V3LinkJump.cpp

@@ -227,7 +227,7 @@ private:
 	    }
 	}
 	//if (debug()>=9) { UINFO(0,"\n"); beginp->dumpTree(cout,"  labeli: "); }
-	if (!beginp) { nodep->v3error("disable isn't underneath a begin with name: "<<nodep->name()); }
+	if (!beginp) { nodep->v3error("disable isn't underneath a begin with name: "<<nodep->prettyName()); }
 	else {
 	    // Jump to the end of the named begin
 	    AstJumpLabel* labelp = findAddLabel(beginp, false);

src/V3Name.cpp

@@ -66,7 +66,7 @@ private:
 	    } else {
 		string rsvd = m_words.isKeyword(nodep->name());
 		if (rsvd != "") {
-		    nodep->v3warn(SYMRSVDWORD,"Symbol matches "+rsvd+": '"<<nodep->name()<<"'");
+		    nodep->v3warn(SYMRSVDWORD,"Symbol matches "+rsvd+": '"<<nodep->prettyName()<<"'");
 		    string newname = (string)"__SYM__"+nodep->name();
 		    nodep->name(newname);
 		}

src/V3Unroll.cpp

@@ -115,7 +115,7 @@ private:
 	m_forVarp = initAssp->lhsp()->castVarRef()->varp();
 	m_forVscp = initAssp->lhsp()->castVarRef()->varScopep();
 	if (nodep->castGenFor() && !m_forVarp->isGenVar()) {
-	    nodep->v3error("Non-genvar used in generate for: "<<m_forVarp->name()<<endl);
+	    nodep->v3error("Non-genvar used in generate for: "<<m_forVarp->prettyName()<<endl);
 	}
 	if (m_generate) V3Const::constifyParamsEdit(initAssp->rhsp());  // rhsp may change
 	AstConst* constInitp = initAssp->rhsp()->castConst();

test_regress/t/t_inst_v2k.v

@@ -18,16 +18,17 @@ module t (/*AUTOARG*/
    reg ionewire;
 
 `ifdef never_just_for_verilog_mode
-   wire oonewire;		// From sub of t_inst_v2k_sub.v
+   wire oonewire;		// From sub of t_inst_v2k__sub.v
 `endif
 
-   wire [7:0]		osizedreg;		// From sub of t_inst_v2k_sub.v
+   wire [7:0]		osizedreg;		// From sub of t_inst_v2k__sub.v
    wire [1:0]		tied;
    wire [3:0]		tied_also;
 
    hello hsub (.tied_also);
 
-   t_inst_v2k_sub sub
+   // Double underscore tests bug631
+   t_inst_v2k__sub sub
      (
       // Outputs
       .osizedreg			(osizedreg[7:0]),

test_regress/t/t_inst_v2k__sub.vi

@@ -5,7 +5,7 @@
 // without warranty, 2003 by Wilson Snyder.
 
 // This file is named .vi to test +libext+ flags.
-module t_inst_v2k_sub
+module t_inst_v2k__sub
   (
    output reg [7:0] osizedreg,
    output wire oonewire /*verilator public*/,