From 464679c78b7778149fc3b8cc4999392681f28b5d Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 12 Mar 2013 07:27:17 -0400 Subject: [PATCH] Fix module resolution with __, bug631. --- Changes | 2 ++ src/V3EmitCSyms.cpp | 2 +- src/V3LinkCells.cpp | 9 +++++---- src/V3LinkDot.cpp | 6 +++--- src/V3LinkJump.cpp | 2 +- src/V3Name.cpp | 2 +- src/V3Unroll.cpp | 2 +- test_regress/t/t_inst_v2k.v | 7 ++++--- test_regress/t/{t_inst_v2k_sub.vi => t_inst_v2k__sub.vi} | 2 +- 9 files changed, 19 insertions(+), 15 deletions(-) rename test_regress/t/{t_inst_v2k_sub.vi => t_inst_v2k__sub.vi} (95%) diff --git a/Changes b/Changes index ffc7ebe17..f92e7872f 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks! * Verilator 3.847 devel +**** Fix module resolution with __, bug631. [Jason McMullan] + * Verilator 3.846 2013-03-09 diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 1d9ca61c2..f17d854fb 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -102,7 +102,7 @@ class EmitCSyms : EmitCBaseVisitor { if (rsvd != "") { // Generally V3Name should find all of these and throw SYMRSVDWORD. // We'll still check here because the compiler errors resulting if we miss this warning are SO nasty - nodep->v3error("Symbol matching "+rsvd+" reserved word reached emitter, should have hit SYMRSVDWORD: '"<name()<<"'"); + nodep->v3error("Symbol matching "+rsvd+" reserved word reached emitter, should have hit SYMRSVDWORD: '"<prettyName()<<"'"); } } } diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp index 92d5c78c2..ad8a9dfc3 100644 --- a/src/V3LinkCells.cpp +++ b/src/V3LinkCells.cpp @@ -75,7 +75,7 @@ public: void LinkCellsGraph::loopsMessageCb(V3GraphVertex* vertexp) { if (LinkCellsVertex* vvertexp = dynamic_cast(vertexp)) { vvertexp->modp()->v3error("Recursive module (module instantiates itself): " - <modp()->name()); + <modp()->prettyName()); V3Error::abortIfErrors(); } else { // Everything should match above, but... v3fatalSrc("Recursive instantiations"); @@ -128,8 +128,9 @@ private: // Read-subfile // If file not found, make AstNotFoundModule, rather than error out. // We'll throw the error when we know the module will really be needed. + string prettyName = AstNode::prettyName(modName); V3Parse parser (v3Global.rootp(), m_filterp, m_parseSymp); - parser.parseFile(nodep->fileline(), modName, false, ""); + parser.parseFile(nodep->fileline(), prettyName, false, ""); V3Error::abortIfErrors(); // We've read new modules, grab new pointers to their names readModNames(); @@ -137,7 +138,7 @@ private: modp = m_mods.rootp()->findIdFallback(modName)->nodep()->castNodeModule(); if (!modp) { // This shouldn't throw a message as parseFile will create a AstNotFoundModule for us - nodep->v3error("Can't resolve module reference: "<v3error("Can't resolve module reference: "<typeName()<<" name: "<prettyName()); } } - bool topMatch = (v3Global.opt.topModule()==nodep->name()); + bool topMatch = (v3Global.opt.topModule()==nodep->prettyName()); if (topMatch) { m_topVertexp = vertex(nodep); UINFO(2,"Link --top-module: "<nodep()) // Not the function's variable hiding function && !nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN) && !foundp->nodep()->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)) { - nodep->v3warn(VARHIDDEN,"Declaration of signal hides declaration in upper scope: "<name()<v3warn(VARHIDDEN,"Declaration of signal hides declaration in upper scope: "<prettyName()<nodep()->warnMore()<<"... Location of original declaration"); } ins = true; @@ -744,7 +744,7 @@ private: // User can disable the message at either point if (!nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN) && !foundp->nodep()->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)) { - nodep->v3warn(VARHIDDEN,"Declaration of enum value hides declaration in upper scope: "<name()<v3warn(VARHIDDEN,"Declaration of enum value hides declaration in upper scope: "<prettyName()<nodep()->warnMore()<<"... Location of original declaration"); } ins = true; @@ -858,7 +858,7 @@ private: } virtual void visit(AstDefParam* nodep, AstNUser*) { nodep->iterateChildren(*this); - nodep->v3warn(DEFPARAM,"Suggest replace defparam with Verilog 2001 #(."<name()<<"(...etc...))"); + nodep->v3warn(DEFPARAM,"Suggest replace defparam with Verilog 2001 #(."<prettyName()<<"(...etc...))"); VSymEnt* foundp = m_statep->getNodeSym(nodep)->findIdFallback(nodep->path()); AstCell* cellp = foundp->nodep()->castCell(); if (!cellp) { diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp index 987fdd074..979ca58a0 100644 --- a/src/V3LinkJump.cpp +++ b/src/V3LinkJump.cpp @@ -227,7 +227,7 @@ private: } } //if (debug()>=9) { UINFO(0,"\n"); beginp->dumpTree(cout," labeli: "); } - if (!beginp) { nodep->v3error("disable isn't underneath a begin with name: "<name()); } + if (!beginp) { nodep->v3error("disable isn't underneath a begin with name: "<prettyName()); } else { // Jump to the end of the named begin AstJumpLabel* labelp = findAddLabel(beginp, false); diff --git a/src/V3Name.cpp b/src/V3Name.cpp index 12b1d0c23..0fdc2b4ea 100644 --- a/src/V3Name.cpp +++ b/src/V3Name.cpp @@ -66,7 +66,7 @@ private: } else { string rsvd = m_words.isKeyword(nodep->name()); if (rsvd != "") { - nodep->v3warn(SYMRSVDWORD,"Symbol matches "+rsvd+": '"<name()<<"'"); + nodep->v3warn(SYMRSVDWORD,"Symbol matches "+rsvd+": '"<prettyName()<<"'"); string newname = (string)"__SYM__"+nodep->name(); nodep->name(newname); } diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp index ee930c3b9..ceeee1856 100644 --- a/src/V3Unroll.cpp +++ b/src/V3Unroll.cpp @@ -115,7 +115,7 @@ private: m_forVarp = initAssp->lhsp()->castVarRef()->varp(); m_forVscp = initAssp->lhsp()->castVarRef()->varScopep(); if (nodep->castGenFor() && !m_forVarp->isGenVar()) { - nodep->v3error("Non-genvar used in generate for: "<name()<v3error("Non-genvar used in generate for: "<prettyName()<rhsp()); // rhsp may change AstConst* constInitp = initAssp->rhsp()->castConst(); diff --git a/test_regress/t/t_inst_v2k.v b/test_regress/t/t_inst_v2k.v index 3cad02087..b2340e028 100644 --- a/test_regress/t/t_inst_v2k.v +++ b/test_regress/t/t_inst_v2k.v @@ -18,16 +18,17 @@ module t (/*AUTOARG*/ reg ionewire; `ifdef never_just_for_verilog_mode - wire oonewire; // From sub of t_inst_v2k_sub.v + wire oonewire; // From sub of t_inst_v2k__sub.v `endif - wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v + wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v wire [1:0] tied; wire [3:0] tied_also; hello hsub (.tied_also); - t_inst_v2k_sub sub + // Double underscore tests bug631 + t_inst_v2k__sub sub ( // Outputs .osizedreg (osizedreg[7:0]), diff --git a/test_regress/t/t_inst_v2k_sub.vi b/test_regress/t/t_inst_v2k__sub.vi similarity index 95% rename from test_regress/t/t_inst_v2k_sub.vi rename to test_regress/t/t_inst_v2k__sub.vi index 631e42489..ac75409db 100644 --- a/test_regress/t/t_inst_v2k_sub.vi +++ b/test_regress/t/t_inst_v2k__sub.vi @@ -5,7 +5,7 @@ // without warranty, 2003 by Wilson Snyder. // This file is named .vi to test +libext+ flags. -module t_inst_v2k_sub +module t_inst_v2k__sub ( output reg [7:0] osizedreg, output wire oonewire /*verilator public*/,