Fix missing assignment for wide class members. (#4267)

src/V3EmitCFunc.h

@@ -354,6 +354,7 @@ public:
                    && !VN_IS(nodep->rhsp(), CMethodHard)  //
                    && !VN_IS(nodep->rhsp(), VarRef)  //
                    && !VN_IS(nodep->rhsp(), AssocSel)  //
+                   && !VN_IS(nodep->rhsp(), MemberSel)  //
                    && !VN_IS(nodep->rhsp(), StructSel)  //
                    && !VN_IS(nodep->rhsp(), ArraySel)) {
             // Wide functions assign into the array directly, don't need separate assign statement

test_regress/t/t_class_wide.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_class_wide.v

@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Jomit626.
+// SPDX-License-Identifier: CC0-1.0
+
+`ifndef WIDTH
+`define WIDTH 128
+`endif
+
+class item;
+    bit [`WIDTH-1:0] data;
+endclass
+
+module t ();
+    logic [`WIDTH-1:0] data;
+    item item0 = new;
+
+    initial begin
+        item0.data = `WIDTH'hda7ada7a;
+        data = item0.data;
+
+        if (data != `WIDTH'hda7ada7a)
+            $stop();
+
+        $write("*-* All Finished *-*\n");
+        $finish();
+    end
+endmodule