luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix emitv 

Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
This commit is contained in:
Bartłomiej Chmiel 2025-11-06 10:55:17 +01:00
parent 129ccb44ae
commit 459333d835
No known key found for this signature in database
GPG Key ID: AF7A8DBF070764A4
2 changed files with 0 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
test_regress/t/t_debug_emitv.out
View File

@ -366,9 +366,6 @@ module Vt_debug_emitv_t;
property p1; property p1;
@( clk) sum[0] @( clk) sum[0]
endproperty endproperty
property p2;
@(posedge clk) disable iff (cyc == 'sh1) ##1 sum[0]
endproperty
assert property (@( clk) (! ##1 in) assert property (@( clk) (! ##1 in)
) begin ) begin
end end

3
test_regress/t/t_debug_emitv.v
View File

@ -277,9 +277,6 @@ module t (/*AUTOARG*/
property p1; property p1;
@(clk) sum[0] @(clk) sum[0]
endproperty endproperty
property p2;
@(posedge clk) disable iff (cyc == 1) ##1 sum[0]
endproperty
assert property (@(clk) not ##1 in); assert property (@(clk) not ##1 in);