diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out
index b2ef88fc7..e09dc1e14 100644
--- a/test_regress/t/t_debug_emitv.out
+++ b/test_regress/t/t_debug_emitv.out
@@ -366,9 +366,6 @@ module Vt_debug_emitv_t;
     property p1;
     @( clk) sum[0]
     endproperty
-    property p2;
-    @(posedge clk) disable iff (cyc == 'sh1) ##1 sum[0]
-    endproperty
     assert property (@( clk) (! ##1 in)
     ) begin
     end
diff --git a/test_regress/t/t_debug_emitv.v b/test_regress/t/t_debug_emitv.v
index ec7cad63a..e7915f47d 100644
--- a/test_regress/t/t_debug_emitv.v
+++ b/test_regress/t/t_debug_emitv.v
@@ -277,9 +277,6 @@ module t (/*AUTOARG*/
    property p1;
       @(clk) sum[0]
    endproperty
-   property p2;
-      @(posedge clk) disable iff (cyc == 1) ##1 sum[0]
-   endproperty
 
    assert property (@(clk) not ##1 in);