Add +verilator+assert+lock to ignore RTL assert control statements (#8086)

Co-authored-by: Sumanth Kadiyala <[email protected]>

test_regress/t/t_assert_ctl_arg.cpp

@@ -138,8 +138,34 @@ void verilatedTest() {
     contextp->assertCtl(FAIL_ON, TYPE, DIRECTIVE);
     TEST_CHECK_NZ(contextp->assertCtlGet(Query::ASSERT_CTL_FAIL_ON, TYPE, DIRECTIVE));
 }
+
+void verilatedLockedTest() {
+    // With +verilator+assert+lock, every assertion-control update is a no-op
+    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+
+    // Clear some bits to test assertOnSet
+    contextp->assertOnClear(2, 3);
+    const char* argsp[] = {"+verilator+assert+lock"};
+    contextp->commandArgsAdd(1, argsp);
+    TEST_CHECK_EQ(contextp->assertCtlsLocked(), true);
+
+    // Validate each assert control API call is a no-op
+    contextp->assertOn(false);
+    TEST_CHECK_NZ(contextp->assertOn());
+
+    contextp->assertOnSet(2, 3);
+    TEST_CHECK_Z(contextp->assertOnGet(2, 3));
+
+    contextp->assertOnClear(1, 1);
+    TEST_CHECK_NZ(contextp->assertOnGet(1, 1));
+
+    contextp->assertCtl(4, 4, 1);
+    TEST_CHECK_NZ(contextp->assertOnGet(4, 1));
+}
+
 int main(int argc, char** argv) {
     verilatedTest();
+    verilatedLockedTest();
     if (errors) return 10;
 
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};

test_regress/t/t_assert_ctl_lock_arg.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=["--binary --assert"])
+
+test.execute(all_run_flags=["+verilator+assert+lock"])
+
+test.passes()

test_regress/t/t_assert_ctl_lock_arg.v

@@ -0,0 +1,70 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+// Run with +verilator+assert+lock, which freezes the enabled assertions, so
+// every assertion control below is ignored and all directives keep firing.
+
+// verilog_format: off
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+// verilog_format: on
+
+`ifdef T_ASSERT_CTL_LOCK_ARG_NOASSERT
+`define ctl_on_off 3  // On, ignored as the assertions stay disabled
+`define expected 0
+`else
+`define ctl_on_off 4  // Off, ignored as the assertions stay enabled
+`define expected 10
+`endif
+
+module t;
+  logic clk = 0;
+  logic fals = 1'b0;
+
+  int imm_fails = 0;
+  int conc_fails = 0;
+  int assume_fails = 0;
+  int ctl;
+
+  always #5 clk = ~clk;
+
+  // posedge clk at t = 5, 15, 25, 35, 45, 55, 65, 75, 85, 95
+  always @(posedge clk) imm_assert : assert (fals) else imm_fails = imm_fails + 1;
+
+  conc_assert : assert property (@(posedge clk) fals) else conc_fails = conc_fails + 1;
+
+  conc_assume : assume property (@(posedge clk) fals) else assume_fails = assume_fails + 1;
+
+  initial begin
+    #6;  // t=6
+    $assertcontrol(`ctl_on_off);  // On or Off, whichever would flip all types
+    #10;  // t=16
+    $assertcontrol(`ctl_on_off, 2);  // Same, but only for SIMPLE_IMMEDIATE
+    #10;  // t=26
+    $assertcontrol(1);  // Lock
+    $assertcontrol(2);  // Unlock
+    #10;  // t=36
+    $assertcontrol(5);  // Kill
+    #10;  // t=46
+    $assertpassoff;
+    $assertfailoff;
+    #10;  // t=56
+    ctl = `ctl_on_off;
+    $assertcontrol(ctl);  // Same again, via a non-constant control_type
+    #10;  // t=66
+    $assertkill;
+    #34;  // t=100
+    $finish;
+  end
+
+  // Every directive kept the enabled state it started with, as no control
+  // above took effect
+  final begin
+    `checkd(imm_fails, `expected);
+    `checkd(conc_fails, `expected);
+    `checkd(assume_fails, `expected);
+    $write("*-* All Finished *-*\n");
+  end
+endmodule

test_regress/t/t_assert_ctl_lock_arg_noassert.py

@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t_assert_ctl_lock_arg.v"
+
+test.compile(
+    verilator_flags2=["--binary --assert +define+T_ASSERT_CTL_LOCK_ARG_NOASSERT"])
+
+test.execute(all_run_flags=["+verilator+noassert", "+verilator+assert+lock"])
+
+# Same result with the arguments in the opposite order
+test.execute(all_run_flags=["+verilator+assert+lock", "+verilator+noassert"])
+
+test.passes()