luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Internals: Remove dupliacte netSig parse rules

This commit is contained in:
Geza Lore 2025-10-01 10:46:55 +01:00
parent 4d518873d0
commit 435e1149d5
1 changed files with 2 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/verilog.y
View File

@ -2969,17 +2969,9 @@ netSigList<varp>: // IEEE: list_of_port_identifiers
;
netSig<varp>: // IEEE: net_decl_assignment - one element from list_of_port_identifiers
netId sigAttrListE
{ $$ = VARDONEA($<fl>1, *$1, nullptr, $2); }
| netId sigAttrListE '=' expr
{ $$ = VARDONEA($<fl>1, *$1, nullptr, $2);
AstDelay* const delayp = $$->delayp() ? $$->delayp()->unlinkFrBack() : nullptr;
AstAssignW* const assignp = new AstAssignW{$3, new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1}, $4, delayp};
if (GRAMMARP->m_netStrengthp) assignp->strengthSpecp(GRAMMARP->m_netStrengthp->cloneTree(false));
AstNode::addNext<AstNode, AstNode>($$, assignp); }
| netId variable_dimensionList sigAttrListE
netId variable_dimensionListE sigAttrListE
{ $$ = VARDONEA($<fl>1, *$1, $2, $3); }
| netId variable_dimensionList sigAttrListE '=' expr
| netId variable_dimensionListE sigAttrListE '=' expr
{ $$ = VARDONEA($<fl>1, *$1, $2, $3);
AstDelay* const delayp = $$->delayp() ? $$->delayp()->unlinkFrBack() : nullptr;
AstAssignW* const assignp = new AstAssignW{$4, new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1}, $5, delayp};