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Fix * with filenames < 8 characters 

git-svn-id: file://localhost/svn/verilator/trunk/verilator@859 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2006-12-21 15:28:32 +00:00
parent dc6a164e01
commit 42883e7b6a
5 changed files with 35 additions and 23 deletions
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2
Changes
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@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
Verilator no longer accepts duplicated variables inside unique
generate blocks as this is illegal according to the specification.
**** Fix $readmem* with filenames < 8 characters. [Emerson Suguimoto]
* Verilator 3.630 12/19/2006
** Support $readmemb and $readmemh. [Eugene Weber, Arthur Kahlich]

4
include/verilated.cpp
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@ -242,7 +242,7 @@ QData VL_FOPEN_WI(int fnwords, WDataInP filenamep, IData mode) {
void VL_READMEM_Q(bool hex, int width, int depth, int array_lsb, int,
QData ofilename, void* memp, IData start, IData end) {
IData fnw[2]; VL_SET_WQ(fnw, ofilename);
return VL_READMEM_W(hex,2,width,depth,array_lsb, fnw,memp,start,end);
return VL_READMEM_W(hex,width,depth,array_lsb,2, fnw,memp,start,end);
}
void VL_READMEM_W(bool hex, int width, int depth, int array_lsb, int fnwords,
@ -257,7 +257,7 @@ void VL_READMEM_W(bool hex, int width, int depth, int array_lsb, int fnwords,
}
// Prep for reading
IData addr = start;
int linenum = 0;
int linenum = 1;
bool innum = false;
bool ignore_to_eol = false;
bool ignore_to_cmt = false;

6
src/V3EmitC.cpp
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@ -239,11 +239,13 @@ public:
emitIQW(nodep->modep());
if (nodep->modep()->width()>4*8) nodep->modep()->v3error("$fopen mode should be <= 4 characters");
puts("(");
if (nodep->filenamep()->isWide()) puts(cvtToStr(nodep->filenamep()->widthWords()));
if (nodep->filenamep()->isWide()) {
puts(cvtToStr(nodep->filenamep()->widthWords()));
putbs(", ");
}
if (nodep->filenamep()->widthWords() > VL_TO_STRING_MAX_WORDS) {
nodep->v3error("String of "<<nodep->filenamep()->width()<<" bits exceeds hardcoded limit VL_TO_STRING_MAX_WORDS in verilatedos.h\n");
}
putbs(", ");
nodep->filenamep()->iterateAndNext(*this);
putbs(", ");
nodep->modep()->iterateAndNext(*this);

6
test_regress/t/t_sys_file.v
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@ -32,6 +32,12 @@ module t;
if (|file) $stop; // Should not exist, IE must return 0
end
begin
// Check quadword access; a little strange, but it's legal to open "."
file = $fopen(".","r");
$fclose(file);
end
$write("*-* All Finished *-*\n");
$finish;
end

40
test_regress/t/t_sys_readmem_b_8.mem
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@ -1,19 +1,21 @@
// $Id$
// DESCRIPTION: Verilator: Verilog Test data file
//
// Copyright 2006 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// General Public License or the Perl Artistic License.
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/*
multi line
ignored
*/
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// $Id$
// DESCRIPTION: Verilator: Verilog Test data file
//
// Copyright 2006 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// General Public License or the Perl Artistic License.
// ** Note this file has DOS CR's so we can test them!
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/*
multi line
ignored
*/
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