luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Tests: Update static test.

This commit is contained in:
Wilson Snyder 2020-04-19 20:10:07 -04:00
parent 39d903375b
commit 4272f2116e
1 changed files with 49 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

69
test_regress/t/t_var_static.v
View File

@ -4,6 +4,8 @@
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
@ -42,29 +44,56 @@ module t (/*AUTOARG*/
endfunction
initial begin
if (f_no_no() != 3) $stop;
if (f_no_no() != 4) $stop;
if (f_no_st() != 3) $stop;
if (f_no_st() != 4) $stop;
if (f_no_au() != 3) $stop;
if (f_no_au() != 3) $stop;
`checkh(f_no_no(), 3);
`checkh(f_no_no(), 4);
`checkh(f_no_st(), 3);
`checkh(f_no_st(), 4);
`checkh(f_no_au(), 3);
`checkh(f_no_au(), 3);
//
if (f_st_no() != 3) $stop;
if (f_st_no() != 4) $stop;
if (f_st_st() != 3) $stop;
if (f_st_st() != 4) $stop;
if (f_st_au() != 3) $stop;
if (f_st_au() != 3) $stop;
`checkh(f_st_no(), 3);
`checkh(f_st_no(), 4);
`checkh(f_st_st(), 3);
`checkh(f_st_st(), 4);
`checkh(f_st_au(), 3);
`checkh(f_st_au(), 3);
//
if (f_au_no() != 3) $stop;
if (f_au_no() != 3) $stop;
if (f_au_st() != 3) $stop;
if (f_au_st() != 4) $stop;
if (f_au_au() != 3) $stop;
if (f_au_au() != 3) $stop;
`checkh(f_au_no(), 3);
`checkh(f_au_no(), 3);
`checkh(f_au_st(), 3);
`checkh(f_au_st(), 4);
`checkh(f_au_au(), 3);
`checkh(f_au_au(), 3);
//
$write("*-* All Finished *-*\n");
$finish;
end
int cyc = 0;
always @ (posedge clk) begin
int ist1;
static int ist2;
automatic int iau3;
cyc <= cyc + 1;
if (cyc == 0) begin
ist1 = 10;
ist2 = 20;
iau3 = 30;
`checkh(ist1, 10);
`checkh(ist2, 20);
`checkh(iau3, 30);
++ist1;
++ist2;
++iau3;
end
else if (cyc == 1) begin
`checkh(ist1, 11);
`checkh(ist2, 21);
`checkh(iau3, 30);
end
else if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule