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Join test cases

This commit is contained in:
wsxarcher 2026-03-24 22:35:49 +01:00
parent d4c848e8ac
commit 400da26f2e
110 changed files with 617 additions and 2918 deletions
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9
test_regress/t/t_trace_dumpvars.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

352
test_regress/t/t_trace_dumpvars.v
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@ -6,33 +6,379 @@
`define STRINGIFY(x) `"x`"
module t(
/* verilator lint_off MULTITOP */
`ifdef TRACE_DUMPVARS_CASE_HIER_STRUCT
`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT
`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT2
`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
`endif
`ifdef TRACE_DUMPVARS_CASE_HIER_ARRAY
`define TRACE_DUMPVARS_ARRAY_BRANCH
`elsif TRACE_DUMPVARS_CASE_HIER_ARRAY_OOB
`define TRACE_DUMPVARS_ARRAY_BRANCH
`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY
`define TRACE_DUMPVARS_ARRAY_BRANCH
`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY_OOB
`define TRACE_DUMPVARS_ARRAY_BRANCH
`endif
`ifdef TRACE_DUMPVARS_CASE_FUNC
`define TRACE_DUMPVARS_TASK_BRANCH
`elsif TRACE_DUMPVARS_CASE_TASK
`define TRACE_DUMPVARS_TASK_BRANCH
`elsif TRACE_DUMPVARS_CASE_TASK2
`define TRACE_DUMPVARS_TASK_BRANCH
`endif
`ifdef TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
typedef struct packed {
logic [31:0] add;
logic [31:0] cyc;
logic [31:0] inner;
} deep_t;
typedef struct packed {
deep_t deep;
logic [31:0] value;
} top_t;
`endif
`ifdef TRACE_DUMPVARS_TASK_BRANCH
function int get_trace_level;
return 1;
endfunction
function void varsdump;
$dumpvars(get_trace_level());
endfunction
`ifdef TRACE_DUMPVARS_CASE_FUNC
function void setup_trace;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
varsdump();
endfunction
`else
task setup_trace;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
varsdump();
endtask
`endif
`ifdef TRACE_DUMPVARS_CASE_TASK2
task setup_trace_nested;
setup_trace();
endtask
`endif
`endif
module t
`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE
;
`else
(
input clk
);
`endif
int cyc;
`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE
logic clk;
`endif
`ifdef TRACE_DUMPVARS_CASE_CONTEXT
int top;
`endif
`ifdef TRACE_DUMPVARS_CASE_WIRE
int counter;
`endif
`ifdef TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
top_t mystruct;
`endif
`ifdef TRACE_DUMPVARS_CASE_STRUCT
typedef struct packed {
logic [7:0] \x ;
logic [7:0] y;
} point_t;
typedef struct packed {
point_t origin;
point_t size;
} rect_t;
rect_t rect;
point_t \pt ;
`endif
`ifdef TRACE_DUMPVARS_ARRAY_BRANCH
sub #(10) arr[2](.*);
`elsif TRACE_DUMPVARS_CASE_GEN
genvar i;
generate
for (i = 0; i < 2; i = i + 1) begin : gen_sub
sub #(10 * (i + 1)) sub_i(.*);
end
endgenerate
`elsif TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
`elsif TRACE_DUMPVARS_CASE_STRUCT
sub #(10) sub_a(.*);
`else
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
`endif
`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE
initial begin
clk = 0;
forever #1 clk = !clk;
end
`endif
always @(posedge clk) begin
cyc <= cyc + 1;
`ifdef TRACE_DUMPVARS_CASE_STRUCT
\pt .\x <= \pt .\x + 1;
\pt .y <= \pt .y + 2;
rect.origin.\x <= rect.origin.\x + 1;
rect.origin.y <= rect.origin.y + 2;
rect.size.\x <= 8'd100;
rect.size.y <= 8'd200;
`endif
`ifdef TRACE_DUMPVARS_CASE_WIRE
counter <= counter + 2;
`endif
`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE
if (cyc == 1) begin
$dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx1.vcd"});
$dumpvars(0, sub_b);
end
`endif
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE
initial begin
$dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx0.vcd"});
$dumpvars(1, sub_a);
end
`elsif TRACE_DUMPVARS_CASE_STRUCT
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
$dumpvars(0);
$dumpvars(1, rect.origin.\x );
$dumpvars(1, \pt .\y );
end
`elsif TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
`ifdef TRACE_DUMPVARS_CASE_HIER_STRUCT
$dumpvars(1, t.mystruct.deep);
`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT
$dumpvars(1, cpptop.t.mystruct.deep);
`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT2
$dumpvars(1, cpptop.t.mystruct.deep.inner);
`else
`error "Missing packed struct trace_dumpvars case"
`endif
end
always_comb begin
mystruct.value = cyc + 32'd10;
mystruct.deep.add = 32'd11;
mystruct.deep.cyc = cyc;
mystruct.deep.inner = cyc + mystruct.deep.add;
end
`elsif TRACE_DUMPVARS_ARRAY_BRANCH
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
`ifdef TRACE_DUMPVARS_CASE_HIER_ARRAY
$dumpvars(1, t.arr[1].deep);
`elsif TRACE_DUMPVARS_CASE_HIER_ARRAY_OOB
$dumpvars(1, t.arr[999].deep);
`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY
$dumpvars(1, cpptop.t.arr[1].deep);
`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY_OOB
$dumpvars(1, cpptop.t.arr[999].deep);
`else
`error "Missing array trace_dumpvars case"
`endif
end
`elsif TRACE_DUMPVARS_CASE_GEN
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
$dumpvars(0, gen_sub[0]);
end
`elsif TRACE_DUMPVARS_TASK_BRANCH
`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL
`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK
`elsif TRACE_DUMPVARS_CASE_NONCONST_SCOPE
initial begin: dumpblock
int level;
if (!$value$plusargs("LEVEL=%d", level)) level = 0;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
$dumpvars(level, t.sub_a);
end
`elsif TRACE_DUMPVARS_CASE_SUB
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
end
`elsif TRACE_DUMPVARS_CASE_SUB0
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
end
`else
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
`ifdef TRACE_DUMPVARS_CASE_BASE
$dumpvars(0);
`elsif TRACE_DUMPVARS_CASE_SCOPE
$dumpvars(0, sub_a);
`elsif TRACE_DUMPVARS_CASE_MULTI_SCOPE
$dumpvars(0+1, t, t.sub_a.deep_i);
`elsif TRACE_DUMPVARS_CASE_ABS_SCOPE
$dumpvars(0, t.sub_a);
`elsif TRACE_DUMPVARS_CASE_OVERRIDE
$dumpvars(1, t.sub_a.deep_i);
$dumpvars(0);
`elsif TRACE_DUMPVARS_CASE_CONTEXT
$dumpvars(1, t.sub_a.deep_i);
$dumpvars(0, top);
`elsif TRACE_DUMPVARS_CASE_LEVEL
$dumpvars(1);
`elsif TRACE_DUMPVARS_CASE_LEVEL_SCOPE
$dumpvars(1, sub_a);
`elsif TRACE_DUMPVARS_CASE_HIER_SCOPE
$dumpvars(1, sub_a.deep_i);
`elsif TRACE_DUMPVARS_CASE_WIRE
$dumpvars(0, cyc, counter);
`elsif TRACE_DUMPVARS_CASE_T
$dumpvars(t);
`elsif TRACE_DUMPVARS_CASE_MISSING_SCOPE
$dumpvars(0, missing_module);
`elsif TRACE_DUMPVARS_CASE_MISSING2
$dumpvars(t.missingname);
`elsif TRACE_DUMPVARS_CASE_MISSING3
$dumpvars(0, t.missing);
`elsif TRACE_DUMPVARS_CASE_MISSING4
$dumpvars(0, t.sub_a.missing);
`elsif TRACE_DUMPVARS_CASE_MISSING5
$dumpvars(0, missing.child);
`elsif TRACE_DUMPVARS_CASE_CPPTOP
$dumpvars(0, cpptop, cpptop.t);
`elsif TRACE_DUMPVARS_CASE_CPPTOP2
$dumpvars(0, cpptop, cpptop.notfound);
`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING
$dumpvars(0, missing_module);
`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING2
$dumpvars(t.missingname);
`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING3
$dumpvars(0, t.missing);
`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING4
$dumpvars(0, t.sub_a.missing);
`else
`error "Missing trace_dumpvars case define"
`endif
end
`endif
endmodule
module sub #(
parameter int ADD
parameter int ADD = 0
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK
function void dump_from_func;
$dumpvars(1, t);
endfunction
task setup_trace;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
dump_from_func();
endtask
`endif
`ifdef TRACE_DUMPVARS_ARRAY_BRANCH
deep #(ADD + 1) deep(.*);
`elsif TRACE_DUMPVARS_CASE_BASE
`elsif TRACE_DUMPVARS_CASE_WIRE
`elsif TRACE_DUMPVARS_CASE_CPPTOP
`elsif TRACE_DUMPVARS_CASE_CPPTOP2
`elsif TRACE_DUMPVARS_CASE_STRUCT
`else
deep #(ADD + 1) deep_i(.*);
`endif
`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
$dumpvars(1, t);
end
`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK
initial begin
setup_trace();
end
`elsif TRACE_DUMPVARS_CASE_TASK2
initial begin
setup_trace_nested;
end
`elsif TRACE_DUMPVARS_TASK_BRANCH
initial begin
setup_trace;
end
`elsif TRACE_DUMPVARS_CASE_SUB
initial begin
$dumpvars(1);
end
`elsif TRACE_DUMPVARS_CASE_SUB0
initial begin
$dumpvars(0);
end
`endif
endmodule
module deep #(
parameter int ADD = 0
)(
input int cyc
);
int inner;
`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL
int t;
`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK
int t;
`endif
always_comb inner = cyc + ADD;
`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK
function void dump_from_func;
$dumpvars(1, t);
endfunction
task setup_trace;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
dump_from_func();
endtask
initial begin
setup_trace();
end
`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
$dumpvars(1, t);
end
`elsif TRACE_DUMPVARS_CASE_CONTEXT
initial begin
$dumpvars(0);
end
`endif
endmodule
/* verilator lint_on MULTITOP */

9
test_regress/t/t_trace_dumpvars_abs_scope.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_abs_scope.v
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@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with absolute hierarchical scope path
$dumpvars(0, t.sub_a);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

10
test_regress/t/t_trace_dumpvars_add_module.py
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@ -8,14 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --timing --trace-vcd'])
test.execute()
test.vcd_identical(test.obj_dir + '/simx0.vcd', test.t_dir + '/t_trace_dumpvars_add_module_0.out')
test.vcd_identical(test.obj_dir + '/simx1.vcd', test.t_dir + '/t_trace_dumpvars_add_module_1.out')
test.passes()
trace_dumpvars_common.run(test)

58
test_regress/t/t_trace_dumpvars_add_module.v
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@ -1,58 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
);
logic clk;
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
initial begin
clk = 0;
forever #1 clk = !clk;
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1) begin
$dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx1.vcd"});
$dumpvars(0, sub_b);
end
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx0.vcd"});
$dumpvars(1, sub_a);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_context.py
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@ -8,14 +8,9 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

57
test_regress/t/t_trace_dumpvars_context.v
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@ -1,57 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
int top;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// First restrict to sub_a.deep_i only, then let deep_i issue $dumpvars(0)
// to confirm the no-target override still expands tracing globally.
$dumpvars(1, t.sub_a.deep_i);
$dumpvars(0, top);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
initial begin
$dumpvars(0);
end
endmodule

16
test_regress/t/t_trace_dumpvars_cpptop.py
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@ -8,20 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
't/t_trace_dumpvars_cpptop.cpp',
])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

39
test_regress/t/t_trace_dumpvars_cpptop.v
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@ -1,39 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// cpptop is defined in the C++ testbench as the root of the trace hierarchy, so $dumpvars(0, cpptop) should dump everything.
$dumpvars(0, cpptop, cpptop.t);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
endmodule

36
test_regress/t/t_trace_dumpvars_cpptop2.cpp
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@ -1,36 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <memory>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return (double)main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::traceEverOn(true);
Verilated::commandArgs(argc, argv);
// Name the top module "cpptop" instead of default "TOP"
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
top->clk = 0;
while (!Verilated::gotFinish()) {
top->eval();
++main_time;
top->clk = !top->clk;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

4
test_regress/t/t_trace_dumpvars_cpptop2.out
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@ -1,5 +1,5 @@
%Error: t/t_trace_dumpvars_cpptop2.v:27:5: $dumpvars target not found: cpptop.notfound
27 | $dumpvars(0, cpptop, cpptop.notfound);
%Error: t/t_trace_dumpvars.v:272:5: $dumpvars target not found: cpptop.notfound
272 | $dumpvars(0, cpptop, cpptop.notfound);
| ^~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

14
test_regress/t/t_trace_dumpvars_cpptop2.py
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@ -8,18 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
fails=True,
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
't/t_trace_dumpvars_cpptop.cpp',
],
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

38
test_regress/t/t_trace_dumpvars_cpptop2.v
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@ -1,38 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
$dumpvars(0, cpptop, cpptop.notfound);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
endmodule

36
test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp
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@ -1,36 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <memory>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return (double)main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::traceEverOn(true);
Verilated::commandArgs(argc, argv);
// Name the top module "cpptop" instead of default "TOP"
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
top->clk = 0;
while (!Verilated::gotFinish()) {
top->eval();
++main_time;
top->clk = !top->clk;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

16
test_regress/t/t_trace_dumpvars_cpptop_hier_array.py
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@ -8,20 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
't/t_trace_dumpvars_cpptop_hier_array.cpp',
])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

49
test_regress/t/t_trace_dumpvars_cpptop_hier_array.v
View File

@ -1,49 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) arr[2](.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with an arrayed hierarchical scope path via cpptop.
$dumpvars(1, cpptop.t.arr[1].deep);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

36
test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp
View File

@ -1,36 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <memory>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return (double)main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::traceEverOn(true);
Verilated::commandArgs(argc, argv);
// Name the top module "cpptop" instead of default "TOP"
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
top->clk = 0;
while (!Verilated::gotFinish()) {
top->eval();
++main_time;
top->clk = !top->clk;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

16
test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py
View File

@ -8,20 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
't/t_trace_dumpvars_cpptop_hier_array_oob.cpp',
])
test.execute()
test.files_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

49
test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v
View File

@ -1,49 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) arr[2](.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with an out-of-range array index via cpptop.
$dumpvars(1, cpptop.t.arr[999].deep);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

36
test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp
View File

@ -1,36 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <memory>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return (double)main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::traceEverOn(true);
Verilated::commandArgs(argc, argv);
// Name the top module "cpptop" instead of default "TOP"
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
top->clk = 0;
while (!Verilated::gotFinish()) {
top->eval();
++main_time;
top->clk = !top->clk;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

14
test_regress/t/t_trace_dumpvars_cpptop_hier_global.py
View File

@ -8,18 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
't/t_trace_dumpvars_cpptop_hier_global.cpp',
])
test.execute()
test.passes()
trace_dumpvars_common.run(test)

56
test_regress/t/t_trace_dumpvars_cpptop_hier_global.v
View File

@ -1,56 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with hierarchical scope: level 1 limits to direct signals of t outside the scope
$dumpvars(1, t);
end
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
int t;
always_comb inner = cyc + ADD;
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
$dumpvars(1, t);
end
endmodule

36
test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp
View File

@ -1,36 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <memory>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return (double)main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::traceEverOn(true);
Verilated::commandArgs(argc, argv);
// Name the top module "cpptop" instead of default "TOP"
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
top->clk = 0;
while (!Verilated::gotFinish()) {
top->eval();
++main_time;
top->clk = !top->clk;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

17
test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py
View File

@ -8,21 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
'--trace-structs',
't/t_trace_dumpvars_cpptop_hier_struct.cpp',
])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

46
test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v
View File

@ -1,46 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
typedef struct packed {
logic [31:0] add;
logic [31:0] cyc;
logic [31:0] inner;
} deep_t;
typedef struct packed {
deep_t deep;
logic [31:0] value;
} top_t;
module t(
input clk
);
int cyc;
top_t mystruct;
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with a traced struct sub-scope via cpptop.
$dumpvars(1, cpptop.t.mystruct.deep);
end
always_comb begin
mystruct.value = cyc + 32'd10;
mystruct.deep.add = 32'd11;
mystruct.deep.cyc = cyc;
mystruct.deep.inner = cyc + mystruct.deep.add;
end
endmodule

36
test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp
View File

@ -1,36 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <memory>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return (double)main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::traceEverOn(true);
Verilated::commandArgs(argc, argv);
// Name the top module "cpptop" instead of default "TOP"
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
top->clk = 0;
while (!Verilated::gotFinish()) {
top->eval();
++main_time;
top->clk = !top->clk;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

15
test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py
View File

@ -8,19 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
'--trace-structs',
't/t_trace_dumpvars_cpptop_hier_struct2.cpp',
])
test.execute()
test.passes()
trace_dumpvars_common.run(test)

46
test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v
View File

@ -1,46 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
typedef struct packed {
logic [31:0] add;
logic [31:0] cyc;
logic [31:0] inner;
} deep_t;
typedef struct packed {
deep_t deep;
logic [31:0] value;
} top_t;
module t(
input clk
);
int cyc;
top_t mystruct;
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with a struct leaf member via cpptop.
$dumpvars(1, cpptop.t.mystruct.deep.inner);
end
always_comb begin
mystruct.value = cyc + 32'd10;
mystruct.deep.add = 32'd11;
mystruct.deep.cyc = cyc;
mystruct.deep.inner = cyc + mystruct.deep.add;
end
endmodule

36
test_regress/t/t_trace_dumpvars_cpptop_missing.cpp
View File

@ -1,36 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <memory>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return (double)main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::traceEverOn(true);
Verilated::commandArgs(argc, argv);
// Name the top module "cpptop" instead of default "TOP"
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
top->clk = 0;
while (!Verilated::gotFinish()) {
top->eval();
++main_time;
top->clk = !top->clk;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

2
test_regress/t/t_trace_dumpvars_cpptop_missing.out
View File

@ -1,2 +1,2 @@
%Error: t/t_trace_dumpvars_cpptop_missing.v:28: $dumpvars target not found: missing_module
%Error: t/t_trace_dumpvars.v:274: $dumpvars target not found: missing_module
Aborting...

15
test_regress/t/t_trace_dumpvars_cpptop_missing.py
View File

@ -8,19 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
't/t_trace_dumpvars_cpptop_missing.cpp',
])
test.execute(fails=True,
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_cpptop_missing.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with a non-existent module scope argument via cpptop.
$dumpvars(0, missing_module);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

36
test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp
View File

@ -1,36 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <memory>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return (double)main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::traceEverOn(true);
Verilated::commandArgs(argc, argv);
// Name the top module "cpptop" instead of default "TOP"
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
top->clk = 0;
while (!Verilated::gotFinish()) {
top->eval();
++main_time;
top->clk = !top->clk;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

4
test_regress/t/t_trace_dumpvars_cpptop_missing2.out
View File

@ -1,5 +1,5 @@
%Error: t/t_trace_dumpvars_cpptop_missing2.v:28:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname'
28 | $dumpvars(t.missingname);
%Error: t/t_trace_dumpvars.v:276:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname'
276 | $dumpvars(t.missingname);
| ^~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

14
test_regress/t/t_trace_dumpvars_cpptop_missing2.py
View File

@ -8,18 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
fails=True,
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
't/t_trace_dumpvars_cpptop_missing2.cpp',
],
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_cpptop_missing2.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with a hierarchical non-existent scope argument via cpptop.
$dumpvars(t.missingname);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

36
test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp
View File

@ -1,36 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <memory>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return (double)main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::traceEverOn(true);
Verilated::commandArgs(argc, argv);
// Name the top module "cpptop" instead of default "TOP"
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
top->clk = 0;
while (!Verilated::gotFinish()) {
top->eval();
++main_time;
top->clk = !top->clk;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

2
test_regress/t/t_trace_dumpvars_cpptop_missing3.out
View File

@ -1,2 +1,2 @@
%Error: t/t_trace_dumpvars_cpptop_missing3.v:28: $dumpvars target not found: t.missing
%Error: t/t_trace_dumpvars.v:278: $dumpvars target not found: t.missing
Aborting...

15
test_regress/t/t_trace_dumpvars_cpptop_missing3.py
View File

@ -8,19 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
't/t_trace_dumpvars_cpptop_missing3.cpp',
])
test.execute(fails=True,
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_cpptop_missing3.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with level and hierarchical non-existent scope via cpptop.
$dumpvars(0, t.missing);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

36
test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp
View File

@ -1,36 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
#include <verilated.h>
#include <memory>
#include VM_PREFIX_INCLUDE
unsigned long long main_time = 0;
double sc_time_stamp() { return (double)main_time; }
int main(int argc, char** argv) {
Verilated::debug(0);
Verilated::traceEverOn(true);
Verilated::commandArgs(argc, argv);
// Name the top module "cpptop" instead of default "TOP"
std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
top->clk = 0;
while (!Verilated::gotFinish()) {
top->eval();
++main_time;
top->clk = !top->clk;
}
top->final();
top.reset();
printf("*-* All Finished *-*\n");
return 0;
}

2
test_regress/t/t_trace_dumpvars_cpptop_missing4.out
View File

@ -1,2 +1,2 @@
%Error: t/t_trace_dumpvars_cpptop_missing4.v:28: $dumpvars target not found: t.sub_a.missing
%Error: t/t_trace_dumpvars.v:280: $dumpvars target not found: t.sub_a.missing
Aborting...

15
test_regress/t/t_trace_dumpvars_cpptop_missing4.py
View File

@ -8,19 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(
make_main=False,
verilator_flags2=[
'--cc',
'--exe',
'--trace-vcd',
't/t_trace_dumpvars_cpptop_missing4.cpp',
])
test.execute(fails=True,
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_cpptop_missing4.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with a valid sub-scope but missing child via cpptop.
$dumpvars(0, t.sub_a.missing);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_func.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

61
test_regress/t/t_trace_dumpvars_func.v
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@ -1,61 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
function int get_trace_level;
return 1;
endfunction
function void varsdump;
$dumpvars(get_trace_level());
endfunction
function void setup_trace;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
varsdump();
endfunction
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
initial begin
setup_trace;
end
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_gen.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

55
test_regress/t/t_trace_dumpvars_gen.v
View File

@ -1,55 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
// Generate block creates sub instances with named block scope
genvar i;
generate
for (i = 0; i < 2; i = i + 1) begin : gen_sub
sub #(10 * (i + 1)) sub_i(.*);
end
endgenerate
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Dump only gen_sub[0] and everything below it
$dumpvars(0, gen_sub[0]);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_hier_array.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

49
test_regress/t/t_trace_dumpvars_hier_array.v
View File

@ -1,49 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) arr[2](.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with an arrayed hierarchical scope path.
$dumpvars(1, t.arr[1].deep);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

7
test_regress/t/t_trace_dumpvars_hier_array_oob.py
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@ -8,11 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.passes()
trace_dumpvars_common.run(test)

49
test_regress/t/t_trace_dumpvars_hier_array_oob.v
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@ -1,49 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) arr[2](.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with an out-of-range array index.
$dumpvars(1, t.arr[999].deep);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_hier_global.py
View File

@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

56
test_regress/t/t_trace_dumpvars_hier_global.v
View File

@ -1,56 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with hierarchical scope: level 1 limits to direct signals of t outside the scope
$dumpvars(1, t);
end
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
int t;
always_comb inner = cyc + ADD;
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
$dumpvars(1, t);
end
endmodule

9
test_regress/t/t_trace_dumpvars_hier_global_task.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd --fno-inline'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

71
test_regress/t/t_trace_dumpvars_hier_global_task.v
View File

@ -1,71 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
function void dump_from_func;
$dumpvars(1, t);
endfunction
task setup_trace;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
dump_from_func();
endtask
deep #(ADD + 1) deep_i(.*);
initial begin
setup_trace();
end
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
int t;
always_comb inner = cyc + ADD;
function void dump_from_func;
$dumpvars(1, t);
endfunction
task setup_trace;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
dump_from_func();
endtask
initial begin
setup_trace();
end
endmodule

9
test_regress/t/t_trace_dumpvars_hier_scope.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_hier_scope.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with hierarchical scope: level 1 limits to direct signals of sub_a.deep_i
$dumpvars(1, sub_a.deep_i);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_hier_struct.py
View File

@ -8,14 +8,9 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd --trace-structs'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

46
test_regress/t/t_trace_dumpvars_hier_struct.v
View File

@ -1,46 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
typedef struct packed {
logic [31:0] add;
logic [31:0] cyc;
logic [31:0] inner;
} deep_t;
typedef struct packed {
deep_t deep;
logic [31:0] value;
} top_t;
module t(
input clk
);
int cyc;
top_t mystruct;
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with a traced struct sub-scope.
$dumpvars(1, t.mystruct.deep);
end
always_comb begin
mystruct.value = cyc + 32'd10;
mystruct.deep.add = 32'd11;
mystruct.deep.cyc = cyc;
mystruct.deep.inner = cyc + mystruct.deep.add;
end
endmodule

9
test_regress/t/t_trace_dumpvars_level.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_level.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with level argument (level 1 = top-level signals only)
$dumpvars(1);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_level_scope.py
View File

@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_level_scope.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with level AND scope: level 1 limits to sub_a direct signals only
$dumpvars(1, sub_a);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

4
test_regress/t/t_trace_dumpvars_missing2.out
View File

@ -1,5 +1,5 @@
%Error: t/t_trace_dumpvars_missing2.v:28:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname'
28 | $dumpvars(t.missingname);
%Error: t/t_trace_dumpvars.v:262:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname'
262 | $dumpvars(t.missingname);
| ^~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

6
test_regress/t/t_trace_dumpvars_missing2.py
View File

@ -8,10 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'],
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_missing2.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with a hierarchical non-existent scope argument
$dumpvars(t.missingname);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

4
test_regress/t/t_trace_dumpvars_missing3.out
View File

@ -1,5 +1,5 @@
%Error: t/t_trace_dumpvars_missing3.v:28:5: $dumpvars target not found: t.missing
28 | $dumpvars(0, t.missing);
%Error: t/t_trace_dumpvars.v:264:5: $dumpvars target not found: t.missing
264 | $dumpvars(0, t.missing);
| ^~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

6
test_regress/t/t_trace_dumpvars_missing3.py
View File

@ -8,10 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'],
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_missing3.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with level and hierarchical non-existent scope
$dumpvars(0, t.missing);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

4
test_regress/t/t_trace_dumpvars_missing4.out
View File

@ -1,5 +1,5 @@
%Error: t/t_trace_dumpvars_missing4.v:28:5: $dumpvars target not found: t.sub_a.missing
28 | $dumpvars(0, t.sub_a.missing);
%Error: t/t_trace_dumpvars.v:266:5: $dumpvars target not found: t.sub_a.missing
266 | $dumpvars(0, t.sub_a.missing);
| ^~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

6
test_regress/t/t_trace_dumpvars_missing4.py
View File

@ -8,10 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'],
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_missing4.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with a valid sub-scope but missing child
$dumpvars(0, t.sub_a.missing);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

4
test_regress/t/t_trace_dumpvars_missing5.out
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@ -1,5 +1,5 @@
%Error: t/t_trace_dumpvars_missing5.v:28:5: $dumpvars target not found: missing.child
28 | $dumpvars(0, missing.child);
%Error: t/t_trace_dumpvars.v:268:5: $dumpvars target not found: missing.child
268 | $dumpvars(0, missing.child);
| ^~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

6
test_regress/t/t_trace_dumpvars_missing5.py
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@ -8,10 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'],
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_missing5.v
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@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with a missing multi-component target under --main.
$dumpvars(0, missing.child);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

4
test_regress/t/t_trace_dumpvars_missing_scope.out
View File

@ -1,5 +1,5 @@
%Error: t/t_trace_dumpvars_missing_scope.v:28:5: $dumpvars target not found: missing_module
28 | $dumpvars(0, missing_module);
%Error: t/t_trace_dumpvars.v:260:5: $dumpvars target not found: missing_module
260 | $dumpvars(0, missing_module);
| ^~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

6
test_regress/t/t_trace_dumpvars_missing_scope.py
View File

@ -8,10 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'],
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_missing_scope.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with a non-existent module scope argument
$dumpvars(0, missing_module);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_multi_scope.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_multi_scope.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test multiple scopes with non-constant level expression
$dumpvars(0+1, t, t.sub_a.deep_i);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_nonconst_scope.py
View File

@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute(all_run_flags=['+LEVEL=0'])
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

52
test_regress/t/t_trace_dumpvars_nonconst_scope.v
View File

@ -1,52 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin: dumpblock
int level;
if (!$value$plusargs("LEVEL=%d", level)) level = 0;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with non-constant level expression and scope argument
$dumpvars(level, t.sub_a);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_override.py
View File

@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

51
test_regress/t/t_trace_dumpvars_override.v
View File

@ -1,51 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// First restrict to deep_i only, then override with $dumpvars(0) to dump all
$dumpvars(1, t.sub_a.deep_i);
$dumpvars(0);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_scope.py
View File

@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_scope.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with module scope argument
$dumpvars(0, sub_a);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_struct.py
View File

@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd --trace-structs'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

57
test_regress/t/t_trace_dumpvars_struct.v
View File

@ -1,57 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
typedef struct packed {
logic [7:0] \x ;
logic [7:0] y;
} point_t;
typedef struct packed {
point_t origin;
point_t size;
} rect_t;
int cyc;
rect_t rect;
point_t \pt ;
sub #(10) sub_a(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
\pt .\x <= \pt .\x + 1;
\pt .y <= \pt .y + 2;
rect.origin.\x <= rect.origin.\x + 1;
rect.origin.y <= rect.origin.y + 2;
rect.size.\x <= 8'd100;
rect.size.y <= 8'd200;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Target a single escaped struct member in $dumpvars.
$dumpvars(1, rect.origin.\x );
$dumpvars(1, \pt .\y );
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_sub.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

54
test_regress/t/t_trace_dumpvars_sub.v
View File

@ -1,54 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
// $dumpvars called from sub module scope with level 1
// Should dump only this sub module's direct signals, not deep_i's
initial begin
$dumpvars(1);
end
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_sub0.py
View File

@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

54
test_regress/t/t_trace_dumpvars_sub0.v
View File

@ -1,54 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
// $dumpvars called from sub module scope with level 0
// Should dump all signals in this sub module and below (including deep_i)
initial begin
$dumpvars(0);
end
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

4
test_regress/t/t_trace_dumpvars_t.out
View File

@ -1,5 +1,5 @@
%Error: t/t_trace_dumpvars_t.v:28:15: Can't find definition of variable: 't'
28 | $dumpvars(t);
%Error: t/t_trace_dumpvars.v:258:15: Can't find definition of variable: 't'
258 | $dumpvars(t);
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

6
test_regress/t/t_trace_dumpvars_t.py
View File

@ -8,10 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'],
expect_filename=test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

50
test_regress/t/t_trace_dumpvars_t.v
View File

@ -1,50 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
initial begin
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
// Test $dumpvars with module type name as argument
$dumpvars(t);
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_task.py
View File

@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

61
test_regress/t/t_trace_dumpvars_task.v
View File

@ -1,61 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
function int get_trace_level;
return 1;
endfunction
function void varsdump;
$dumpvars(get_trace_level());
endfunction
task setup_trace;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
varsdump();
endtask
module t(
input clk
);
int cyc;
sub #(10) sub_a(.*);
sub #(20) sub_b(.*);
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub #(
parameter int ADD
)(
input int cyc
);
int value;
always_comb value = cyc + ADD;
initial begin
setup_trace;
end
deep #(ADD + 1) deep_i(.*);
endmodule
module deep #(
parameter int ADD
)(
input int cyc
);
int inner;
always_comb inner = cyc + ADD;
endmodule

9
test_regress/t/t_trace_dumpvars_task2.py
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@ -8,13 +8,8 @@
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
import trace_dumpvars_common
test.scenarios('vlt')
test.compile(verilator_flags2=['--binary --trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()
trace_dumpvars_common.run(test)

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