diff --git a/test_regress/t/t_trace_dumpvars.py b/test_regress/t/t_trace_dumpvars.py index d2549038e..59ddf5500 100644 --- a/test_regress/t/t_trace_dumpvars.py +++ b/test_regress/t/t_trace_dumpvars.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars.v b/test_regress/t/t_trace_dumpvars.v index 5c2063a08..d7758b922 100644 --- a/test_regress/t/t_trace_dumpvars.v +++ b/test_regress/t/t_trace_dumpvars.v @@ -6,33 +6,379 @@ `define STRINGIFY(x) `"x`" -module t( +/* verilator lint_off MULTITOP */ + +`ifdef TRACE_DUMPVARS_CASE_HIER_STRUCT +`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT +`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT2 +`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH +`endif + +`ifdef TRACE_DUMPVARS_CASE_HIER_ARRAY +`define TRACE_DUMPVARS_ARRAY_BRANCH +`elsif TRACE_DUMPVARS_CASE_HIER_ARRAY_OOB +`define TRACE_DUMPVARS_ARRAY_BRANCH +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY +`define TRACE_DUMPVARS_ARRAY_BRANCH +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY_OOB +`define TRACE_DUMPVARS_ARRAY_BRANCH +`endif + +`ifdef TRACE_DUMPVARS_CASE_FUNC +`define TRACE_DUMPVARS_TASK_BRANCH +`elsif TRACE_DUMPVARS_CASE_TASK +`define TRACE_DUMPVARS_TASK_BRANCH +`elsif TRACE_DUMPVARS_CASE_TASK2 +`define TRACE_DUMPVARS_TASK_BRANCH +`endif + +`ifdef TRACE_DUMPVARS_PACKED_STRUCT_BRANCH +typedef struct packed { + logic [31:0] add; + logic [31:0] cyc; + logic [31:0] inner; +} deep_t; + +typedef struct packed { + deep_t deep; + logic [31:0] value; +} top_t; +`endif + +`ifdef TRACE_DUMPVARS_TASK_BRANCH +function int get_trace_level; + return 1; +endfunction + +function void varsdump; + $dumpvars(get_trace_level()); +endfunction + +`ifdef TRACE_DUMPVARS_CASE_FUNC +function void setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + varsdump(); +endfunction +`else +task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + varsdump(); +endtask +`endif + +`ifdef TRACE_DUMPVARS_CASE_TASK2 +task setup_trace_nested; + setup_trace(); +endtask +`endif +`endif + +module t +`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE +; +`else +( input clk ); +`endif int cyc; +`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE + logic clk; +`endif +`ifdef TRACE_DUMPVARS_CASE_CONTEXT + int top; +`endif +`ifdef TRACE_DUMPVARS_CASE_WIRE + int counter; +`endif +`ifdef TRACE_DUMPVARS_PACKED_STRUCT_BRANCH + top_t mystruct; +`endif +`ifdef TRACE_DUMPVARS_CASE_STRUCT + typedef struct packed { + logic [7:0] \x ; + logic [7:0] y; + } point_t; + typedef struct packed { + point_t origin; + point_t size; + } rect_t; + + rect_t rect; + point_t \pt ; +`endif + +`ifdef TRACE_DUMPVARS_ARRAY_BRANCH + sub #(10) arr[2](.*); +`elsif TRACE_DUMPVARS_CASE_GEN + genvar i; + generate + for (i = 0; i < 2; i = i + 1) begin : gen_sub + sub #(10 * (i + 1)) sub_i(.*); + end + endgenerate +`elsif TRACE_DUMPVARS_PACKED_STRUCT_BRANCH +`elsif TRACE_DUMPVARS_CASE_STRUCT + sub #(10) sub_a(.*); +`else sub #(10) sub_a(.*); sub #(20) sub_b(.*); +`endif + +`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE + initial begin + clk = 0; + forever #1 clk = !clk; + end +`endif always @(posedge clk) begin cyc <= cyc + 1; +`ifdef TRACE_DUMPVARS_CASE_STRUCT + \pt .\x <= \pt .\x + 1; + \pt .y <= \pt .y + 2; + rect.origin.\x <= rect.origin.\x + 1; + rect.origin.y <= rect.origin.y + 2; + rect.size.\x <= 8'd100; + rect.size.y <= 8'd200; +`endif +`ifdef TRACE_DUMPVARS_CASE_WIRE + counter <= counter + 2; +`endif +`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE + if (cyc == 1) begin + $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx1.vcd"}); + $dumpvars(0, sub_b); + end +`endif if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end +`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE + initial begin + $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx0.vcd"}); + $dumpvars(1, sub_a); + end +`elsif TRACE_DUMPVARS_CASE_STRUCT initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(0); + $dumpvars(1, rect.origin.\x ); + $dumpvars(1, \pt .\y ); end +`elsif TRACE_DUMPVARS_PACKED_STRUCT_BRANCH + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); +`ifdef TRACE_DUMPVARS_CASE_HIER_STRUCT + $dumpvars(1, t.mystruct.deep); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT + $dumpvars(1, cpptop.t.mystruct.deep); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT2 + $dumpvars(1, cpptop.t.mystruct.deep.inner); +`else +`error "Missing packed struct trace_dumpvars case" +`endif + end + + always_comb begin + mystruct.value = cyc + 32'd10; + mystruct.deep.add = 32'd11; + mystruct.deep.cyc = cyc; + mystruct.deep.inner = cyc + mystruct.deep.add; + end +`elsif TRACE_DUMPVARS_ARRAY_BRANCH + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); +`ifdef TRACE_DUMPVARS_CASE_HIER_ARRAY + $dumpvars(1, t.arr[1].deep); +`elsif TRACE_DUMPVARS_CASE_HIER_ARRAY_OOB + $dumpvars(1, t.arr[999].deep); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY + $dumpvars(1, cpptop.t.arr[1].deep); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY_OOB + $dumpvars(1, cpptop.t.arr[999].deep); +`else +`error "Missing array trace_dumpvars case" +`endif + end +`elsif TRACE_DUMPVARS_CASE_GEN + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(0, gen_sub[0]); + end +`elsif TRACE_DUMPVARS_TASK_BRANCH +`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL +`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK +`elsif TRACE_DUMPVARS_CASE_NONCONST_SCOPE + initial begin: dumpblock + int level; + if (!$value$plusargs("LEVEL=%d", level)) level = 0; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(level, t.sub_a); + end +`elsif TRACE_DUMPVARS_CASE_SUB + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + end +`elsif TRACE_DUMPVARS_CASE_SUB0 + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + end +`else + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); +`ifdef TRACE_DUMPVARS_CASE_BASE + $dumpvars(0); +`elsif TRACE_DUMPVARS_CASE_SCOPE + $dumpvars(0, sub_a); +`elsif TRACE_DUMPVARS_CASE_MULTI_SCOPE + $dumpvars(0+1, t, t.sub_a.deep_i); +`elsif TRACE_DUMPVARS_CASE_ABS_SCOPE + $dumpvars(0, t.sub_a); +`elsif TRACE_DUMPVARS_CASE_OVERRIDE + $dumpvars(1, t.sub_a.deep_i); + $dumpvars(0); +`elsif TRACE_DUMPVARS_CASE_CONTEXT + $dumpvars(1, t.sub_a.deep_i); + $dumpvars(0, top); +`elsif TRACE_DUMPVARS_CASE_LEVEL + $dumpvars(1); +`elsif TRACE_DUMPVARS_CASE_LEVEL_SCOPE + $dumpvars(1, sub_a); +`elsif TRACE_DUMPVARS_CASE_HIER_SCOPE + $dumpvars(1, sub_a.deep_i); +`elsif TRACE_DUMPVARS_CASE_WIRE + $dumpvars(0, cyc, counter); +`elsif TRACE_DUMPVARS_CASE_T + $dumpvars(t); +`elsif TRACE_DUMPVARS_CASE_MISSING_SCOPE + $dumpvars(0, missing_module); +`elsif TRACE_DUMPVARS_CASE_MISSING2 + $dumpvars(t.missingname); +`elsif TRACE_DUMPVARS_CASE_MISSING3 + $dumpvars(0, t.missing); +`elsif TRACE_DUMPVARS_CASE_MISSING4 + $dumpvars(0, t.sub_a.missing); +`elsif TRACE_DUMPVARS_CASE_MISSING5 + $dumpvars(0, missing.child); +`elsif TRACE_DUMPVARS_CASE_CPPTOP + $dumpvars(0, cpptop, cpptop.t); +`elsif TRACE_DUMPVARS_CASE_CPPTOP2 + $dumpvars(0, cpptop, cpptop.notfound); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING + $dumpvars(0, missing_module); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING2 + $dumpvars(t.missingname); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING3 + $dumpvars(0, t.missing); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING4 + $dumpvars(0, t.sub_a.missing); +`else +`error "Missing trace_dumpvars case define" +`endif + end +`endif endmodule module sub #( - parameter int ADD + parameter int ADD = 0 )( input int cyc ); int value; always_comb value = cyc + ADD; + +`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK + function void dump_from_func; + $dumpvars(1, t); + endfunction + + task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + dump_from_func(); + endtask +`endif + +`ifdef TRACE_DUMPVARS_ARRAY_BRANCH + deep #(ADD + 1) deep(.*); +`elsif TRACE_DUMPVARS_CASE_BASE +`elsif TRACE_DUMPVARS_CASE_WIRE +`elsif TRACE_DUMPVARS_CASE_CPPTOP +`elsif TRACE_DUMPVARS_CASE_CPPTOP2 +`elsif TRACE_DUMPVARS_CASE_STRUCT +`else + deep #(ADD + 1) deep_i(.*); +`endif + +`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(1, t); + end +`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK + initial begin + setup_trace(); + end +`elsif TRACE_DUMPVARS_CASE_TASK2 + initial begin + setup_trace_nested; + end +`elsif TRACE_DUMPVARS_TASK_BRANCH + initial begin + setup_trace; + end +`elsif TRACE_DUMPVARS_CASE_SUB + initial begin + $dumpvars(1); + end +`elsif TRACE_DUMPVARS_CASE_SUB0 + initial begin + $dumpvars(0); + end +`endif endmodule + +module deep #( + parameter int ADD = 0 +)( + input int cyc +); + int inner; +`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL + int t; +`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK + int t; +`endif + always_comb inner = cyc + ADD; + +`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK + function void dump_from_func; + $dumpvars(1, t); + endfunction + + task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + dump_from_func(); + endtask + + initial begin + setup_trace(); + end +`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(1, t); + end +`elsif TRACE_DUMPVARS_CASE_CONTEXT + initial begin + $dumpvars(0); + end +`endif +endmodule + +/* verilator lint_on MULTITOP */ diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.py b/test_regress/t/t_trace_dumpvars_abs_scope.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_abs_scope.py +++ b/test_regress/t/t_trace_dumpvars_abs_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.v b/test_regress/t/t_trace_dumpvars_abs_scope.v deleted file mode 100644 index 2a225c3cb..000000000 --- a/test_regress/t/t_trace_dumpvars_abs_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with absolute hierarchical scope path - $dumpvars(0, t.sub_a); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_add_module.py b/test_regress/t/t_trace_dumpvars_add_module.py index 006c898da..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_add_module.py +++ b/test_regress/t/t_trace_dumpvars_add_module.py @@ -8,14 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --timing --trace-vcd']) - -test.execute() - -test.vcd_identical(test.obj_dir + '/simx0.vcd', test.t_dir + '/t_trace_dumpvars_add_module_0.out') -test.vcd_identical(test.obj_dir + '/simx1.vcd', test.t_dir + '/t_trace_dumpvars_add_module_1.out') - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_add_module.v b/test_regress/t/t_trace_dumpvars_add_module.v deleted file mode 100644 index bf812302c..000000000 --- a/test_regress/t/t_trace_dumpvars_add_module.v +++ /dev/null @@ -1,58 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( -); - logic clk; - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - initial begin - clk = 0; - forever #1 clk = !clk; - end - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx1.vcd"}); - $dumpvars(0, sub_b); - end - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx0.vcd"}); - $dumpvars(1, sub_a); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_context.py b/test_regress/t/t_trace_dumpvars_context.py index 5a79df61f..558d60a06 100644 --- a/test_regress/t/t_trace_dumpvars_context.py +++ b/test_regress/t/t_trace_dumpvars_context.py @@ -8,14 +8,9 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_context.v b/test_regress/t/t_trace_dumpvars_context.v deleted file mode 100644 index 5bc230c54..000000000 --- a/test_regress/t/t_trace_dumpvars_context.v +++ /dev/null @@ -1,57 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - int top; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // First restrict to sub_a.deep_i only, then let deep_i issue $dumpvars(0) - // to confirm the no-target override still expands tracing globally. - $dumpvars(1, t.sub_a.deep_i); - $dumpvars(0, top); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; - - initial begin - $dumpvars(0); - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop.py b/test_regress/t/t_trace_dumpvars_cpptop.py index e59720885..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop.py +++ b/test_regress/t/t_trace_dumpvars_cpptop.py @@ -8,20 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop.cpp', - ]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop.v b/test_regress/t/t_trace_dumpvars_cpptop.v deleted file mode 100644 index 334e709e0..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop.v +++ /dev/null @@ -1,39 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // cpptop is defined in the C++ testbench as the root of the trace hierarchy, so $dumpvars(0, cpptop) should dump everything. - $dumpvars(0, cpptop, cpptop.t); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.cpp b/test_regress/t/t_trace_dumpvars_cpptop2.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop2.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.out b/test_regress/t/t_trace_dumpvars_cpptop2.out index 7660a7232..a585565b4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop2.out +++ b/test_regress/t/t_trace_dumpvars_cpptop2.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_cpptop2.v:27:5: $dumpvars target not found: cpptop.notfound - 27 | $dumpvars(0, cpptop, cpptop.notfound); +%Error: t/t_trace_dumpvars.v:272:5: $dumpvars target not found: cpptop.notfound + 272 | $dumpvars(0, cpptop, cpptop.notfound); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.py b/test_regress/t/t_trace_dumpvars_cpptop2.py index b942b16fa..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop2.py +++ b/test_regress/t/t_trace_dumpvars_cpptop2.py @@ -8,18 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - fails=True, - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop.cpp', - ], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.v b/test_regress/t/t_trace_dumpvars_cpptop2.v deleted file mode 100644 index 4d3f29d36..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop2.v +++ /dev/null @@ -1,38 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(0, cpptop, cpptop.notfound); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py index 4e8341f6c..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py @@ -8,20 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_hier_array.cpp', - ]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.v deleted file mode 100644 index a36a7a8d5..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.v +++ /dev/null @@ -1,49 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) arr[2](.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with an arrayed hierarchical scope path via cpptop. - $dumpvars(1, cpptop.t.arr[1].deep); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py index 976058255..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py @@ -8,20 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_hier_array_oob.cpp', - ]) - -test.execute() - -test.files_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v deleted file mode 100644 index 6a64c812f..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v +++ /dev/null @@ -1,49 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) arr[2](.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with an out-of-range array index via cpptop. - $dumpvars(1, cpptop.t.arr[999].deep); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py index 9779f2f74..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py @@ -8,18 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_hier_global.cpp', - ]) - -test.execute() - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.v deleted file mode 100644 index 37dd5d357..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.v +++ /dev/null @@ -1,56 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with hierarchical scope: level 1 limits to direct signals of t outside the scope - $dumpvars(1, t); - end -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - int t; - always_comb inner = cyc + ADD; - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(1, t); - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py index 8947c16b2..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py @@ -8,21 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - '--trace-structs', - 't/t_trace_dumpvars_cpptop_hier_struct.cpp', - ]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v deleted file mode 100644 index 351212317..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v +++ /dev/null @@ -1,46 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -typedef struct packed { - logic [31:0] add; - logic [31:0] cyc; - logic [31:0] inner; -} deep_t; - -typedef struct packed { - deep_t deep; - logic [31:0] value; -} top_t; - -module t( - input clk -); - int cyc; - top_t mystruct; - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a traced struct sub-scope via cpptop. - $dumpvars(1, cpptop.t.mystruct.deep); - end - - always_comb begin - mystruct.value = cyc + 32'd10; - mystruct.deep.add = 32'd11; - mystruct.deep.cyc = cyc; - mystruct.deep.inner = cyc + mystruct.deep.add; - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py index dce00d975..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py @@ -8,19 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - '--trace-structs', - 't/t_trace_dumpvars_cpptop_hier_struct2.cpp', - ]) - -test.execute() - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v deleted file mode 100644 index e15dc0c45..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v +++ /dev/null @@ -1,46 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -typedef struct packed { - logic [31:0] add; - logic [31:0] cyc; - logic [31:0] inner; -} deep_t; - -typedef struct packed { - deep_t deep; - logic [31:0] value; -} top_t; - -module t( - input clk -); - int cyc; - top_t mystruct; - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a struct leaf member via cpptop. - $dumpvars(1, cpptop.t.mystruct.deep.inner); - end - - always_comb begin - mystruct.value = cyc + 32'd10; - mystruct.deep.add = 32'd11; - mystruct.deep.cyc = cyc; - mystruct.deep.inner = cyc + mystruct.deep.add; - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.out b/test_regress/t/t_trace_dumpvars_cpptop_missing.out index 1342a7374..def8decb6 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing.out +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing.out @@ -1,2 +1,2 @@ -%Error: t/t_trace_dumpvars_cpptop_missing.v:28: $dumpvars target not found: missing_module +%Error: t/t_trace_dumpvars.v:274: $dumpvars target not found: missing_module Aborting... diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.py b/test_regress/t/t_trace_dumpvars_cpptop_missing.py index c5f10a6dd..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing.py @@ -8,19 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_missing.cpp', - ]) - -test.execute(fails=True, - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.v b/test_regress/t/t_trace_dumpvars_cpptop_missing.v deleted file mode 100644 index 52816b852..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a non-existent module scope argument via cpptop. - $dumpvars(0, missing_module); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.out b/test_regress/t/t_trace_dumpvars_cpptop_missing2.out index 829ff6e43..a1a1a3e13 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing2.out +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing2.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_cpptop_missing2.v:28:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname' - 28 | $dumpvars(t.missingname); +%Error: t/t_trace_dumpvars.v:276:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname' + 276 | $dumpvars(t.missingname); | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.py b/test_regress/t/t_trace_dumpvars_cpptop_missing2.py index b0c45db1a..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing2.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing2.py @@ -8,18 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - fails=True, - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_missing2.cpp', - ], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.v b/test_regress/t/t_trace_dumpvars_cpptop_missing2.v deleted file mode 100644 index 600be2574..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing2.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a hierarchical non-existent scope argument via cpptop. - $dumpvars(t.missingname); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.out b/test_regress/t/t_trace_dumpvars_cpptop_missing3.out index f7ba9c4e1..9f778c04b 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing3.out +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing3.out @@ -1,2 +1,2 @@ -%Error: t/t_trace_dumpvars_cpptop_missing3.v:28: $dumpvars target not found: t.missing +%Error: t/t_trace_dumpvars.v:278: $dumpvars target not found: t.missing Aborting... diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.py b/test_regress/t/t_trace_dumpvars_cpptop_missing3.py index 642a2cb0b..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing3.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing3.py @@ -8,19 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_missing3.cpp', - ]) - -test.execute(fails=True, - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.v b/test_regress/t/t_trace_dumpvars_cpptop_missing3.v deleted file mode 100644 index e00189d61..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing3.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with level and hierarchical non-existent scope via cpptop. - $dumpvars(0, t.missing); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.out b/test_regress/t/t_trace_dumpvars_cpptop_missing4.out index 9c860bd10..cf0802e31 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing4.out +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing4.out @@ -1,2 +1,2 @@ -%Error: t/t_trace_dumpvars_cpptop_missing4.v:28: $dumpvars target not found: t.sub_a.missing +%Error: t/t_trace_dumpvars.v:280: $dumpvars target not found: t.sub_a.missing Aborting... diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.py b/test_regress/t/t_trace_dumpvars_cpptop_missing4.py index 5696a1b7f..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing4.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing4.py @@ -8,19 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_missing4.cpp', - ]) - -test.execute(fails=True, - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.v b/test_regress/t/t_trace_dumpvars_cpptop_missing4.v deleted file mode 100644 index e03a6d18f..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing4.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a valid sub-scope but missing child via cpptop. - $dumpvars(0, t.sub_a.missing); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_func.py b/test_regress/t/t_trace_dumpvars_func.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_func.py +++ b/test_regress/t/t_trace_dumpvars_func.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_func.v b/test_regress/t/t_trace_dumpvars_func.v deleted file mode 100644 index cf70710da..000000000 --- a/test_regress/t/t_trace_dumpvars_func.v +++ /dev/null @@ -1,61 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -function int get_trace_level; - return 1; -endfunction - -function void varsdump; - $dumpvars(get_trace_level()); -endfunction - -function void setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - varsdump(); -endfunction - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - initial begin - setup_trace; - end - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_gen.py b/test_regress/t/t_trace_dumpvars_gen.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_gen.py +++ b/test_regress/t/t_trace_dumpvars_gen.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_gen.v b/test_regress/t/t_trace_dumpvars_gen.v deleted file mode 100644 index 1b6b0524b..000000000 --- a/test_regress/t/t_trace_dumpvars_gen.v +++ /dev/null @@ -1,55 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - // Generate block creates sub instances with named block scope - genvar i; - generate - for (i = 0; i < 2; i = i + 1) begin : gen_sub - sub #(10 * (i + 1)) sub_i(.*); - end - endgenerate - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Dump only gen_sub[0] and everything below it - $dumpvars(0, gen_sub[0]); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_array.py b/test_regress/t/t_trace_dumpvars_hier_array.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_array.py +++ b/test_regress/t/t_trace_dumpvars_hier_array.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_array.v b/test_regress/t/t_trace_dumpvars_hier_array.v deleted file mode 100644 index dbe673d73..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_array.v +++ /dev/null @@ -1,49 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) arr[2](.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with an arrayed hierarchical scope path. - $dumpvars(1, t.arr[1].deep); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_array_oob.py b/test_regress/t/t_trace_dumpvars_hier_array_oob.py index 3ead6a6d5..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_array_oob.py +++ b/test_regress/t/t_trace_dumpvars_hier_array_oob.py @@ -8,11 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_array_oob.v b/test_regress/t/t_trace_dumpvars_hier_array_oob.v deleted file mode 100644 index 8da72ff52..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_array_oob.v +++ /dev/null @@ -1,49 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) arr[2](.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with an out-of-range array index. - $dumpvars(1, t.arr[999].deep); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_global.py b/test_regress/t/t_trace_dumpvars_hier_global.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_global.py +++ b/test_regress/t/t_trace_dumpvars_hier_global.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_global.v b/test_regress/t/t_trace_dumpvars_hier_global.v deleted file mode 100644 index 37dd5d357..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_global.v +++ /dev/null @@ -1,56 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with hierarchical scope: level 1 limits to direct signals of t outside the scope - $dumpvars(1, t); - end -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - int t; - always_comb inner = cyc + ADD; - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(1, t); - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.py b/test_regress/t/t_trace_dumpvars_hier_global_task.py index 38f138c77..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_global_task.py +++ b/test_regress/t/t_trace_dumpvars_hier_global_task.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd --fno-inline']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.v b/test_regress/t/t_trace_dumpvars_hier_global_task.v deleted file mode 100644 index 5877a243c..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_global_task.v +++ /dev/null @@ -1,71 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - function void dump_from_func; - $dumpvars(1, t); - endfunction - - task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - dump_from_func(); - endtask - - deep #(ADD + 1) deep_i(.*); - - initial begin - setup_trace(); - end -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - int t; - always_comb inner = cyc + ADD; - - function void dump_from_func; - $dumpvars(1, t); - endfunction - - task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - dump_from_func(); - endtask - - initial begin - setup_trace(); - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.py b/test_regress/t/t_trace_dumpvars_hier_scope.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_scope.py +++ b/test_regress/t/t_trace_dumpvars_hier_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.v b/test_regress/t/t_trace_dumpvars_hier_scope.v deleted file mode 100644 index 97c3bfd55..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with hierarchical scope: level 1 limits to direct signals of sub_a.deep_i - $dumpvars(1, sub_a.deep_i); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.py b/test_regress/t/t_trace_dumpvars_hier_struct.py index 791c137e1..558d60a06 100644 --- a/test_regress/t/t_trace_dumpvars_hier_struct.py +++ b/test_regress/t/t_trace_dumpvars_hier_struct.py @@ -8,14 +8,9 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd --trace-structs']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.v b/test_regress/t/t_trace_dumpvars_hier_struct.v deleted file mode 100644 index 82614345a..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_struct.v +++ /dev/null @@ -1,46 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -typedef struct packed { - logic [31:0] add; - logic [31:0] cyc; - logic [31:0] inner; -} deep_t; - -typedef struct packed { - deep_t deep; - logic [31:0] value; -} top_t; - -module t( - input clk -); - int cyc; - top_t mystruct; - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a traced struct sub-scope. - $dumpvars(1, t.mystruct.deep); - end - - always_comb begin - mystruct.value = cyc + 32'd10; - mystruct.deep.add = 32'd11; - mystruct.deep.cyc = cyc; - mystruct.deep.inner = cyc + mystruct.deep.add; - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_level.py b/test_regress/t/t_trace_dumpvars_level.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_level.py +++ b/test_regress/t/t_trace_dumpvars_level.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_level.v b/test_regress/t/t_trace_dumpvars_level.v deleted file mode 100644 index df73db139..000000000 --- a/test_regress/t/t_trace_dumpvars_level.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with level argument (level 1 = top-level signals only) - $dumpvars(1); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_level_scope.py b/test_regress/t/t_trace_dumpvars_level_scope.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_level_scope.py +++ b/test_regress/t/t_trace_dumpvars_level_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_level_scope.v b/test_regress/t/t_trace_dumpvars_level_scope.v deleted file mode 100644 index b7863aee2..000000000 --- a/test_regress/t/t_trace_dumpvars_level_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with level AND scope: level 1 limits to sub_a direct signals only - $dumpvars(1, sub_a); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing2.out b/test_regress/t/t_trace_dumpvars_missing2.out index 6f63f58e5..34d4cf6c8 100644 --- a/test_regress/t/t_trace_dumpvars_missing2.out +++ b/test_regress/t/t_trace_dumpvars_missing2.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_missing2.v:28:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname' - 28 | $dumpvars(t.missingname); +%Error: t/t_trace_dumpvars.v:262:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname' + 262 | $dumpvars(t.missingname); | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing2.py b/test_regress/t/t_trace_dumpvars_missing2.py index b00fb4934..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_missing2.py +++ b/test_regress/t/t_trace_dumpvars_missing2.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_missing2.v b/test_regress/t/t_trace_dumpvars_missing2.v deleted file mode 100644 index 0f54a11c6..000000000 --- a/test_regress/t/t_trace_dumpvars_missing2.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a hierarchical non-existent scope argument - $dumpvars(t.missingname); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing3.out b/test_regress/t/t_trace_dumpvars_missing3.out index 5f9651d7e..ff13ccdd2 100644 --- a/test_regress/t/t_trace_dumpvars_missing3.out +++ b/test_regress/t/t_trace_dumpvars_missing3.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_missing3.v:28:5: $dumpvars target not found: t.missing - 28 | $dumpvars(0, t.missing); +%Error: t/t_trace_dumpvars.v:264:5: $dumpvars target not found: t.missing + 264 | $dumpvars(0, t.missing); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing3.py b/test_regress/t/t_trace_dumpvars_missing3.py index b00fb4934..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_missing3.py +++ b/test_regress/t/t_trace_dumpvars_missing3.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_missing3.v b/test_regress/t/t_trace_dumpvars_missing3.v deleted file mode 100644 index c00c8687a..000000000 --- a/test_regress/t/t_trace_dumpvars_missing3.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with level and hierarchical non-existent scope - $dumpvars(0, t.missing); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing4.out b/test_regress/t/t_trace_dumpvars_missing4.out index cb1dfa5fc..692c591c2 100644 --- a/test_regress/t/t_trace_dumpvars_missing4.out +++ b/test_regress/t/t_trace_dumpvars_missing4.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_missing4.v:28:5: $dumpvars target not found: t.sub_a.missing - 28 | $dumpvars(0, t.sub_a.missing); +%Error: t/t_trace_dumpvars.v:266:5: $dumpvars target not found: t.sub_a.missing + 266 | $dumpvars(0, t.sub_a.missing); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing4.py b/test_regress/t/t_trace_dumpvars_missing4.py index b00fb4934..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_missing4.py +++ b/test_regress/t/t_trace_dumpvars_missing4.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_missing4.v b/test_regress/t/t_trace_dumpvars_missing4.v deleted file mode 100644 index 288885aaa..000000000 --- a/test_regress/t/t_trace_dumpvars_missing4.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a valid sub-scope but missing child - $dumpvars(0, t.sub_a.missing); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing5.out b/test_regress/t/t_trace_dumpvars_missing5.out index a3e49d998..1301b5faf 100644 --- a/test_regress/t/t_trace_dumpvars_missing5.out +++ b/test_regress/t/t_trace_dumpvars_missing5.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_missing5.v:28:5: $dumpvars target not found: missing.child - 28 | $dumpvars(0, missing.child); +%Error: t/t_trace_dumpvars.v:268:5: $dumpvars target not found: missing.child + 268 | $dumpvars(0, missing.child); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing5.py b/test_regress/t/t_trace_dumpvars_missing5.py index 8a19e71bf..5d72fbb34 100644 --- a/test_regress/t/t_trace_dumpvars_missing5.py +++ b/test_regress/t/t_trace_dumpvars_missing5.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() \ No newline at end of file +trace_dumpvars_common.run(test) \ No newline at end of file diff --git a/test_regress/t/t_trace_dumpvars_missing5.v b/test_regress/t/t_trace_dumpvars_missing5.v deleted file mode 100644 index 28eb3e1b8..000000000 --- a/test_regress/t/t_trace_dumpvars_missing5.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a missing multi-component target under --main. - $dumpvars(0, missing.child); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule \ No newline at end of file diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.out b/test_regress/t/t_trace_dumpvars_missing_scope.out index 7272e6db5..dfaa1f61a 100644 --- a/test_regress/t/t_trace_dumpvars_missing_scope.out +++ b/test_regress/t/t_trace_dumpvars_missing_scope.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_missing_scope.v:28:5: $dumpvars target not found: missing_module - 28 | $dumpvars(0, missing_module); +%Error: t/t_trace_dumpvars.v:260:5: $dumpvars target not found: missing_module + 260 | $dumpvars(0, missing_module); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.py b/test_regress/t/t_trace_dumpvars_missing_scope.py index b00fb4934..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_missing_scope.py +++ b/test_regress/t/t_trace_dumpvars_missing_scope.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.v b/test_regress/t/t_trace_dumpvars_missing_scope.v deleted file mode 100644 index f7c24a635..000000000 --- a/test_regress/t/t_trace_dumpvars_missing_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a non-existent module scope argument - $dumpvars(0, missing_module); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.py b/test_regress/t/t_trace_dumpvars_multi_scope.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_multi_scope.py +++ b/test_regress/t/t_trace_dumpvars_multi_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.v b/test_regress/t/t_trace_dumpvars_multi_scope.v deleted file mode 100644 index ae673be07..000000000 --- a/test_regress/t/t_trace_dumpvars_multi_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test multiple scopes with non-constant level expression - $dumpvars(0+1, t, t.sub_a.deep_i); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.py b/test_regress/t/t_trace_dumpvars_nonconst_scope.py index 14865b871..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_nonconst_scope.py +++ b/test_regress/t/t_trace_dumpvars_nonconst_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute(all_run_flags=['+LEVEL=0']) - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.v b/test_regress/t/t_trace_dumpvars_nonconst_scope.v deleted file mode 100644 index 3664cc288..000000000 --- a/test_regress/t/t_trace_dumpvars_nonconst_scope.v +++ /dev/null @@ -1,52 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin: dumpblock - int level; - if (!$value$plusargs("LEVEL=%d", level)) level = 0; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with non-constant level expression and scope argument - $dumpvars(level, t.sub_a); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_override.py b/test_regress/t/t_trace_dumpvars_override.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_override.py +++ b/test_regress/t/t_trace_dumpvars_override.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_override.v b/test_regress/t/t_trace_dumpvars_override.v deleted file mode 100644 index 9d45daa56..000000000 --- a/test_regress/t/t_trace_dumpvars_override.v +++ /dev/null @@ -1,51 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // First restrict to deep_i only, then override with $dumpvars(0) to dump all - $dumpvars(1, t.sub_a.deep_i); - $dumpvars(0); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_scope.py b/test_regress/t/t_trace_dumpvars_scope.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_scope.py +++ b/test_regress/t/t_trace_dumpvars_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_scope.v b/test_regress/t/t_trace_dumpvars_scope.v deleted file mode 100644 index 6b5621bc4..000000000 --- a/test_regress/t/t_trace_dumpvars_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with module scope argument - $dumpvars(0, sub_a); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_struct.py b/test_regress/t/t_trace_dumpvars_struct.py index d4c312914..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_struct.py +++ b/test_regress/t/t_trace_dumpvars_struct.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd --trace-structs']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_struct.v b/test_regress/t/t_trace_dumpvars_struct.v deleted file mode 100644 index 8f7d3e8e9..000000000 --- a/test_regress/t/t_trace_dumpvars_struct.v +++ /dev/null @@ -1,57 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - typedef struct packed { - logic [7:0] \x ; - logic [7:0] y; - } point_t; - - typedef struct packed { - point_t origin; - point_t size; - } rect_t; - - int cyc; - rect_t rect; - point_t \pt ; - - sub #(10) sub_a(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - \pt .\x <= \pt .\x + 1; - \pt .y <= \pt .y + 2; - rect.origin.\x <= rect.origin.\x + 1; - rect.origin.y <= rect.origin.y + 2; - rect.size.\x <= 8'd100; - rect.size.y <= 8'd200; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Target a single escaped struct member in $dumpvars. - $dumpvars(1, rect.origin.\x ); - $dumpvars(1, \pt .\y ); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_sub.py b/test_regress/t/t_trace_dumpvars_sub.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_sub.py +++ b/test_regress/t/t_trace_dumpvars_sub.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_sub.v b/test_regress/t/t_trace_dumpvars_sub.v deleted file mode 100644 index b79b4012b..000000000 --- a/test_regress/t/t_trace_dumpvars_sub.v +++ /dev/null @@ -1,54 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); - - // $dumpvars called from sub module scope with level 1 - // Should dump only this sub module's direct signals, not deep_i's - initial begin - $dumpvars(1); - end -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_sub0.py b/test_regress/t/t_trace_dumpvars_sub0.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_sub0.py +++ b/test_regress/t/t_trace_dumpvars_sub0.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_sub0.v b/test_regress/t/t_trace_dumpvars_sub0.v deleted file mode 100644 index 409aab752..000000000 --- a/test_regress/t/t_trace_dumpvars_sub0.v +++ /dev/null @@ -1,54 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); - - // $dumpvars called from sub module scope with level 0 - // Should dump all signals in this sub module and below (including deep_i) - initial begin - $dumpvars(0); - end -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_t.out b/test_regress/t/t_trace_dumpvars_t.out index 439aa8cfc..564660194 100644 --- a/test_regress/t/t_trace_dumpvars_t.out +++ b/test_regress/t/t_trace_dumpvars_t.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_t.v:28:15: Can't find definition of variable: 't' - 28 | $dumpvars(t); +%Error: t/t_trace_dumpvars.v:258:15: Can't find definition of variable: 't' + 258 | $dumpvars(t); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_t.py b/test_regress/t/t_trace_dumpvars_t.py index b00fb4934..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_t.py +++ b/test_regress/t/t_trace_dumpvars_t.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_t.v b/test_regress/t/t_trace_dumpvars_t.v deleted file mode 100644 index 29d4138b3..000000000 --- a/test_regress/t/t_trace_dumpvars_t.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with module type name as argument - $dumpvars(t); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_task.py b/test_regress/t/t_trace_dumpvars_task.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_task.py +++ b/test_regress/t/t_trace_dumpvars_task.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_task.v b/test_regress/t/t_trace_dumpvars_task.v deleted file mode 100644 index b8566d9bf..000000000 --- a/test_regress/t/t_trace_dumpvars_task.v +++ /dev/null @@ -1,61 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -function int get_trace_level; - return 1; -endfunction - -function void varsdump; - $dumpvars(get_trace_level()); -endfunction - -task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - varsdump(); -endtask - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - initial begin - setup_trace; - end - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_task2.py b/test_regress/t/t_trace_dumpvars_task2.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_task2.py +++ b/test_regress/t/t_trace_dumpvars_task2.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_task2.v b/test_regress/t/t_trace_dumpvars_task2.v deleted file mode 100644 index 2c3de1177..000000000 --- a/test_regress/t/t_trace_dumpvars_task2.v +++ /dev/null @@ -1,65 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -function int get_trace_level; - return 1; -endfunction - -function void varsdump; - $dumpvars(get_trace_level()); -endfunction - -task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - varsdump(); -endtask - -task setup_trace_nested; - setup_trace(); -endtask - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - initial begin - setup_trace_nested; - end - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.py b/test_regress/t/t_trace_dumpvars_task2_no_inl.py index 38f138c77..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_task2_no_inl.py +++ b/test_regress/t/t_trace_dumpvars_task2_no_inl.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd --fno-inline']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.v b/test_regress/t/t_trace_dumpvars_task2_no_inl.v deleted file mode 100644 index 2c3de1177..000000000 --- a/test_regress/t/t_trace_dumpvars_task2_no_inl.v +++ /dev/null @@ -1,65 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -function int get_trace_level; - return 1; -endfunction - -function void varsdump; - $dumpvars(get_trace_level()); -endfunction - -task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - varsdump(); -endtask - -task setup_trace_nested; - setup_trace(); -endtask - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - initial begin - setup_trace_nested; - end - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.py b/test_regress/t/t_trace_dumpvars_task_no_inl.py index 38f138c77..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_task_no_inl.py +++ b/test_regress/t/t_trace_dumpvars_task_no_inl.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd --fno-inline']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.v b/test_regress/t/t_trace_dumpvars_task_no_inl.v deleted file mode 100644 index b8566d9bf..000000000 --- a/test_regress/t/t_trace_dumpvars_task_no_inl.v +++ /dev/null @@ -1,61 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -function int get_trace_level; - return 1; -endfunction - -function void varsdump; - $dumpvars(get_trace_level()); -endfunction - -task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - varsdump(); -endtask - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - initial begin - setup_trace; - end - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_top.py b/test_regress/t/t_trace_dumpvars_top.py index e69de29bb..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_top.py +++ b/test_regress/t/t_trace_dumpvars_top.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_common + +test.scenarios('vlt') + +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_top.v b/test_regress/t/t_trace_dumpvars_top.v deleted file mode 100644 index e69de29bb..000000000 diff --git a/test_regress/t/t_trace_dumpvars_wire.py b/test_regress/t/t_trace_dumpvars_wire.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_wire.py +++ b/test_regress/t/t_trace_dumpvars_wire.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_wire.v b/test_regress/t/t_trace_dumpvars_wire.v deleted file mode 100644 index 8a8714ac5..000000000 --- a/test_regress/t/t_trace_dumpvars_wire.v +++ /dev/null @@ -1,41 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - int counter; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - counter <= counter + 2; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with specific wire names - $dumpvars(0, cyc, counter); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; -endmodule diff --git a/test_regress/t/trace_dumpvars_common.py b/test_regress/t/trace_dumpvars_common.py new file mode 100644 index 000000000..164b81538 --- /dev/null +++ b/test_regress/t/trace_dumpvars_common.py @@ -0,0 +1,148 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import os +import re + + +_SHARED_TOP = "t/t_trace_dumpvars.v" +_SHARED_CPPTOP = "t/t_trace_dumpvars_cpptop.cpp" + +_COMPILE_FAIL_CASES = { + "cpptop2", + "cpptop_missing2", + "missing_scope", + "missing2", + "missing3", + "missing4", + "missing5", + "t", +} + +_EXECUTE_FAIL_CASES = { + "cpptop_missing", + "cpptop_missing3", + "cpptop_missing4", +} + +_CPPTOP_CASES = { + "cpptop", + "cpptop2", + "cpptop_hier_array", + "cpptop_hier_array_oob", + "cpptop_hier_global", + "cpptop_hier_struct", + "cpptop_hier_struct2", + "cpptop_missing", + "cpptop_missing2", + "cpptop_missing3", + "cpptop_missing4", +} + +_STRUCT_TRACE_CASES = { + "struct", + "hier_struct", + "cpptop_hier_struct", + "cpptop_hier_struct2", +} + +_NO_INLINE_CASES = { + "hier_global_task", + "task_no_inl", + "task2_no_inl", +} + +_FILE_COMPARE_CASES = { + "cpptop_hier_array_oob", +} + +_DEFINE_ALIASES = { + "cpptop_hier_global": "hier_global", + "task_no_inl": "task", + "task2_no_inl": "task2", +} + + +def _case_name(test): + name = os.path.splitext(os.path.basename(test.py_filename))[0] + prefix = "t_trace_dumpvars" + if name == prefix: + return "base" + if not name.startswith(prefix + "_"): + test.error(f"Invalid trace dumpvars test file '{name}'") + return name[len(prefix) + 1:] + + +def _define_name(case): + define_case = _DEFINE_ALIASES.get(case, case) + token = re.sub(r"[^0-9A-Za-z]+", "_", define_case).upper() + return f"+define+TRACE_DUMPVARS_CASE_{token}" + + +def _compile_flags(case): + flags = ["--top-module", "t", _define_name(case)] + if case == "add_module": + flags = ["--binary", "--timing", "--trace-vcd", *flags] + elif case in _CPPTOP_CASES: + flags = ["--cc", "--exe", "--trace-vcd", *flags, _SHARED_CPPTOP] + else: + flags = ["--binary", "--trace-vcd", *flags] + + if case in _STRUCT_TRACE_CASES: + flags.append("--trace-structs") + if case in _NO_INLINE_CASES: + flags.append("--fno-inline") + return flags + + +def _has_golden_trace(test): + return os.path.exists(test.golden_filename) and os.path.getsize(test.golden_filename) > 0 + + +def run(test): + case = _case_name(test) + if case == "top": + test.passes() + return + + test.top_filename = _SHARED_TOP + compile_kwargs = {"verilator_flags2": _compile_flags(case)} + if case in _CPPTOP_CASES: + compile_kwargs["make_main"] = False + + if case in _COMPILE_FAIL_CASES: + test.compile(fails=True, expect_filename=test.golden_filename, **compile_kwargs) + test.passes() + return + + test.compile(**compile_kwargs) + + if case in _EXECUTE_FAIL_CASES: + test.execute(fails=True, expect_filename=test.golden_filename) + test.passes() + return + + execute_kwargs = {} + if case == "nonconst_scope": + execute_kwargs["all_run_flags"] = ['+LEVEL=0'] + + test.execute(**execute_kwargs) + + if case == "add_module": + test.vcd_identical(test.obj_dir + "/simx0.vcd", + test.t_dir + "/t_trace_dumpvars_add_module_0.out") + test.vcd_identical(test.obj_dir + "/simx1.vcd", + test.t_dir + "/t_trace_dumpvars_add_module_1.out") + elif _has_golden_trace(test): + if case in _FILE_COMPARE_CASES: + test.files_identical(test.trace_filename, test.golden_filename) + else: + test.vcd_identical(test.trace_filename, test.golden_filename) + + test.passes() \ No newline at end of file