Fix "cloning" error with -y/--top-module, bug76.

This commit is contained in:
Wilson Snyder 2009-04-07 13:23:25 -04:00
parent 6d3dd98e77
commit 3d85cbe6b5
4 changed files with 19 additions and 18 deletions

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@ -3,6 +3,10 @@ Revision history for Verilator
The contributors that suggested a given feature are shown in []. [by ...] The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks! indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.7***
**** Fix "cloning" error with -y/--top-module, bug76. [Dimitris Nalbantis]
* Verilator 3.702 2009/03/28 * Verilator 3.702 2009/03/28
*** Add --pins-bv option to use sc_bv for all ports. [Brian Small] *** Add --pins-bv option to use sc_bv for all ports. [Brian Small]

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@ -95,6 +95,7 @@ private:
V3SymTable m_mods; // Symbol table of all module names V3SymTable m_mods; // Symbol table of all module names
LinkCellsGraph m_graph; // Linked graph of all cell interconnects LinkCellsGraph m_graph; // Linked graph of all cell interconnects
LibraryVertex* m_libVertexp; // Vertex at root of all libraries LibraryVertex* m_libVertexp; // Vertex at root of all libraries
V3GraphVertex* m_topVertexp; // Vertex of top module
static int debug() { static int debug() {
static int level = -1; static int level = -1;
@ -126,12 +127,22 @@ private:
vvertexp->modp()->level(vvertexp->rank()+1); vvertexp->modp()->level(vvertexp->rank()+1);
} }
} }
if (v3Global.opt.topModule()!=""
&& !m_topVertexp) {
v3error("Specified --top-module '"<<v3Global.opt.topModule()<<"' was not found in design.");
}
} }
virtual void visit(AstModule* nodep, AstNUser*) { virtual void visit(AstModule* nodep, AstNUser*) {
// Module: Pick up modnames, so we can resolve cells later // Module: Pick up modnames, so we can resolve cells later
m_modp = nodep; m_modp = nodep;
UINFO(2,"Link Module: "<<nodep<<endl); UINFO(2,"Link Module: "<<nodep<<endl);
if (nodep->inLibrary()) { bool topMatch = (v3Global.opt.topModule()==nodep->name());
if (topMatch) m_topVertexp = vertex(nodep);
if (v3Global.opt.topModule()==""
? nodep->inLibrary() // Library cells are lower
: !topMatch) { // Any non-specified module is lower
// Put under a fake vertex so that the graph ranking won't indicate
// this is a top level module
if (!m_libVertexp) m_libVertexp = new LibraryVertex(&m_graph); if (!m_libVertexp) m_libVertexp = new LibraryVertex(&m_graph);
new V3GraphEdge(&m_graph, m_libVertexp, vertex(nodep), 1, false); new V3GraphEdge(&m_graph, m_libVertexp, vertex(nodep), 1, false);
} }
@ -231,9 +242,9 @@ public:
LinkCellsVisitor() { LinkCellsVisitor() {
m_modp = NULL; m_modp = NULL;
m_libVertexp = NULL; m_libVertexp = NULL;
m_topVertexp = NULL;
} }
virtual ~LinkCellsVisitor() { virtual ~LinkCellsVisitor() {}
}
void main(AstNetlist* rootp) { void main(AstNetlist* rootp) {
rootp->accept(*this); rootp->accept(*this);
} }

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@ -50,20 +50,6 @@ void V3LinkLevel::modSortByLevel() {
// Calculate levels again in case we added modules // Calculate levels again in case we added modules
UINFO(2,"modSortByLevel()\n"); UINFO(2,"modSortByLevel()\n");
if (v3Global.opt.topModule()!="") {
bool hit = false;
for (AstModule* nodep = v3Global.rootp()->modulesp(); nodep; nodep=nodep->nextp()->castModule()) {
if (nodep->name() == v3Global.opt.topModule()) {
hit = true;
} else {
nodep->level(3);
}
}
if (!hit) {
v3error("Specified --top-module '"<<v3Global.opt.topModule()<<"' was not found in design.");
}
}
// level() was computed for us in V3LinkCells // level() was computed for us in V3LinkCells
vector<AstModule*> vec; vector<AstModule*> vec;

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@ -7,7 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# General Public License or the Perl Artistic License. # General Public License or the Perl Artistic License.
compile ( compile (
v_flags2 => ["--top-module b"], v_flags2 => ["--top-module b "],
) if $Self->{v3}; ) if $Self->{v3};
execute ( execute (