From 3d85cbe6b56c33ce4876cbbbe320175993fb49c8 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 7 Apr 2009 13:23:25 -0400
Subject: [PATCH] Fix "cloning" error with -y/--top-module, bug76.

---
 Changes                            |  4 ++++
 src/V3LinkCells.cpp                | 17 ++++++++++++++---
 src/V3LinkLevel.cpp                | 14 --------------
 test_regress/t/t_flag_topmodule.pl |  2 +-
 4 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/Changes b/Changes
index 074116d37..c65a9e569 100644
--- a/Changes
+++ b/Changes
@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.7***
+
+**** Fix "cloning" error with -y/--top-module, bug76. [Dimitris Nalbantis]
+
 * Verilator 3.702 2009/03/28
 
 ***  Add --pins-bv option to use sc_bv for all ports.  [Brian Small]
diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp
index 12a851f0b..166b9468d 100644
--- a/src/V3LinkCells.cpp
+++ b/src/V3LinkCells.cpp
@@ -95,6 +95,7 @@ private:
     V3SymTable  m_mods;		// Symbol table of all module names
     LinkCellsGraph	m_graph;	// Linked graph of all cell interconnects
     LibraryVertex*	m_libVertexp;	// Vertex at root of all libraries
+    V3GraphVertex*	m_topVertexp;	// Vertex of top module
 
     static int debug() {
 	static int level = -1;
@@ -126,12 +127,22 @@ private:
 		vvertexp->modp()->level(vvertexp->rank()+1);
 	    }
 	}
+	if (v3Global.opt.topModule()!=""
+	    && !m_topVertexp) {
+	    v3error("Specified --top-module '"<<v3Global.opt.topModule()<<"' was not found in design.");
+	}
     }
     virtual void visit(AstModule* nodep, AstNUser*) {
 	// Module: Pick up modnames, so we can resolve cells later
 	m_modp = nodep;
 	UINFO(2,"Link Module: "<<nodep<<endl);
-	if (nodep->inLibrary()) {
+	bool topMatch = (v3Global.opt.topModule()==nodep->name());
+	if (topMatch) m_topVertexp = vertex(nodep);
+	if (v3Global.opt.topModule()==""
+	    ? nodep->inLibrary()   // Library cells are lower
+	    : !topMatch) {  // Any non-specified module is lower
+	    // Put under a fake vertex so that the graph ranking won't indicate
+	    // this is a top level module
 	    if (!m_libVertexp) m_libVertexp = new LibraryVertex(&m_graph);
 	    new V3GraphEdge(&m_graph, m_libVertexp, vertex(nodep), 1, false);
 	}
@@ -231,9 +242,9 @@ public:
     LinkCellsVisitor() {
 	m_modp = NULL;
 	m_libVertexp = NULL;
+	m_topVertexp = NULL;
     }
-    virtual ~LinkCellsVisitor() {
-    }
+    virtual ~LinkCellsVisitor() {}
     void main(AstNetlist* rootp) {
 	rootp->accept(*this);
     }
diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp
index 12e96cd85..86a25f592 100644
--- a/src/V3LinkLevel.cpp
+++ b/src/V3LinkLevel.cpp
@@ -50,20 +50,6 @@ void V3LinkLevel::modSortByLevel() {
     // Calculate levels again in case we added modules
     UINFO(2,"modSortByLevel()\n");
 
-    if (v3Global.opt.topModule()!="") {
-	bool hit = false;
-	for (AstModule* nodep = v3Global.rootp()->modulesp(); nodep; nodep=nodep->nextp()->castModule()) {
-	    if (nodep->name() == v3Global.opt.topModule()) {
-		hit = true;
-	    } else {
-		nodep->level(3);
-	    }
-	}
-	if (!hit) {
-	    v3error("Specified --top-module '"<<v3Global.opt.topModule()<<"' was not found in design.");
-	}
-    }
-
     // level() was computed for us in V3LinkCells
 
     vector<AstModule*> vec;
diff --git a/test_regress/t/t_flag_topmodule.pl b/test_regress/t/t_flag_topmodule.pl
index da2d5fe95..80452f52d 100755
--- a/test_regress/t/t_flag_topmodule.pl
+++ b/test_regress/t/t_flag_topmodule.pl
@@ -7,7 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # General Public License or the Perl Artistic License.
 
 compile (
-	 v_flags2 => ["--top-module b"],
+	 v_flags2 => ["--top-module b "],
 	 ) if $Self->{v3};
 
 execute (