luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Commentary (#7916)

This commit is contained in:
Wilson Snyder 2026-07-10 08:37:52 -04:00
parent feb2fe0d94
commit 3bd04a70bd
1 changed files with 11 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
docs/guide/connecting.rst
View File

@ -92,13 +92,17 @@ model.
Refer to ``examples/make_tracing_c`` in the distribution for a detailed Refer to ``examples/make_tracing_c`` in the distribution for a detailed
commented example. commented example.
Top level IO signals are read and written as members of the model. You call Top level IO signals are read and written as members of the model. All
the model's ``eval()`` method to evaluate the model. When the simulation is inputs must be sanitized, that is have no bits set above those
complete call the model's ``final()`` method to execute any SystemVerilog corresponding to the width of the Verilog construct;
final blocks, and complete any assertions. If using :vlopt:`--timing`, :vlopt:`--runtime-debug` will assert this is correct.
there are two additional functions for checking if there are any events
pending in the simulation due to delays, and for retrieving the simulation Call the model's ``eval()`` method to evaluate the model. When the
time of the next delayed event. See :ref:`Evaluation Loop`. simulation is complete call the model's ``final()`` method to execute any
SystemVerilog final blocks, and complete any assertions. If using
:vlopt:`--timing`, there are two additional functions for checking if there
are any events pending in the simulation due to delays, and for retrieving
the simulation time of the next delayed event. See :ref:`Evaluation Loop`.
Connecting to SystemC Connecting to SystemC