From 3bd04a70bd418803c7e2eab87e19b64821563acc Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 10 Jul 2026 08:37:52 -0400 Subject: [PATCH] Commentary (#7916) --- docs/guide/connecting.rst | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst index 35ec9742b..3d1fafd5d 100644 --- a/docs/guide/connecting.rst +++ b/docs/guide/connecting.rst @@ -92,13 +92,17 @@ model. Refer to ``examples/make_tracing_c`` in the distribution for a detailed commented example. -Top level IO signals are read and written as members of the model. You call -the model's ``eval()`` method to evaluate the model. When the simulation is -complete call the model's ``final()`` method to execute any SystemVerilog -final blocks, and complete any assertions. If using :vlopt:`--timing`, -there are two additional functions for checking if there are any events -pending in the simulation due to delays, and for retrieving the simulation -time of the next delayed event. See :ref:`Evaluation Loop`. +Top level IO signals are read and written as members of the model. All +inputs must be sanitized, that is have no bits set above those +corresponding to the width of the Verilog construct; +:vlopt:`--runtime-debug` will assert this is correct. + +Call the model's ``eval()`` method to evaluate the model. When the +simulation is complete call the model's ``final()`` method to execute any +SystemVerilog final blocks, and complete any assertions. If using +:vlopt:`--timing`, there are two additional functions for checking if there +are any events pending in the simulation due to delays, and for retrieving +the simulation time of the next delayed event. See :ref:`Evaluation Loop`. Connecting to SystemC