diff --git a/Changes b/Changes
index 328f4abd8..12d810a8a 100644
--- a/Changes
+++ b/Changes
@@ -20,6 +20,7 @@ Verilator 5.045 devel
 * Fix MULTIDRIVEN with task and default driver (#4045) (#6858). [em2machine]
 * Fix use-after-free error (#6846). [Matthew Ballance]
 * Fix dynamic array elements passed to ref argument (#6877). [Ryszard Rozak, Antmicro Ltd.]
+* Fix WIDTHEXTEND suppression on add/sub with single-bit signal. [Dan Katz]
 
 
 Verilator 5.044 2026-01-01
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 24d6a3bda..e3dd541af 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -7694,6 +7694,11 @@ class WidthVisitor final : public VNVisitor {
                 // Warn if user wants extra bit from carry
                 if (subDTypep->widthMin() == (nodep->lhsp()->widthMin() + 1)) lhsWarn = false;
                 if (subDTypep->widthMin() == (nodep->rhsp()->widthMin() + 1)) rhsWarn = false;
+                if (VN_IS(nodep, Add) && nodep->lhsp()->width() == 1
+                    && nodep->rhsp()->width() != 1)
+                    lhsWarn = false;  // do_increment + ...
+                if (nodep->rhsp()->width() == 1 && nodep->lhsp()->width() != 1)
+                    rhsWarn = false;  // ... + do_increment
             } else if (VN_IS(nodep, Mul) || VN_IS(nodep, MulS)) {
                 if (subDTypep->widthMin() >= (nodep->lhsp()->widthMin())) lhsWarn = false;
                 if (subDTypep->widthMin() >= (nodep->rhsp()->widthMin())) rhsWarn = false;
diff --git a/test_regress/t/t_lint_width.v b/test_regress/t/t_lint_width.v
index 0931dd1b2..0ab62537d 100644
--- a/test_regress/t/t_lint_width.v
+++ b/test_regress/t/t_lint_width.v
@@ -16,6 +16,11 @@ module t ();
    wire [4:0] neg5 = - five;
    wire [5:0] neg6 = - five;
 
+   wire inc = 1'b1;
+   wire [4:0] sumd = inc + five;
+   wire [4:0] sume = five + inc;
+   wire [4:0] nege = five - inc;
+
    // Relatively harmless < or <= compared with something less wide
    localparam [1:0] THREE = 3;
    int        a;