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Support SystemC time resolution with step 10/100 (#6633) (#6715)

This commit is contained in:
Aliaksei Chapyzhenka 2025-12-09 16:34:29 -08:00 committed by GitHub
parent 075d624b29
commit 3b0db630c1
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GPG Key ID: B5690EEEBB952194
4 changed files with 40 additions and 15 deletions
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19
include/verilated.h
View File

@ -1027,18 +1027,13 @@ void VerilatedContext::timeprecision(int value) VL_MT_SAFE {
m_s.m_timeprecision = value;
#if VM_SC
const sc_core::sc_time sc_res = sc_core::sc_get_time_resolution();
if (sc_res == sc_core::sc_time(1, sc_core::SC_SEC)) {
sc_prec = 0;
} else if (sc_res == sc_core::sc_time(1, sc_core::SC_MS)) {
sc_prec = 3;
} else if (sc_res == sc_core::sc_time(1, sc_core::SC_US)) {
sc_prec = 6;
} else if (sc_res == sc_core::sc_time(1, sc_core::SC_NS)) {
sc_prec = 9;
} else if (sc_res == sc_core::sc_time(1, sc_core::SC_PS)) {
sc_prec = 12;
} else if (sc_res == sc_core::sc_time(1, sc_core::SC_FS)) {
sc_prec = 15;
double mult = 1.0;
for (int i = 0; i < 16; i++) {
if (sc_res == sc_core::sc_time(mult, sc_core::SC_FS)) {
sc_prec = 15 - i;
break;
}
mult *= 10.0;
}
// SC_AS, SC_ZS, SC_YS not supported as no Verilog equivalent; will error below
#endif

9
test_regress/driver.py
View File

@ -712,6 +712,7 @@ class VlTest:
self.make_pli = 0 # need to compile pli
self.make_top_shell = 1 # Make a default __top.v file
self.rerunnable = True # Rerun if fails
self.sc_time_resolution_multiplier = 1 # Time resolution multiplier
self.sc_time_resolution = "SC_PS" # Keep - PS is SystemC default
self.sim_time = 1100 # simulation time units for main wrapper
self.threads = -1 # --threads (negative means auto based on scenario)
@ -2096,7 +2097,8 @@ class VlTest:
fh.write(" sc_signal<sc_dt::sc_uint<1>> clk;\n")
else:
fh.write(" sc_signal<bool> clk;\n")
fh.write(" sc_set_time_resolution(1, " + self.sc_time_resolution + ");\n")
fh.write(" sc_set_time_resolution(" + str(self.sc_time_resolution_multiplier) +
", " + self.sc_time_resolution + ");\n")
fh.write(" sc_time sim_time(" + str(self.sim_time) + ", " +
self.sc_time_resolution + ");\n")
else:
@ -2183,7 +2185,8 @@ class VlTest:
if 'clk' in self._inputs:
fh.write(" " + setp + "clk = false;\n")
if not timing_loop:
self._print_advance_time(fh, 10, None)
start_time = 10
self._print_advance_time(fh, start_time * self.sc_time_resolution_multiplier, None)
fh.write(" }\n")
timestamp = "sc_time_stamp()" if self.sc else "contextp->time()"
@ -2240,7 +2243,7 @@ class VlTest:
fh.write(" topp.reset(nullptr);\n")
fh.write(" return 0;\n")
fh.write(" }\n")
self._print_advance_time(fh, 1, action)
self._print_advance_time(fh, self.sc_time_resolution_multiplier, action)
if self.benchmarksim:
fh.write(" if (VL_UNLIKELY(!warm)) {\n")
fh.write(" starttime = std::chrono::steady_clock::now();\n")

5
test_regress/t/t_time_sc_10_ns.out Normal file
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@ -0,0 +1,5 @@
Warning: (W516) default time unit changed to time resolution
Time scale of t is 10ns / 10ns
[20] In top.t: Hi - expect this is 20
*-* All Finished *-*

22
test_regress/t/t_time_sc_10_ns.py Executable file
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@ -0,0 +1,22 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_time_sc.v"
test.sc_time_resolution = 'SC_NS'
test.sc_time_resolution_multiplier = 10
test.compile(verilator_flags2=['-sc', '-timescale 10ns/10ns', '+define+TEST_EXPECT=200ns'])
test.execute(expect_filename=test.golden_filename)
test.passes()