From 3b0db630c19e730b34eab212af60b4d88c1ded7d Mon Sep 17 00:00:00 2001 From: Aliaksei Chapyzhenka Date: Tue, 9 Dec 2025 16:34:29 -0800 Subject: [PATCH] Support SystemC time resolution with step 10/100 (#6633) (#6715) --- include/verilated.h | 19 +++++++------------ test_regress/driver.py | 9 ++++++--- test_regress/t/t_time_sc_10_ns.out | 5 +++++ test_regress/t/t_time_sc_10_ns.py | 22 ++++++++++++++++++++++ 4 files changed, 40 insertions(+), 15 deletions(-) create mode 100644 test_regress/t/t_time_sc_10_ns.out create mode 100755 test_regress/t/t_time_sc_10_ns.py diff --git a/include/verilated.h b/include/verilated.h index 77c655689..02c022176 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -1027,18 +1027,13 @@ void VerilatedContext::timeprecision(int value) VL_MT_SAFE { m_s.m_timeprecision = value; #if VM_SC const sc_core::sc_time sc_res = sc_core::sc_get_time_resolution(); - if (sc_res == sc_core::sc_time(1, sc_core::SC_SEC)) { - sc_prec = 0; - } else if (sc_res == sc_core::sc_time(1, sc_core::SC_MS)) { - sc_prec = 3; - } else if (sc_res == sc_core::sc_time(1, sc_core::SC_US)) { - sc_prec = 6; - } else if (sc_res == sc_core::sc_time(1, sc_core::SC_NS)) { - sc_prec = 9; - } else if (sc_res == sc_core::sc_time(1, sc_core::SC_PS)) { - sc_prec = 12; - } else if (sc_res == sc_core::sc_time(1, sc_core::SC_FS)) { - sc_prec = 15; + double mult = 1.0; + for (int i = 0; i < 16; i++) { + if (sc_res == sc_core::sc_time(mult, sc_core::SC_FS)) { + sc_prec = 15 - i; + break; + } + mult *= 10.0; } // SC_AS, SC_ZS, SC_YS not supported as no Verilog equivalent; will error below #endif diff --git a/test_regress/driver.py b/test_regress/driver.py index 2a6314cc8..674727a92 100755 --- a/test_regress/driver.py +++ b/test_regress/driver.py @@ -712,6 +712,7 @@ class VlTest: self.make_pli = 0 # need to compile pli self.make_top_shell = 1 # Make a default __top.v file self.rerunnable = True # Rerun if fails + self.sc_time_resolution_multiplier = 1 # Time resolution multiplier self.sc_time_resolution = "SC_PS" # Keep - PS is SystemC default self.sim_time = 1100 # simulation time units for main wrapper self.threads = -1 # --threads (negative means auto based on scenario) @@ -2096,7 +2097,8 @@ class VlTest: fh.write(" sc_signal> clk;\n") else: fh.write(" sc_signal clk;\n") - fh.write(" sc_set_time_resolution(1, " + self.sc_time_resolution + ");\n") + fh.write(" sc_set_time_resolution(" + str(self.sc_time_resolution_multiplier) + + ", " + self.sc_time_resolution + ");\n") fh.write(" sc_time sim_time(" + str(self.sim_time) + ", " + self.sc_time_resolution + ");\n") else: @@ -2183,7 +2185,8 @@ class VlTest: if 'clk' in self._inputs: fh.write(" " + setp + "clk = false;\n") if not timing_loop: - self._print_advance_time(fh, 10, None) + start_time = 10 + self._print_advance_time(fh, start_time * self.sc_time_resolution_multiplier, None) fh.write(" }\n") timestamp = "sc_time_stamp()" if self.sc else "contextp->time()" @@ -2240,7 +2243,7 @@ class VlTest: fh.write(" topp.reset(nullptr);\n") fh.write(" return 0;\n") fh.write(" }\n") - self._print_advance_time(fh, 1, action) + self._print_advance_time(fh, self.sc_time_resolution_multiplier, action) if self.benchmarksim: fh.write(" if (VL_UNLIKELY(!warm)) {\n") fh.write(" starttime = std::chrono::steady_clock::now();\n") diff --git a/test_regress/t/t_time_sc_10_ns.out b/test_regress/t/t_time_sc_10_ns.out new file mode 100644 index 000000000..0c8487f8b --- /dev/null +++ b/test_regress/t/t_time_sc_10_ns.out @@ -0,0 +1,5 @@ + +Warning: (W516) default time unit changed to time resolution +Time scale of t is 10ns / 10ns +[20] In top.t: Hi - expect this is 20 +*-* All Finished *-* diff --git a/test_regress/t/t_time_sc_10_ns.py b/test_regress/t/t_time_sc_10_ns.py new file mode 100755 index 000000000..62ffd5f17 --- /dev/null +++ b/test_regress/t/t_time_sc_10_ns.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_time_sc.v" + +test.sc_time_resolution = 'SC_NS' +test.sc_time_resolution_multiplier = 10 + +test.compile(verilator_flags2=['-sc', '-timescale 10ns/10ns', '+define+TEST_EXPECT=200ns']) + +test.execute(expect_filename=test.golden_filename) + +test.passes()