Tests: Add t_lint_always_comb_automatic (#2862)

This commit is contained in:
Wilson Snyder 2025-09-28 21:23:15 -04:00
parent 21b42c4463
commit 3b049ab9ee
2 changed files with 38 additions and 0 deletions

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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint()
test.passes()

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (
input logic a,
input logic [7:0] b,
output logic [7:0] c
);
always_comb begin : p
c = b;
if (a) begin : x
automatic logic [7:0] n;
n = b;
n += 8'h01;
c = n;
end
end
endmodule