diff --git a/test_regress/t/t_lint_always_comb_automatic.py b/test_regress/t/t_lint_always_comb_automatic.py
new file mode 100755
index 000000000..cca4c9e73
--- /dev/null
+++ b/test_regress/t/t_lint_always_comb_automatic.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint()
+
+test.passes()
diff --git a/test_regress/t/t_lint_always_comb_automatic.v b/test_regress/t/t_lint_always_comb_automatic.v
new file mode 100644
index 000000000..7b0c4af70
--- /dev/null
+++ b/test_regress/t/t_lint_always_comb_automatic.v
@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (
+    input logic a,
+    input logic [7:0] b,
+    output logic [7:0] c
+);
+
+  always_comb begin : p
+    c = b;
+    if (a) begin : x
+      automatic logic [7:0] n;
+      n = b;
+      n += 8'h01;
+      c = n;
+    end
+  end
+endmodule