[#73220] add t_trace_enum_saif test

test_regress/t/t_trace_enum_saif.out

@@ -0,0 +1,26 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "t")
+(DATE "02-25-2025 13:59:21")
+(VENDOR "AxPy Inc")
+(PROGRAM_NAME "open_vcd2saif")
+(VERSION "v0")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 10)
+(INSTANCE top
+  (NET
+    (clk (T0 10) (T1 0) (TX 0) (TC 1))
+  )
+  (INSTANCE t
+    (NET
+      (clk (T0 10) (T1 0) (TX 0) (TC 1))
+    )
+    (INSTANCE sink
+      (NET
+      )
+    )
+  )
+)
+)

test_regress/t/t_trace_enum_saif.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_enum.v"
+
+test.compile(verilator_flags2=['--cc --trace-saif --output-split-ctrace 1'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()